JPS60114943A - Self diagnosis circuit - Google Patents

Abstract

PURPOSE:To attain efficient self-diagnosis with a test pattern generated automatically by providing a hardward operating other circuits except a firmware control circuit in the scan mode by means of a signal transmitted from the firmware control circuit. CONSTITUTION:A signal generated by an instruction of the firmware control circuit sets a scan flip-flop 202 through a signal line 204 to set a DMA control circuit 200 into the scan mode. A test data is set to a scan register 201 from an operation logical unit 111 and inputted to the DMA control circuit 200 in bit serial form. Moreover, the result of test is inputted also to the scan register 201 in bit serial form and inputted to the 2nd multiplexer 110. Thus, the firmware control circuit checks the result of test so as to attain self-diagnosis.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a self-diagnosis circuit for a VLSI peripheral control device.

(Prior art) Conventionally, the operation of scan mode in which 7 circuits and 70 circuits inside the VLSI are connected in a line during testing and the VLSI test is performed becomes difficult as the amount of logic elements inside the VLSI increases. It has become essential. These are 7 lip 70 lip yVL inside VLSI.
Since it is necessary to configure the vLSI to operate in scan mode regardless of signals from outside the vLSI, self-diagnosis cannot be performed by the firmware circuit inside the vLSI.

On the other hand, in firmware-controlled peripheral control devices, the function of performing self-diagnosis when the power is turned on or upon request from the host computer is partially achieved using an internal firmware control circuit, but this self-diagnosis test
It takes a huge amount of man-hours to create a gram.
It was difficult to create something with a high failure detection rate. However, the generation of test patterns using scan mode in VLSI has currently been automated to a very low level. Normally, when testing a single vLSI, a test pattern using such a scan canvas is used.

For a VLSI that has an internal firmware control circuit and other 71-ware circuits, there is no hardware to put the circuits other than the 71-ware control circuit into scan mode, so the logic of the VLSI It has not been possible to perform self-diagnosis by the firmware control circuit inside the VLSI using a test pattern that can be automatically generated. Therefore, there are problems in that it takes a lot of man-hours to create a test program for self-diagnosis, and the failure detection rate is very low.

(Objective of the Invention) The object of the present invention is to provide a VLSI that has a firmware control circuit and other hardware circuits internally, by a signal sent from the firmware control circuit.
By providing hardware to operate circuits other than the firmware control circuit inside the LSI in scan mode, it is possible to perform self-sieving efficiently using test patterns that can be automatically generated. The object of the present invention is to provide a self-diagnosis circuit constructed according to the present invention.

(Structure of the Invention) The VLSI self-diagnosis circuit according to the present invention is included in a peripheral control device configured by VLSI, and includes a firmware control circuit and a DMA1'1ilJ1 circuit.

The firmware control circuit is for executing microprograms. The DMA control circuit is for controlling DMA transfers between the bus and peripheral devices.

In the present invention, as described above, 1) the 7 lip-flops inside the VLS1 are connected in a row by the signals input from the outside of the 5VLSI, and the firmware control circuit is connected by the signals sent from the firmware control circuit. It is constructed by connecting flip-flops in a row except for flip-flops.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a peripheral control device equipped with a self-diagnosis circuit according to the present invention, and FIG. 2 is a diagram showing details of an embodiment of the self-diagnosis device according to the present invention.

In FIG. 1, 1 is a bus, 2 is a bus transceiver, and 6 is a bus transceiver.
is a peripheral device, 4 is a ROM, 5 is a sequencer, 6 is a clock generator, 7 is a VLSI, f3 is a memory, Q, 1
01 and 105 are the first and second registers, respectively.
02, 104, and 108 are first to third selectors, 10 is a FIFO type register, 106 is an address counter, 107 is a range counter, and 109 and 110 are first
and a second multiplexer, 111 is an arithmetic logic unit, 112 is an accumulator, 113 is a memory address register, and 203 is a scan control circuit.

In FIG. 1, one embodiment of the self-diagnosis device according to the present invention, a peripheral control device 6 equipped with all the embodiments includes a path transceiver 2,
ROM 4, sequencer 5, clock generator 6,
It is composed of a VLSI 7 and a memory 8, and controls data transfer between the bus 1 and the peripheral device 6.

When testing VLSI7 alone,
The control line 601 connects the entire scan control circuit 203 to V.
All 7 lip-flops inside the LSI 7 are put into scan mode and tested. However, if the VLSI 7 is incorporated in a peripheral control device, this control line 601 is not used. This is because the VLSI 7 occupies most of the logic section of the peripheral control device, so if all of the VLSI 7 are placed in scan mode, all self-diagnosis operations cannot be performed.

Therefore, in FIG. 1, the first register 101, the second register 105, the address counter 106, the range counter 107 are all scanned, and in addition, the first selector 102 is used.

A test program is executed for the FIFO type register 106, the second selector 104, and the third selector 108 to self-diagnose their normality.

The above test program is stored in ROM4,
ROM 4, sequencer 5, clock generator 6,
In addition to the memory 8, there is also a firmware control circuit inside the LSI that includes a first multiplexer 109, a second multiplexer 110, an arithmetic logic unit 111, an accumulator 112, and a memory address register 116. 701.

FIG. 2 is a detailed block diagram of the self-diagnosis device shown in FIG. 1.

In FIG. 2, 200 is a DMA control circuit, 201 is a scan register, 202 is a scan flip-flop,
20ro is cut by the scan control circuit.

Next, the operation of this embodiment will be explained with reference to FIG.

In FIG. 2, the DMA control circuit 200 includes the first register 101 and the second register 105 in FIG.
Consisting of an address counter 106, a register counter 107, a first selector 102, a FIFO type register 106, a second selector 104, and a third selector 108, the signal is generated according to instructions from the firmware control circuit. sets the scan flip-flop 202 through the signal line 204 and sets the DMA control circuit 200 to scan mode. Further, test data is set in the scan register 201 from the arithmetic logic unit 111 inside the firmware control circuit, and is input to the DMA control circuit 200 in bit serial form. The test result is also input bit-serial to the scan register 201, and then input to the second multiplexer 110 inside the firmware control circuit. This allows the firmware control circuit to check the test results and perform self-diagnosis.

(Effects of the Invention) As explained above, the present invention is a VLSI having a firmware control circuit and other hardware, and is configured to include hardware for setting the parts other than the firmware control circuit to scan mode. By doing, p, V
This has the advantage that hardware other than the firmware control circuit can be self-diagnosed using a test pattern that can be automatically generated from logical data used during LSI design.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a peripheral control device including an embodiment of a self-diagnosis device according to the present invention. FIG. 2 is a block diagram showing details of the self-diagnosis device shown in FIG. 1. 1・e・path 2・1111 path transceiver 3・・φ peripheral device 4, ROM 51・sequencer 6・・clock generator 7・−・VLS I 8・・memory 101.105・φ・register 102 .104,108...Selector 106...-F
IFO type register 106...Address counter 107...Fist range counter 109t11o...Multiplexer 111...1 Arithmetic logic unit 112...Accumulator 113...Memory address register 200...DMAIIJ control circuit 201... Scan register 202φ...Scan flip-flop 206...φ Scan control circuit 210...Firmware control circuit 204φ...Signal line RO01 @-control line Patent applicant: NEC Corporation Representative, Patent attorney Hisashi Inoro

Claims (1)

[Claims] VL included in a peripheral control device composed of multiple VLSIs
The SI self-diagnosis circuit includes a firmware control circuit for executing a microprogram and a DMA control circuit for controlling DMA transfer between a bus and a peripheral device, and includes a signal input from the outside of the VLSI. According to the present invention, the flip-flops inside the VLSI are connected in a line, and seven flip-flops other than the firmware control circuit are connected in a line by a signal sent from the firmware control circuit. Diagnostic circuit.