JPS60113474A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60113474A JPS60113474A JP58220597A JP22059783A JPS60113474A JP S60113474 A JPS60113474 A JP S60113474A JP 58220597 A JP58220597 A JP 58220597A JP 22059783 A JP22059783 A JP 22059783A JP S60113474 A JPS60113474 A JP S60113474A
- Authority
- JP
- Japan
- Prior art keywords
- film
- ferroelectric polymer
- polymer film
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229920006254 polymer film Polymers 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 90
- 239000002033 PVDF binder Substances 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 6
- 229920002981 polyvinylidene fluoride Polymers 0.000 claims description 6
- BQCIDUSAKPWEOX-UHFFFAOYSA-N 1,1-Difluoroethene Chemical compound FC(F)=C BQCIDUSAKPWEOX-UHFFFAOYSA-N 0.000 claims description 5
- 229920001577 copolymer Polymers 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000010287 polarization Effects 0.000 abstract description 19
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000005669 field effect Effects 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- ZMXDDKWLCZADIW-UHFFFAOYSA-N N,N-Dimethylformamide Chemical compound CN(C)C=O ZMXDDKWLCZADIW-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005264 electron capture Effects 0.000 description 1
- 230000005621 ferroelectricity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
不発明は、情報の電気的書き込み、書き替え、および読
み出しが可能で、かつ電源を切った後も情報の記憶全維
持できる、強誘電性材料を用いた半導体記憶装置及びそ
の製造方法に関する。[Detailed Description of the Invention] (Industrial Application Field) The invention is based on ferroelectric properties that allow information to be electrically written, rewritten, and read, and that retains all information even after the power is turned off. The present invention relates to a semiconductor memory device using the material and a method for manufacturing the same.
(従来技術)
従来のこの種の装置全実現するため、文献〔1〕(Y、
Higuma、 Y、 Matsui、 M、 Ok
uyama、 T、 Nakagawa and Y、
Hamakawa : Japanese Jour
nal ofApplied Physics、vol
、17 (1978)Supplement17−1.
pp、 209−214)に記載されている構造の半
導体装置が提案されている。第1図に、その製法2よび
構造を示し、以下説明する。(Prior art) In order to realize all the conventional devices of this kind, reference [1] (Y,
Higuma, Y, Matsui, M, Ok
uyama, T., Nakagawa and Y.
Hamakawa: Japanese Jour
nal of Applied Physics, vol.
, 17 (1978) Supplement 17-1.
A semiconductor device having the structure described in (pp. 209-214) has been proposed. FIG. 1 shows its manufacturing method 2 and structure, which will be explained below.
第1図(4)に示すように、n型半導体基板1上に不純
物拡散によってp型層2を形成する。次に、第1図の)
に示すように、フォトリソグラフィ技術を用いてn型基
板1に至る溝3會形成することにより、ソース4、ドレ
イン5を形成する。次に、高周波スパッタ法により、P
LZT(鉛、ランタン、ジルコニウム、チタンを構成元
素とする無機強誘電性物質)膜6を堆積し、フォトリソ
グラフィ技術を用いて加工することにより、第1図(C
)に示す構造を得る。次に、金属膜を堆積し、これ全フ
ォトリソグラフィ技術により加工してゲート電極7およ
びソース・ドレインの配線8全形成し、第1図aに示す
構造全得る。As shown in FIG. 1(4), a p-type layer 2 is formed on an n-type semiconductor substrate 1 by impurity diffusion. Next, in Figure 1)
As shown in FIG. 2, a source 4 and a drain 5 are formed by forming grooves 3 that reach the n-type substrate 1 using photolithography. Next, by high frequency sputtering method, P
By depositing an LZT (inorganic ferroelectric substance whose constituent elements are lead, lanthanum, zirconium, and titanium) film 6 and processing it using photolithography, the structure shown in FIG.
) obtain the structure shown. Next, a metal film is deposited and processed by photolithography to form the entire gate electrode 7 and source/drain wirings 8, thereby obtaining the entire structure shown in FIG. 1a.
第1図aに示す構造はゲート電極7、ソース4、ドレイ
ン5からなるMIS型電界効果トランジスタとなってい
る。文献〔1〕に述べられているように、PLZT膜6
は強誘電性會有するため、ゲート電極7とn型半導体基
板lの間に、ある方向に!し、絶対値が一定値以上であ
る電界を印加することにより、PLZT膜6を分極させ
ることができる。さらに、分極させるのに用いた電界と
、逆の方向會有し、絶対値が一定値以上である電界ケゲ
ート電極7とn型半導体基板10間に印加することにエ
フ、分極の方向全逆転させることができる。PLZT膜
6の強誘電性により分極は、電界ケ除いた後も維持され
る。PLZT膜6とn型半導体基板1の界面に2けるn
型半導体基板1の表面ポテンシャルはPLZT膜6の分
極の方向に対応して二つの値會とるため、第1図0)の
MIS型電界効果トランジスタは分極の方向に対応した
二つの閾値電圧を有する。従って、MIS型電界効果ト
ランジスタの二つの閾値電圧に情報(“0”、”1”)
全対応させれば、情報の書き込み、書き替え、および読
み出しが可能であり、かつ、電11fl切つた後も、情
報の記憶全維持させることができる。The structure shown in FIG. 1a is an MIS type field effect transistor consisting of a gate electrode 7, a source 4, and a drain 5. As stated in the document [1], the PLZT film 6
has a ferroelectric association, so there is a gap between the gate electrode 7 and the n-type semiconductor substrate l in a certain direction! However, by applying an electric field whose absolute value is a certain value or more, the PLZT film 6 can be polarized. Furthermore, by applying an electric field having a direction opposite to that used for polarization and having an absolute value of a certain value or more between the gate electrode 7 and the n-type semiconductor substrate 10, the direction of polarization is completely reversed. be able to. Due to the ferroelectricity of the PLZT film 6, polarization is maintained even after the electric field is removed. n at 2 at the interface between the PLZT film 6 and the n-type semiconductor substrate 1
Since the surface potential of the type semiconductor substrate 1 has two values corresponding to the polarization direction of the PLZT film 6, the MIS type field effect transistor shown in FIG. 1 (0) has two threshold voltages corresponding to the polarization direction. . Therefore, there is information (“0”, “1”) in the two threshold voltages of the MIS field effect transistor.
If it is fully compatible, it is possible to write, rewrite, and read information, and even after the power is turned off, the information can be fully stored.
以上説明した、従来提案されている構造の半導体装置は
、次の欠点があるため、未だ実用化されるに至っていな
い。The conventionally proposed semiconductor devices described above have the following drawbacks and have not yet been put into practical use.
その第一は、MIS型電界効果トランジスタの二つの閾
値電圧の差音十分大きくすることができないことである
。閾値電圧の差が小さいと、情報を誤って読み出す確率
が高くなり、半導体装置の信頼性を確保することができ
ない。二つの閾値電圧の差は、PLZT膜6の膜厚、残
留分極の大きさ寂よび比誘電率によって決まる。The first problem is that the difference between the two threshold voltages of MIS field effect transistors cannot be made sufficiently large. If the difference in threshold voltage is small, the probability of reading information incorrectly increases, making it impossible to ensure the reliability of the semiconductor device. The difference between the two threshold voltages is determined by the thickness of the PLZT film 6, the magnitude of residual polarization, and the dielectric constant.
ここで、PLZT膜6の膜厚ytとし、残留分極の大き
さ全Q、比誘電率ヲ68.真空の誘電率をε。とする。Here, the film thickness of the PLZT film 6 is yt, the total residual polarization is Q, and the dielectric constant is 68. The permittivity of vacuum is ε. shall be.
このとき、MIS型電界効果トランジスタの二つの閾値
゛電圧の差は、文献〔1〕に記載さnているように、2
・QΦ1/(ε8・ε。)で表わすことができる。PL
ZT膜の残留分極の大きさQは、文献〔1〕に記載され
ているように、7.7 uC/dであ勺、比誘電率εS
は約1000である。At this time, the difference between the two threshold voltages of the MIS field effect transistor is 2 as described in reference [1].
・It can be expressed as QΦ1/(ε8·ε.). P.L.
As described in literature [1], the magnitude Q of the residual polarization of the ZT film is 7.7 uC/d, and the relative dielectric constant εS
is approximately 1000.
残留分極の大きさQおよび比誘電率ε8はPLZT膜固
有の物性値であるため、大幅に変えることはできない。The magnitude Q of residual polarization and the dielectric constant ε8 are physical property values specific to the PLZT film, and therefore cannot be changed significantly.
従って、PLZT膜6の膜厚?例えば0.5μmとした
ときのMIS型電界効果トランジスタの二つの閾値電圧
の差は、上記計算式および数値によれば、9Vにしかな
らない。しかも、実際の情報の電気的書き替え時間では
、書き替え時間を短くするためPLZT膜6が完全には
分極していない状態で使用せざるを得ないこと全考慮す
ると、この閾値電圧差は、半導体装置の信頼性を確保す
るのに十分とは言えない。また、半導体装置を微細化す
るためPLZT膜6の膜厚を薄くすれば、閾値電圧の差
はtに比例して小さくなるため、閾値電圧の差はますま
す小さくなシ、情報を誤って読み出す確率が高くなる。Therefore, the thickness of the PLZT film 6? For example, when the thickness is 0.5 μm, the difference between the two threshold voltages of MIS field effect transistors is only 9 V according to the above calculation formula and numerical value. Moreover, in the actual electrical rewriting time of information, in order to shorten the rewriting time, the PLZT film 6 must be used in a state that is not completely polarized. Considering this, this threshold voltage difference is This cannot be said to be sufficient to ensure the reliability of semiconductor devices. Furthermore, if the thickness of the PLZT film 6 is made thinner in order to miniaturize semiconductor devices, the difference in threshold voltage will become smaller in proportion to t. The probability increases.
(発明の目的)
本発明はこnらの欠点全解決するために提案されたもの
で、強誘電性膜として強誘電性高分子膜?用い、さらに
この強誘電性高分子膜を二つの絶縁膜で挾んだ構造全採
用し、これによつて信頼性の高い不揮発性の半導体記憶
装置及びその袈造力法全提供すること?目的とする。(Objective of the Invention) The present invention has been proposed to solve all of these drawbacks. Furthermore, by employing a structure in which this ferroelectric polymer film is sandwiched between two insulating films, it is possible to provide a highly reliable nonvolatile semiconductor memory device and its fabrication method. purpose.
(発明の構成)
上記の目的を達成するため、本発明は半導体基板上に形
成された強誘電性高分子膜と、前記の強誘電性高分子膜
上に形成された導電性の膜よりなる電極とを備えること
全特徴とする半導体装置ケ発明の要旨とするものである
。(Structure of the Invention) In order to achieve the above object, the present invention comprises a ferroelectric polymer film formed on a semiconductor substrate and a conductive film formed on the ferroelectric polymer film. The gist of the invention is a semiconductor device characterized by comprising an electrode.
さらに本発明は半導体基板上に形成された第一の絶縁膜
と、前記の絶縁膜上に形成された強誘電性高分子膜と、
前記の強誘電性高分子膜上に形成された第二の絶縁膜と
、前記の第二の絶縁膜上に形成された導電性の膜よりな
る電極とを備えること全特徴とする半導体装置全発明の
要旨とするものである。Furthermore, the present invention includes a first insulating film formed on a semiconductor substrate, a ferroelectric polymer film formed on the insulating film,
A semiconductor device comprising: a second insulating film formed on the ferroelectric polymer film; and an electrode made of a conductive film formed on the second insulating film. This is the gist of the invention.
さらに不発明は半導体基板上に第一の絶縁膜全形成する
工程と、前記の絶縁膜上に強誘電性高分子を滴下して強
誘電性高分子の薄膜を形成する工程と、前記の強誘電性
高分子膜上に第二の絶縁膜全形成する工程と、前記の第
二の絶縁膜上に導電性の膜上形成し、ついでエツチング
加工して電極を形成する工程とを備えること全特徴とす
る半導体装置の製造方法全発明の要旨とするものである
。Furthermore, the invention includes a step of completely forming a first insulating film on a semiconductor substrate, a step of dropping a ferroelectric polymer onto the insulating film to form a thin film of the ferroelectric polymer, and a step of forming a thin film of the ferroelectric polymer on the insulating film. A step of forming a second insulating film entirely on the dielectric polymer film, and a step of forming a conductive film on the second insulating film and then etching it to form an electrode. This is the gist of the entire invention, which is a characterized method for manufacturing a semiconductor device.
次に本発明の実施例全添付図面について説明する。なお
実施例は一つの例示であって、本発明の精神全逸脱しな
い範囲で、種々の変更あるいは改良全行いうろことは言
うまでもない。Next, embodiments of the present invention will be described with reference to all attached drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.
まず、本発明の詳細な説明する。First, the present invention will be explained in detail.
第2図は、本発明の半導体装置の一実施例を示す。図に
2いて半導体基板1上に強誘電性高分子膜11が形成さ
れ、その上に導電膜からなるゲート電極7が形成さ才1
1、ゲート電極7の両側にソース4およびドレイン5が
形成さn7たMIS型電界効果トランジスタ構造となっ
ている。FIG. 2 shows an embodiment of the semiconductor device of the present invention. As shown in FIG. 2, a ferroelectric polymer film 11 is formed on a semiconductor substrate 1, and a gate electrode 7 made of a conductive film is formed thereon.
1. It has a MIS type field effect transistor structure in which a source 4 and a drain 5 are formed on both sides of a gate electrode 7.
第2図に示す構造のMIS型電界効果トランジスタでは
、第1図0に示した半導体装置と基本的には同じ原理に
より、情報の電気的書き込み、書き替え、読み出し、お
よび情報の記憶の維持が可能である。すなわち、強誘電
性高分子(7)
膜11ヲ、外部電界により分極させることができ、かつ
分極の方向全逆転させることができ、さらに高分子膜1
1の強誘電性により、分極の方向は、電界會除いた後も
維持さnる。半導体基板1と強誘電性高分子膜11の界
面に?ける半導体基板1の表面ポテンシャルは、強誘電
性高分子膜11の分極の方向によって2つの値をとるた
め、第2図のMIS型電界効果トランジスタは、分極の
方向に対応した2つの閾値電圧全有する。従って、閾値
電圧の大小に情報(″0″、”1#)全対応させれば、
情報の書き込み、書き替え、および読み出しが可能であ
り、かつ、電諒會切った後も、情報の記憶全維持させる
ことができる。The MIS type field effect transistor having the structure shown in FIG. 2 basically uses the same principle as the semiconductor device shown in FIG. It is possible. That is, the ferroelectric polymer (7) film 11 can be polarized by an external electric field, and the direction of polarization can be completely reversed.
Due to the ferroelectric property of 1, the direction of polarization is maintained even after the electric field is removed. At the interface between semiconductor substrate 1 and ferroelectric polymer film 11? Since the surface potential of the semiconductor substrate 1 in which the ferroelectric polymer film 11 is polarized takes two values depending on the polarization direction of the ferroelectric polymer film 11, the MIS field effect transistor shown in FIG. have Therefore, if all the information ("0", "1#") corresponds to the magnitude of the threshold voltage,
It is possible to write, rewrite, and read information, and the information can be maintained in its entirety even after the telephone conversation ends.
第2図に示した構造のMIS型電界効果トランジスタの
2つの閾値電圧の差は、強誘電性高分子膜11の膜厚、
残留分極の大きさ、および比誘電率によって決まる。前
述したように、強誘電性高分子膜11の膜厚をt、強誘
電性高分子膜の残留分極の大きさをQ5比誘電率t68
、真空の誘電率を匂とするとき、MIS型電界効果ト(
8)
ランジスタの2つの闇値電圧の差は、2・Q−t/(ε
8・ε。)と表すことができる。従って、残留分極の大
きさQ’に大きくするか、比誘電率εsk小さくすれば
閾値電圧の差を大きくできる。しかし、一般に強誘電性
膜の残留分極の大きさQはそれほど大きく変えることは
できない。そこで、本発明では、強誘電性高分子膜の比
誘電率がPLZT膜などの無機強誘電性膜に比べ一般に
数百倍の−であることに着目した。強誘電性膜6として
強誘電性高分子膜を用いることにより、ε8が小さくな
るため、上記2つの閾値電圧の差は著しく大きくなる。The difference between the two threshold voltages of the MIS field effect transistor having the structure shown in FIG. 2 is determined by the thickness of the ferroelectric polymer film 11,
Determined by the magnitude of residual polarization and relative dielectric constant. As mentioned above, the film thickness of the ferroelectric polymer film 11 is t, and the magnitude of the residual polarization of the ferroelectric polymer film is Q5 and the dielectric constant t68.
, MIS type field effect (
8) The difference between the two dark value voltages of the transistor is 2・Q-t/(ε
8・ε. )It can be expressed as. Therefore, the difference in threshold voltage can be increased by increasing the residual polarization to the magnitude Q' or by decreasing the relative dielectric constant εsk. However, in general, the magnitude Q of residual polarization of a ferroelectric film cannot be changed significantly. Therefore, in the present invention, we focused on the fact that the dielectric constant of a ferroelectric polymer film is generally several hundred times lower than that of an inorganic ferroelectric film such as a PLZT film. By using a ferroelectric polymer film as the ferroelectric film 6, ε8 becomes small, so the difference between the two threshold voltages becomes significantly large.
例えば、代表的な強誘電性高分子材料であるポリ弗化ビ
ニリデンの残留分極の大きさは、文献[2] (T、
Takahashi。For example, the magnitude of the residual polarization of polyvinylidene fluoride, a typical ferroelectric polymer material, is reported in Reference [2] (T,
Takahashi.
M、 1)ate、 E、 Fukuda : App
lied physics 1etters。M, 1)ate, E, Fukuda: App
Lied physics 1etters.
vol、 37. p、 791.(1980)に記載
されているように、約6μC/−であり、比誘電率は、
文献〔3〕(H,Qhgashi and K、 Ko
ga : Japanese Journalof A
pplied Physics vol、 21. T
)、 L455. (1982)に記載されているよう
に、6.2である。強誘電性膜の膜厚’k O,5μm
としたときのMIS型電界効果トランジスタの2つの閾
値電圧の差は、強誘電性@11としてポリ弗化ビニリチ
ンを用いた場合、閾値電圧の差は約1100vとなる。vol, 37. p, 791. (1980), it is about 6 μC/-, and the dielectric constant is:
Reference [3] (H, Qhgashi and K, Ko
ga: Japanese Journal of A
pplied Physics vol, 21. T
), L455. 6.2, as described in (1982). Film thickness of ferroelectric film 'kO, 5μm
When polyvinyritine fluoride is used as the ferroelectric @11, the difference in threshold voltage between the two MIS field effect transistors is approximately 1100V.
このように、無機強誘電性膜に替えて、比誘電率の極め
て小さい強誘電性高分子膜を用いることにより、MIS
型電界効果トランジスタの閾値電圧の差の計算値を、P
LZT膜を用いた半導体装置に比べ、百数十倍とするこ
とができ、従来提案さnている半導体装置の欠点全解決
できる。In this way, by using a ferroelectric polymer film with an extremely low dielectric constant in place of an inorganic ferroelectric film, MIS
The calculated value of the difference in threshold voltage of type field effect transistor is P
Compared to a semiconductor device using an LZT film, it can be made more than 100 times larger, and all the drawbacks of conventionally proposed semiconductor devices can be solved.
また、半導体装置の微細化のため、強誘電性膜11の膜
厚ケさらに薄くしても、実用上十分大きな閾値電圧差全
確保できる。In addition, even if the thickness of the ferroelectric film 11 is made thinner due to miniaturization of semiconductor devices, a practically large enough threshold voltage difference can be ensured.
強誘電性高分子膜11の材料としては、ポリ弗化ビニリ
デンあるいは弗化ビニリデン・3弗化工チレン共重合体
が、比誘電率が小で製造し易いため、適当である。As the material for the ferroelectric polymer film 11, polyvinylidene fluoride or vinylidene fluoride/trifluoroethylene copolymer is suitable because it has a small dielectric constant and is easy to manufacture.
MIS型電界効果トランジスタの閾値電圧の差全大きく
する目的は情報ケ誤って読み出す確率會小さくすること
、すなわち、半導体装置の信頼性を高めることにある。The purpose of increasing the difference in threshold voltages of MIS field effect transistors is to reduce the probability of erroneously reading information, that is, to improve the reliability of the semiconductor device.
しかしながら、第2図のように、強誘電性高分子膜11
と半導体基板1およびゲート電極7が直接液する構造全
相いた場合、情報の書き込み、書き替えのため強誘電性
高分子膜11に電界全かける際、強誘電性高分子膜11
に電子が注入され、この電子が膜中に捕獲されることに
より閾値電圧が変動する恐れがある。また、一般に高分
子膜中の電子捕獲準位は無機材料に比べ多いとされてい
る。このため、強誘電性高分子膜な用い、かつより信頼
性の高い半導体装置全実現するには、強誘電性高分子膜
への電子注入全防止でさる構造とする必をがある。However, as shown in FIG.
If there is a structure in which the semiconductor substrate 1 and the gate electrode 7 are directly in contact with each other, when applying a full electric field to the ferroelectric polymer film 11 for writing or rewriting information, the ferroelectric polymer film 11
When electrons are injected into the film and captured in the film, the threshold voltage may fluctuate. Furthermore, it is generally believed that there are more electron capture levels in polymer films than in inorganic materials. Therefore, in order to use a ferroelectric polymer film and to realize a more reliable semiconductor device, it is necessary to create a structure that completely prevents electron injection into the ferroelectric polymer film.
第3図は、本発明の半導体装置の他の実施例ケ示す。図
において半導体基板1上に第一の絶縁膜9が形成さ肛、
その上に強誘電性高分子膜11が形成さ扛、その上に第
二の絶縁膜12が形成され、その上に導電脱力)らなる
ゲート電極7が形成され、ゲート電極7の両側にソース
4およびドレイン5が形成された構造となっている。FIG. 3 shows another embodiment of the semiconductor device of the present invention. In the figure, a first insulating film 9 is formed on a semiconductor substrate 1;
A ferroelectric polymer film 11 is formed on it, a second insulating film 12 is formed on it, a gate electrode 7 made of conductive material is formed on both sides of the gate electrode 7, and a source is formed on both sides of the gate electrode 7. 4 and a drain 5 are formed.
(11)
すなわち、本発明の第二の実施例である半導体装置では
、強誘電性高分子膜11を第一の絶縁膜9および第二の
絶縁膜12で挾んだ構造を用いている。こnらの絶縁膜
はゲート電極7と半導体基板10間に電界が印加された
とき、強誘電性高分子膜11への電子注入全防止する役
割全果たす。このことにより、MIS型電界効果トラン
ジスタの閾値電圧の変動を改善できる。なお、第一の絶
縁膜9または第二の絶縁膜12のどちらかが無い場合で
も、強誘電性高分子膜11への電子注入は起こる。従っ
て、いずれの絶縁膜も強誘電性高分子膜の劣化を防ぐた
め、欠かすことができない。(11) That is, the semiconductor device according to the second embodiment of the present invention uses a structure in which a ferroelectric polymer film 11 is sandwiched between a first insulating film 9 and a second insulating film 12. These insulating films play the role of completely preventing electron injection into the ferroelectric polymer film 11 when an electric field is applied between the gate electrode 7 and the semiconductor substrate 10. This makes it possible to improve the fluctuation of the threshold voltage of the MIS field effect transistor. Note that even if either the first insulating film 9 or the second insulating film 12 is absent, electron injection into the ferroelectric polymer film 11 occurs. Therefore, both insulating films are indispensable in order to prevent deterioration of the ferroelectric polymer film.
本発明の一実施例における半導体装置の製法全第4図に
示す。まず、第4図(至)に示すように、p型半導体基
板l上に熱酸化法により、シリコン酸化膜からなり、膜
厚10〜100 nmの第一の絶縁膜9を形成する。次
に、フォトリソグラフィ技術により、レジストパタン1
0ヲ形成し、これをマスクとして燐または砒素をイオン
注入する(12)
ことにより、ソース4訃よびドレイン5を形成し、第4
図[F])に示す構造を得る。次に、レジストバタン1
0ヲ除去した後、p型半導体基板1を毎分300回転以
上の速度で回転させ、その上から、ポリ弗化ビニリデン
または弗化ビニリデン03弗化工チレン共重合体を例え
ばジメテルホルムアミドカどの溶媒に溶かした溶液を滴
下し、その後5秒以上回転を続けることにより、強誘電
性高分子膜11’(j形成し、第4図CC)に示す構造
を得る。次に、シリコン酸化膜からなり、膜厚10〜1
00 nmの第二の絶縁膜12ヲ堆積し、第4図(2)
に示す構造會得る。ポリ弗化ビニリデンや弗化ビニリデ
ン・3弗化工チレン共重合体の融点は約150℃である
から、強誘電性高分子膜11の変形を防ぐため、第二の
絶縁膜12の堆積は、高周波スパッタ法など、150℃
以下の温度で膜全堆積できる方法によらなければならな
い。次に、アルミニウム膜々どの金属膜全堆積し、フォ
トリングラフィ技術によりゲート電極7を形成し、次い
で第二の絶縁膜12および強誘電性高分子膜11會エツ
チング加工し、第4図■に示す構造を得る。次に、層間
絶縁膜13會堆積し、コンタクトホーシカ1丁を行った
後、金属膜を形成し、この金属映全フォトリソグラフィ
技術會用いてエツナング加工することにより、ソース・
ドレインの配線8およびゲート電極の配線14ヲ形成し
、最終的に第4図面に示す構造を得、半導体装置全完成
する。A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown in FIG. First, as shown in FIG. 4, a first insulating film 9 made of a silicon oxide film and having a thickness of 10 to 100 nm is formed on a p-type semiconductor substrate l by thermal oxidation. Next, resist pattern 1 is created using photolithography technology.
0 is formed, and using this as a mask, ions of phosphorus or arsenic are implanted (12) to form a source 4 and a drain 5.
The structure shown in Figure [F]) is obtained. Next, resist button 1
After removing 0, the p-type semiconductor substrate 1 is rotated at a speed of 300 revolutions per minute or more, and from thereon, polyvinylidene fluoride or vinylidene fluoride 03 fluorochemical tyrene copolymer is added to a solvent such as dimethylformamide. By dripping a solution dissolved in water and then continuing to rotate for 5 seconds or more, a ferroelectric polymer film 11' (j is formed, and the structure shown in FIG. 4 CC) is obtained. Next, it consists of a silicon oxide film with a film thickness of 10 to 1
A second insulating film 12 with a thickness of 0.00 nm is deposited as shown in FIG. 4(2).
We obtain the structure shown in Since the melting point of polyvinylidene fluoride and vinylidene fluoride/trifluoroethylene copolymer is approximately 150°C, the deposition of the second insulating film 12 is performed using high-frequency waves to prevent deformation of the ferroelectric polymer film 11. 150℃ such as sputtering method
The method must be such that the entire film can be deposited at a temperature below. Next, all metal films such as aluminum films are deposited, a gate electrode 7 is formed by photolithography technology, and then the second insulating film 12 and the ferroelectric polymer film 11 are etched, as shown in FIG. Obtain the structure shown. Next, 13 interlayer insulating films are deposited, one contact film is formed, a metal film is formed, and the source layer is etched using this metal film photolithography technology.
A drain wiring 8 and a gate electrode wiring 14 are formed, and finally the structure shown in the fourth drawing is obtained, and the semiconductor device is completely completed.
ポリ弗化ビニリデンや弗化ビニリデン・3弗化工チレン
共重合体の抗電界の値は、文献〔2〕2よび文献[3)
K x nば、約40 MV/m ”’C6ルア7>
ら、以上説明した製法により製作した半導体装置におい
て、絶対値20 V以上の電圧全半導体基板1とゲート
電極7Kかけることにより、情報の電気的書き込みおよ
び書き替えができる。書き替え時間を短くするため強誘
電性高分子膜1門が完全には分極していない状態で使用
する場合でも、2つの閾値電圧のうち、ひとつを少なく
とも100v以上、もうひとつ1−100V以下とする
ことができるため、情報を誤って読み出す恐れは無い。The coercive electric field values of polyvinylidene fluoride and vinylidene fluoride/trifluoro-modified tyrene copolymer are given in Reference [2] 2 and Reference [3].
K x n, approximately 40 MV/m ”'C6 Lua 7>
In the semiconductor device manufactured by the manufacturing method described above, information can be electrically written and rewritten by applying a voltage of 20 V or more in absolute value to the entire semiconductor substrate 1 and gate electrode 7K. In order to shorten the rewriting time, even if one ferroelectric polymer film is used in a state where it is not completely polarized, one of the two threshold voltages must be at least 100V or higher and the other 1-100V or lower. Therefore, there is no risk of reading information by mistake.
なお、本実施例は一つの例示であって、不発明の趣旨全
逸脱しない範囲で種々の変更あるいは改良を行いうる。Note that this embodiment is merely an example, and various changes and improvements can be made without departing from the spirit of the invention.
例えば、第一の絶縁膜9および第二の絶縁膜12は強誘
電性高分子膜11への電子注入を防止できる膜であれば
良く、半導体基板1としてシリコンを用いた場合は、第
一の絶縁@9として、熱酸化法により形成したシリコン
酸化膜以外にも、熱窒化法により形成した窒化シリコン
膜等を用いることができる。半導体基板1としてシリコ
ン以外の半導体を用いた場合は、第一の絶縁膜9として
、スパッタ法により堆積したシリコン酸化膜または窒化
シリコン膜等を用いることができる。また、第二の絶縁
膜12としては、スパッタ法により堆積した窒化シリコ
ン膜等も用いることができる。For example, the first insulating film 9 and the second insulating film 12 may be films that can prevent electron injection into the ferroelectric polymer film 11. As the insulation@9, in addition to a silicon oxide film formed by a thermal oxidation method, a silicon nitride film formed by a thermal nitridation method, etc. can be used. When a semiconductor other than silicon is used as the semiconductor substrate 1, a silicon oxide film, a silicon nitride film, or the like deposited by a sputtering method can be used as the first insulating film 9. Further, as the second insulating film 12, a silicon nitride film or the like deposited by sputtering can also be used.
(発明の効果)
以上説明したように、本発明によ九ば、信頼性の商い不
揮発性半導体記憶装置を実現できるという利点がある。(Effects of the Invention) As explained above, the present invention has the advantage that it is possible to realize a nonvolatile semiconductor memory device with high reliability.
(15)
上記実施例から明らかなように、本発明の半導体装置の
構造2よび製法は、多数の半導体装置全半導体基板上に
集積するのに適している。(15) As is clear from the above embodiments, the semiconductor device structure 2 and manufacturing method of the present invention are suitable for integrating a large number of semiconductor devices on all semiconductor substrates.
従って、本発明の半導体装置全素子として半導体乗積回
路装置全製作すれば、上記利点をより有効に活力1丁こ
とかできる。すなわち、本発明の半導体装置を素子とし
て半導体集積回路装置を製作し、これ全電子計算機や各
種の端末装置に用いれば、これらの装置の信頼性向上を
実現できる。Therefore, if the entire semiconductor multiplication circuit device is manufactured as all the semiconductor device elements of the present invention, the above advantages can be more effectively utilized in one device. That is, by manufacturing a semiconductor integrated circuit device using the semiconductor device of the present invention as an element and using it in all-electronic computers and various terminal devices, it is possible to improve the reliability of these devices.
第1図は、従来提案されている半導体装置の製法および
構造を示す。第2図は、本発明の一実施例である半導体
装置の構造を示す。第3図は、本発明の他の実施例であ
る半導体装置の構造を示す。第4図は、本発明の一実施
例における半導体装置の製法を示す。
l・・・・・・・・半導体基板
2・・・・・・・・・p型層
3・・・・・・・・・溝
(16)
4・・・・・・・・・ソース
5・・・・・・・・・ドレイン
6・・・・・・・・・PLZT膜
7・・・・・・・・・ゲート電極
8・・・・・・・・・ソース・ドレインの配線9・・・
・・・・・・第一の絶縁膜
10・・・・・・・・・レジストバタン11・・・・・
・・・・強誘電性高分子膜12・・・・・・・・・第二
の絶縁膜
13・・・・・・・・・層間絶縁膜
14・・・・・・・・・ゲート電極の配線特許出願人
日本電信電話公社
第1図
第2図
1/、
第3図FIG. 1 shows the manufacturing method and structure of a conventionally proposed semiconductor device. FIG. 2 shows the structure of a semiconductor device that is an embodiment of the present invention. FIG. 3 shows the structure of a semiconductor device according to another embodiment of the present invention. FIG. 4 shows a method for manufacturing a semiconductor device in one embodiment of the present invention. l...Semiconductor substrate 2...P-type layer 3...Groove (16) 4...Source 5 ......Drain 6...PLZT film 7...Gate electrode 8...Source/drain wiring 9 ...
......First insulating film 10...Resist baton 11...
...Ferroelectric polymer film 12...Second insulating film 13...Interlayer insulating film 14...Gate electrode wiring patent applicant
Nippon Telegraph and Telephone Public Corporation Figure 1 Figure 2 Figure 1/, Figure 3
Claims (4)
前記の強誘電性高分子膜上に形成された導電性の膜より
なる電極と金備えること全特徴とする半導体装置。(1) A ferroelectric polymer film formed on a semiconductor substrate,
A semiconductor device comprising: an electrode made of a conductive film formed on the ferroelectric polymer film; and gold.
の絶縁膜上に形成された強誘電性高分子膜と、前記の強
誘電性高分子膜上に形成された第二の絶縁膜と、前記の
第二の絶縁膜上に形成された導電性の膜よりなる電極と
を備えること全特徴とする半導体装置。(2) A first insulating film formed on a semiconductor substrate, a ferroelectric polymer film formed on the insulating film, and a second insulating film formed on the ferroelectric polymer film. A semiconductor device comprising: an insulating film; and an electrode made of a conductive film formed on the second insulating film.
電性高分子の薄膜を形成する工程と、(ハ)前記の強誘
電性高分子膜上に第二の絶縁膜全形成する工程と、 に)前記の第二の絶縁膜上に導電性の膜を形成し、つい
でエツチング加工して電極全形成する工程 と全備えることを特徴とする半導体装置の製造方法。(3) (a) A step of forming a first insulating film r on a semiconductor substrate; (b) A step of dropping a ferroelectric polymer onto the insulating film to form a thin film of ferroelectric polymer. (c) forming a second insulating film entirely on the ferroelectric polymer film; d) forming a conductive film on the second insulating film, and then etching it. 1. A method for manufacturing a semiconductor device, comprising a step of forming all electrodes.
は弗化ビニリデン・3弗化工チレン共重合体を用いるこ
とを特徴とする特許請求の範囲第1項または第2項記載
の半導体装置。(4) The semiconductor device according to claim 1 or 2, wherein polyvinylidene fluoride or vinylidene fluoride/trifluoro-modified tyrene copolymer is used as the ferroelectric polymer film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58220597A JPS60113474A (en) | 1983-11-25 | 1983-11-25 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58220597A JPS60113474A (en) | 1983-11-25 | 1983-11-25 | Semiconductor device and manufacture thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60113474A true JPS60113474A (en) | 1985-06-19 |
JPH0574232B2 JPH0574232B2 (en) | 1993-10-18 |
Family
ID=16753469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58220597A Granted JPS60113474A (en) | 1983-11-25 | 1983-11-25 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60113474A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0294571A (en) * | 1988-09-30 | 1990-04-05 | Toshiba Corp | Semiconductor device |
WO1998014989A1 (en) * | 1996-09-30 | 1998-04-09 | Siemens Aktiengesellschaft | Memory cell with a polymer capacitor |
GB2404785A (en) * | 2003-08-07 | 2005-02-09 | Univ Sheffield | Field effect transistor with organic ferroelectric gate insulator |
-
1983
- 1983-11-25 JP JP58220597A patent/JPS60113474A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0294571A (en) * | 1988-09-30 | 1990-04-05 | Toshiba Corp | Semiconductor device |
WO1998014989A1 (en) * | 1996-09-30 | 1998-04-09 | Siemens Aktiengesellschaft | Memory cell with a polymer capacitor |
GB2404785A (en) * | 2003-08-07 | 2005-02-09 | Univ Sheffield | Field effect transistor with organic ferroelectric gate insulator |
GB2406437A (en) * | 2003-08-07 | 2005-03-30 | Univ Sheffield | Field effect transistor with organic ferroelectric gate insulator |
Also Published As
Publication number | Publication date |
---|---|
JPH0574232B2 (en) | 1993-10-18 |
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