GB2404785A

GB2404785A - Field effect transistor with organic ferroelectric gate insulator

Info

Publication number: GB2404785A
Application number: GB0318522A
Authority: GB
Inventors: Raoul Schroeder; Martin Grell
Original assignee: University of Sheffield
Current assignee: University of Sheffield
Priority date: 2003-08-07
Filing date: 2003-08-07
Publication date: 2005-02-09
Also published as: GB2406437A; GB0406334D0; GB0318522D0

Abstract

A field effect transistor 1 comprises source and drain electrodes 6, 7 separated by a semiconductor body 5, and a gate electrode 3 separated from the semiconductor body 5 by a non-crystalline organic ferroelectric-like gate insulator 4. The semiconductor body 5 may comprise an organic or inorganic semiconductor material and the gate insulator 4 may be a polymer material. The device may be formed on a glass or plastic substrate 2 and is useful in non-volatile memory devices. The ferroelectric gate dielectric allows the voltage of an active matrix display transistor to be sustained without the use of a capacitor.

Description

2404785

1

FIELD EFFECT TRANSISTOR

The present invention relates to a field effect transistor and a method of fabricating the same, and more particularly but not exclusively, a field effect transistor for use in devices such as smart cards, liquid crystalline displays (LCDs) and organic light emitting displays (OLEDs).

A wide range of electronic devices use field effect transistors (FETs). For example, organic active matrix drivers for displays (both LCD and OLED) currently rely on memories consisting of a conventional field effect transistor and a capacitor. A significant drawback to such memory devices is that they require two components and the memory is volatile due to capacitor leakage.

The working principle of an FET is that the current between source and drain electrodes (which are separated by a semiconductor region) depends on the field present in the transistor which is itself controlled by applying a voltage to a gate insulator region via a gate electrode. The semiconductor body is separated from the gate electrode by the gate insulator region. When a sufficiently high voltage of a suitable polarity is applied to the gate electrode the associated electric field induces a charged accumulation layer in the semiconductor at the semiconductor-gate insulator interface of the device. Current will flow through the accumulation layer so as to put the device into an "on" state.

For an n-channel FET when a positive voltage is applied to the gate electrode a conducting accumulation layer is induced in the semiconductor body region adjacent to the gate insulator. The result of this is that if a voltage is applied to the drain electrode with respect to the source electrode then a current will flow. This current will flow from the drain to the source (following the convention on direction of current flow), adjacent to the body region, with electrons comprising the majority charge carriers (i.e. the electrons will flow from the source to the drain). It will be appreciated that for a p-channel FET a negative voltage must be applied to the gate electrode in order to induce an accumulation layer in the semiconductor body, and in this case the majority charge carriers making up the current from the drain to the source will be holes. When the voltage applied to the gate electrode is reduced below a threshold voltage the charged accumulation layer is removed and significant current can no longer flow from the drain to the source electrode through the body region of the FET, although there will still be a very low "off' current within the semiconductor body.

In order for a conventional FET (i.e. a FET having a dielectric insulating layer) to perform a memory function the voltage to the gate electrode must be sustained for the drain to source current to remain in its "on" state, which is achieved by applying a suitable gate voltage to the transistor incessantly, most typically by using a capacitor to store charge to help uphold the field in the FET. (C. D. Sheraw, et al., "Organic thin-film transistor-driven polymer-dispersed liquid crystal displays on flexible polymeric substrates", Appl Phys Lett. 80, p. 1088-1090 (2002)), (H.E.A. Huitema, et al., "Active-Matrix Displays Driven by Solution-Processed Polymeric Transistors", Adv. Mat. 14, p.1201-1204 (2002)). When a high voltage is applied to the gate electrode of the FET, current is allowed to flow between the drain and the source. A capacitor is charged and stores a charge equating to a logic high condition. When the gate control voltage is reduced below the threshold value the capacitor retains its charge for a period of time until the capacitor has discharged. In order for the logic high condition on the capacitor to be maintained the device must be periodically refreshed, before the capacitor has discharged significantly. The voltage across the capacitor must be read and if this equates to a logic high the gate voltage of the FET must be pulsed high again, to allow current to flow from the drain to the source, and replace the charge on the capacitor.

Within an active matrix display the voltage applied to the gate electrode of the FET must again be sustained in order to maintain the drain to source current in the "on" state. A capacitor is connected between the gate and source electrodes of the FET. The drain electrode is connected to one of the display electrodes. A separate voltage charges the capacitor such that the voltage at the gate electrode is sustained. In order to maintain a current to the display electrode it is necessary to periodically refresh the charge on the capacitor to sustain the gate voltage.

One way of overcoming some of the problems encountered when using capacitor-based transistor memory devices is to use a ferroelectric or ferroelectric-like material as the gate insulator. Ferroelectric materials possess a thermodynamic phase wherein they display a characteristic hysteresis loop for the electric displacement with respect to the applied electric field. When the electric field is increased in one direction the polarity of the material is aligned, and this alignment remains at least in part when the electric field is reduced back to zero. The material retains a remanent polarisation. To reverse this polarisation it is necessary to apply an electric field across the material in the opposite direction. The term ferroelectric-like will be used herein to refer to materials that exhibit a similar electric displacement / electric field hysteresis loop but do not necessarily possess the same thermodynamic properties.

The FET can then simply be poled by an initially applied voltage, with the insulator acting to keep the FET in the "on" state after the poling voltage is turned off (Tingkai Li et al., "Fabrication and characterization of a Pb5Ge30n one-transistor-memory device", Appl. Phys. Lett. 79, p. 1661-1663 (2001); M. W. J. Prins et al., "A ferroelectric transparent thin-film transistor", ,4/?/?/. Phys. Lett. 68, p. 3650-3652 (1996).).

The development of new transistor memory devices is of particular interest in applications, such as mobile telecommunications, where there is a desire to lower the power consumption and nonvolatile memories are desirable. Ferroelectric FETs typically employ an inorganic semiconductor layer in conjunction with an inorganic ferroelectric insulating layer. More recently, the development of organic memory devices, such as organic smart cards and organic active matrix drivers for displays has lead to the investigation of FETs incorporating organic semiconductors (such devices are referred to as Organic FETs or OFETs).

Significant problems have been encountered in fabricating single OFET memory devices using ferroelectric gate insulators which do not comprise a capacitor. This is due to the incompatibility of the processing steps required to construct the organic semiconductor layer and the crystal growing process normally required to ensure the insulating layer exhibits ferroelectric behaviour. One approach to overcoming such problems involves the incorporation of an 'intermediate crystal structure mediating layer'. However many of the resulting devices exhibit unacceptable performance. Fabrication of an OFET incorporating an inorganic ferroelectric insulator region and an organic semiconductor has been described (G. Velu et al., "Low driving voltages and memory effect in organic thin-film transistors with a ferroelectric gate insulator", Appl. Phys. Lett. 79, p. 659-661 (2001)). The inorganic insulator material (PbZrTiOs (PZT)) was deposited by radio frequency sputtering and then annealed at 625 °C for 30 min, which is both a lengthy and costly process. Moreover, while it would be desirable to incorporate a flexible organic substrate in an OFET (such as that produced by G. Velu et al.), the high temperature processing steps required to provide the inorganic ferroelectric insulator region are incompatible with organic substrates since the organic substrate is unlikely to withstand the high temperatures involved (e.g. 625 °C).

A further possible approach to overcoming problems relating to the fabrication of OFETs comprising organic semiconductors and inorganic ferroelectric insulators is to use an organic

insulator material. One organic material known to exhibit ferroelectric behaviour is polyvinylidenefluoride (PVDF). This material may exhibit ferroelectricity when formed into films by melt processing followed by stretching. Unfortunately PVDF films processed in that way are typically several microns thick and are therefore not suitable for FET construction which requires much thinner insulator layers to operate at commercially acceptable voltages. Moreover, PVDF films formed in this way are likely to be too rough for incorporation in to a FET. Furthermore, the ferroelectric behaviour exhibited by PVDF films is not displayed uniformly across the surface of the film because PVDF films comprise crystalline regions that are ferroelectric, and non-crystalline regions that are not ferroelectric. Such ferroelectric heterogeneity is likely to result in unacceptable performance of a FET incorporating a PVDF film making the use of such films highly unattractive.

Further organic materials that exhibit ferroelectric-like behaviour when formed into films are described by Murata et al. (Y. Murata et al., "Ferroelectric behaviour in polyamides of m-Xylylenediamine and dicarboxylic acids", Jpn. J. Appl. Phys. 34, p. 6458-6462 (1995)). Murata describes the electric behaviour of a series of nylon-type polyamide films 8 to 45 j^m thick formed by melt processing. The films produced exhibited electric displacement/electric field hysteresis loops characteristic of ferroelectric materials, however, the thickness of Murata's films alone makes them unsuitable for incorporation in to an OFET device.

An object of the present invention is to obviate or mitigate one or more of the aforementioned problems.

According to a first aspect of the present invention there is provided a field effect transistor comprising source and drain electrodes separated by a semiconductor body region, and a gate electrode separated from said semiconductor body region by a gate insulator region, wherein the gate insulator region comprises a non-crystalline solution-processed organic ferroelectric-like material.

This aspect of the present invention thus provides a field effect transistor comprising a noncrystalline solution-processed organic insulator region, which exhibits ferroelectric-like behaviour rather than an inorganic insulator region, which exhibits ferroelectric behaviour. The term 'ferroelectric-like' is used in accordance with the definition set out above.

A transistor in accordance with an embodiment of the present invention can be used in memory devices to store one bit per one component and the memory is permanent but re-writeable. Poling the gate once into the "on" or "off' bias state switches the transistor into the respective state. It will remain in that state as long as no new gate bias is applied. When a new gate bias is applied memory can be erased or reset at will. Thus embodiments of the present invention can provide significant advantages over flash memory in terms of the power required to write and delete memory, the speed of operation, and the complexity of construction of the device.

It is envisaged that single transistor, permanent memory devices in accordance with the present invention based on organic materials which are compatible with flexible substrates are likely to find application in the field of organic electronics, for example in organic active matrix displays for use in the mobile telecommunications and various non-mobile electronics markets. A transistor in accordance with an embodiment of the present invention will also be a good candidate for LCD and OLED driver electronics because its fabrication should be compatible with the LCD/OLED fabrication process. Furthermore such devices will no longer incorporate a capacitor. Therefore capacitor leakage will be eliminated and the fabrication of displays (e.g. active matrix displays) which require several thousand pixels will be simplified significantly. Removing the need to refresh the device through not incorporating capacitors which need to be repeatedly refreshed, will reduce the amount of energy drawn from the power supply. This will also improve the performance of smart cards which will not need to be permanently connected to a power supply to refresh memory and will only require power when the memory is altered.

Preferably the ferroelectric-like material comprises at least one type of polymer. Thus, the ferroelectric-like material may be comprised substantially of one type of polymer or may comprise a blend of two or more different types of polymer. The ferroelectric-like material may comprise hydrogen bond donor and hydrogen bond acceptor groups.

The ferroelectric-like material is preferably a polyamide and may be formed from the condensation of a diamine and a dicarboxylic acid. It is preferred that the diamine comprises an aromatic group, more preferably the diamine is xylenediamine and most preferably the diamine is m-xylenediamine. The dicarboxylic acid preferably comprises an aliphatic hydrocarbon moiety linking the two carboxylic acid groups. The dicarboxylic acid may comprise up to 13 carbon atoms, 5 to 11 carbon atoms or 6 carbon atoms.

In a preferred embodiment of this aspect of the invention the ferroelectric-like material comprises a repeating unit having the formula:

Where n = 4 - 11.

More preferably n = 4, in which case the polymer is poly(m-xylylenediamine-alt-adipic acid).

The insulator region should be of sufficient thickness to ensure that it contains no pinholes. For many applications it will be desirable to make the insulator region as thin as practically possible. However, in certain circumstances (e.g. if a larger memory window was required) a slightly thicker insulator region would be desirable. The thickness of the insulator region influences the memory window of the device (defined as the difference between the gate voltages that turn the device "off' and "on"). Preferably the insulator region has a thickness in the range 50-400 nm. Such thicknesses provide a memory window of approximately 5 V to 40 V depending on the application.

The insulator region should have a surface roughness, which is as low as possible. Preferably the insulator region has a surface roughness equal to or less than 5 nm.

It is preferred that the semiconductor body region comprises an organic semiconductor material. Alternatively, since inorganic semiconductors are often used in conventional FETs, any known inorganic semiconductor may be used in the device according to the present invention. The semiconductor body region may comprise a p-type semiconductor material. The semiconductor body region may comprise pentacene.

A transistor in accordance with an embodiment of the present invention may additionally comprise a substrate region, which may comprise glass or plastic. The gate electrode preferably comprises indium tin oxide or a synthetic metal (e.g. poly(ethylene dioxythiophene)-poly(styrene sulfonic acid) (PEDOT/PSS)), although any suitable material may be used e.g. emerald-phase polyaniline (PANI) or a metal as such aluminium or gold. It is preferred that at least one of the source and drain electrodes comprises a material selected from the group consisting of PEDOT/PSS, emerald-phase polyaniline, gold, calcium, silver, magnesium, tin, aluminium, alloys comprising one or more of the aforementioned materials, or any other suitable material.

According to a second aspect of the present invention there is provided a method of fabricating a field effect transistor comprising the steps of:

a) forming a gate electrode;

b) forming a gate insulator region;

c) forming a semiconductor body region separated from said gate electrode by said gate insulator region; and d) forming source and drain electrodes separated from each other by said semiconductor body region,

wherein the gate insulator region is formed in step b) by solution processing of a non-crystalline organic ferroelectric-like material.

It will be evident to the skilled person that steps a)-d) may be carried out in any convenient order to produce the desired transistor structure. For example, the order of steps may be a), b), c), d), or a), b), d), c), or alternatively d), c), b), a).

Being able to form the insulator layer from the solution phase means that the process should be much cheaper and less time-intensive than conventional methods of fabricating transistor devices incorporating crystalline or polycrystalline inorganic materials. Additionally, the inventive method is compatible with the deposition of organic semiconductors on top of the ferroelectric-like non-crystalline gate insulator.

Further steps may be performed so as to modify the structure formed in steps a) - d), e.g. surface modification of the gate insulator, modification of the gate insulator bulk, modification of the

electrode/semiconductor interface, modification of the semiconductors etc. The gate insulator region may comprise a plurality of insulator materials.

Preferably step b) comprises solution phase deposition of the ferroelectric-like material. The ferroelectric-like material may be amorphous. The ferroelectric-like material is preferably deposited by spin-casting, although it will be evident to the skilled person that any number of alternative techniques may be used to deposit the ferroelectric-like material from solution, such as inkjet printing, or dip coating. The ferroelectric-like material may be deposited by spin-casting at a speed in the range 100 to 10000 rpm, at a speed in the range 3000 to 5000 rpm, or at a speed of approximately 4000 rpm. It is preferred that the ferroelectric-like material is deposited by spin-casting over a period of time in the range 20 seconds to 15 minutes, over a period of time in the range 5 to 11 minutes, or over a period of time of approximately 8 minutes.

It is preferred that a solution of the ferroelectric-like material is formed by dissolving said ferroelectric-like material in a suitable solvent (e.g. hexafluoroisopropanol, formic acid, trifluoroacetic acid and sulfuric acid, phenol/ethanol (as a 4:1 by volume mixture)) prior to formation of the gate insulator region. The solvent is preferably an organic solvent. The solvent may be an organic acid. The solvent may comprise an aromatic group and the solvent is preferably o-cresol or m-cresol. It is particularly preferred that the solvent is m-cresol. While the ferroelectric-like material may be dissolved in the solvent at room temperature (i.e. a temperature of approximately 20°C), given a sufficient period of time, it is preferable that the ferroelectric-like material is dissolved in the solvent at a temperature in the range 20 to 70 °C, more preferably at a temperature in the range 40 to 60 °C, and yet more preferably at a temperature of approximately 50 °C.

Preferably the solution of the ferroelectric-like material is filtered prior to formation of the gate insulator region. The solution of the ferroelectric-like material may be filtered at a temperature in the range 50 to 100°C prior to formation of the gate insulator region. Moreover, the solution of the ferroelectric-like material may be filtered at a temperature in the range 70 to 80°C prior to formation of the gate insulator region. The solution of the ferroelectric-like material may be filtered through a syringe-mounted filter, which preferably has a pore diameter of approximately 5 (im.

The semiconductor body region may be formed in step c) by thermal evaporation or spin casting.

It is preferred that the gate electrode is formed at least in part on a substrate region. It is further preferred that the gate insulator region is formed at least in part on the gate electrode. The semiconductor body region may be formed at least in part on the gate insulator region.

An embodiment of the present invention will now be described, by way of example only, with reference to the accompanying figures in which:

Figure 1 is a schematic representation of a transistor device in accordance with the first aspect of the invention;

Figure 2 is a schematic representation of the device of figure 1 showing how to turn the device "on" by applying a gate voltage;

Figure 3 is a schematic representation of the device of figure 1 showing how the device remains in the "on" state when the gate voltage is zero;

Figure 4 is a schematic representation of the device of figure 1 showing how to turn the device "off';

Figure 5 is a schematic representation of the device of figure 1 showing how the device remains in the "off' state when the gate voltage is zero; and

Figure 6 is a circuit diagram representing the arrangement of apparatus used to test the inventive device of figure 1; and

Figure 7 is a graphical representation of the output characteristics of the inventive device of figure 1.

The basic construction of a field effect transistor in accordance with the first aspect of the present invention is illustrated schematically in figure 1. A transistor 1 comprises a glass substrate 2 with an indium tin oxide gate electrode 3 preformed thereon. A thin layer of a non-crystalline gate insulator material 4, MXD-6, is supported on the substrate/gate electrode layer 2, 3. A semiconductor layer 5 comprised of a p-type organic semiconductor, pentacene, is supported on

• • * • • • • • « • • •• •• • • • • • • •••

• • • < I • • * • • • «

III ••• ••••

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the insulator layer 4, and gold source and drain electrodes 6, 7 are formed on the semiconductor layer 5. Details of a non-limiting example of a method for fabricating the transistor 1 are set out below.

Figure 2 shows the operation of switching the transistor 1 on. The device as drawn is a p-channel FET, but it will be appreciated that this embodiment is for illustration only and a transistor in accordance with an embodiment of the present invention may also comprise an n-channel FET. If the voltage between the source 6 and the drain 7 is kept constant, a current may flow between the drain 7 and the source 6 if an accumulation layer is induced in the body region 5. -40V is applied between the gate region 3 and the body region 5 polarising the insulator layer 4. The effect is to induce an accumulation layer in the body region 5 adjacent the insulator layer 4 between the drain 7 and the source 6. Arrows 8 show the insulator layer 4 being polarised in a first direction creating an electric displacement in a first direction i.e. from the gate region 3 to the body region 5. The arrows 8 point from positive to negative polarity. Thus the current flowing between the drain and the source increases. For a p-channel transistor in accordance with the present invention poling the gate voltage to a negative voltage will polarise the ferroelectric-like material layer in a first direction, which induces holes in the semiconductor body region by driving out electrons allowing current to flow. It will be appreciated that for an n-channel transistor in accordance with the present invention the polarity of the voltage that must be applied to the gate to create an accumulation layer will be reversed to that described above. Furthermore, for current to flow in an n-channel transistor in the "on" state the drain voltage must be reversed. Additionally for an n-channel transistor in accordance with an embodiment of the present invention the polarisation of the insulator that induces an accumulation layer in the semiconductor body region will be reversed.

Figure 3 shows that when the voltage applied to the gate region 3 is returned to ground the insulator layer 4 retains a remanent polarisation and the associated electric displacement in the body region 5 remains. The accumulation layer remains and current continues to flow between the drain 7 and the source 6. Arrows 9 show that the insulator layer 4 remains polarised in the first direction creating an electric displacement in the first direction, in the absence of an applied gate voltage corresponding to the remanent polarisation. When using pentacene as semiconductor the majority of charge carriers will be holes.

• • •

I • • I • •

• • • • •

• • • • ••••• • • • • • • • • •

11

Figure 4 shows that when 40V is applied between the gate region 3 and the body region 5 the polarity of the insulator layer 4 reverses. This has the effect of removing the accumulation layer in the body region 5 and reducing the current flowing from the drain 7 to the source 6. Arrows 10 show the insulator layer 4 being polarised in a second direction, opposite to the first direction creating an electric displacement in the second direction. If the gate voltage is then poled to a positive voltage the electric displacement of the ferroelectric-like material layer is first zeroed when the applied positive voltage is large enough to reach the coercitive field of the ferroelectric-like material and then reversed when the positive voltage is increased beyond the voltage required to reach the coercitive field. The effect is that the accumulation layer is removed and therefore the current that can flow from the drain to the source is considerably reduced and the device 1 is in the "off' state.

Figure 5 shows that when the voltage applied to the gate region 3 is returned to zero the insulator layer 4 retains its remanent polarisation while the accumulation layer is removed, inhibiting current flow between the drain 7 and the source 6 [between drain and source?]and therefore the device remains in the "off state. Arrows 11 show that the insulator layer 4 remains polarised in the second direction creating an electric displacement in the second direction, in the absence of an applied gate voltage.

From the above description it will be evident to the skilled person that the inventive device may store a logical high or low condition depending on the direction in which the gate has most recently been poled. In order to read this logic value a voltage is applied to the drain region with respect to the source region. A current sensor senses whether the current flowing through the transistor is high or low and registers a logic high or logic low condition respectively. Alternatively, if the transistor is used in an active matrix display, a display pixel will light-up or not light-up. In essence, during use the device 1 would be cycled between the situations shown in Figures 3 and 5. This approach has significant advantages over the traditional use of a conventional FET in conjunction with a storage capacitor for memory devices. It does not involve a capacitor to store the charge, which may discharge over time. As such a transistor in accordance with an embodiment of the present invention does not need to be periodically refreshed in order to store the logic state. The circuit will thus require no power other than during a read or write operation as in accordance with conventional ferroelectric gate insulator FETs.

The transistor 1 was tested using two Keithley 2400 (denoted 12 in figure 6) source and measure units, one for applying a gate voltage, and one for applying a drain voltage and simultaneously measuring the resulting drain current. The ground of the two Keithley units 12 was linked and connected to the source contact. Note that, in figure 6, the electronic symbol of a p-type, accumulation mode MESFET has been used to represent the inventive device 1 under test as we are currently unaware of a standardised symbol for a ferroelectric FET. The memory effect of the transistor 1 was characterized by holding the drain voltage constant and varying the gate voltage while reading the current between source and drain. A so-called memory window of about 40V was observed, while the current between gate and source was less than 0.1 nA (minimum resolution of the Keithley 2400) at all times. The results of these tests are shown in Figure 7.

Such high voltages were used in these tests due to the thickness of the insulator layer. The thickness of the layer was chosen to ensure that it did not contain any pinholes. It will be evident that the method forming the second aspect of the present invention is eminently suitable to be adapted to produce thinner insulator layers, which would use smaller gate voltages and provide smaller memory windows.

Ferroelectric-like behaviour, and the hysteresis associated with it, are visualized by a gate-sweep transfer characteristic, where the voltage between source and drain is held constant, and the gate voltage is swept from a positive voltage to a negative voltage and back. Figure 7 shows the associated source-drain current vs gate voltage characteristic of the transistor 1. Starting at point 13 this shows a device in the "off' state with no voltage applied to the gate and minimal leakage current flowing from the drain to the source. When the voltage applied to the gate is ramped to -40V the drain to source current increases to point 14. As the gate voltage is returned to zero (point 15) the drain to source current reduces slightly as the electric displacement is lower resulting from the polarised insulator layer compared to that present when the gate voltage is at -40V. As the gate voltage is ramped to +40V the drain / source current decreases to point 16, which is substantially the same current level as at point 13. As the positive gate voltage is removed the drain / source current remains low.

The key feature of the behaviour of the device 1 as depicted in figure 7 is that the current at point 15 (after negative pulsing of the gate voltage) is 5.5 times higher than at point 13 (after positive pulsing of the gate voltage) even though the gate voltage at points 13 and 15 is zero. This is a sufficient variation in current for a current sensor to register the difference between high and low

current and thus record logic high and logic low respectively thus enabling the device 1 to perform a memory function.

Figures 1-5 show the transistor 1 in accordance with an embodiment of the present invention constructed as a planar FET with the gate electrode lowermost on the substrate. The insulator, semiconductor body and drain / source electrodes are shown as being placed on top of one another working upwards. It will be clear to the appropriately skilled person that a transistor in accordance with an embodiment of the present invention may take any number of physical forms, in common with other forms of both ferroelectric transistors and traditional FETs. The form of the device can be controlled by choosing a particular order for steps a) to d) as previously defined for fabricating the device. A transistor in accordance with an embodiment of the present invention may include a planar layer of semiconductor material deposited on top of an insulator material as shown in figures 1 to 5, however, planar structures with the gate uppermost may also be formed. Alternatively trench structures wherein the gate is formed in a trench etched into the body of the semiconductor through the source electrode and / or the drain electrode, and separated from these by an insulator layer lining the gate trench may be constructed.

Fabrication of Device

A field effect transistor device forming an embodiment of the present invention was prepared according to the following process.

Step 1 - Substrate And Gate Electrode

A glass substrate was purchased with indium-tin-oxide (ITO, a conductive, transparent metal oxide) sputtered upon it.

The ITO was patterned using the following process. The parts of the ITO electrode to be preserved were coated with a protective acid-resistant material in solution (which could subsequently be removed by acetone). The protective layer was then dried and the substrate immersed in 30 % hydrochloric acid for 6 minutes to remove the non-protected ITO. The protective layer was then removed by immersion in acetone.

The substrate was cleaned using the following procedure. Ultrasonic bath cleaning in acetone for 5 minutes followed by ultrasonic bath cleaning for 20 minutes in a 70 °C solution of deionised water with 3 % Helmanex cleaning agent. The substrate was then washed with de-ionised water and subjected to further ultrasonic bath cleaning in deionised water at 70 °C for 20 minutes. Finally, the substrate was washed with de-ionised water and then underwent ultrasonic bath cleaning in a 50 °C methanol bath for 15 minutes.

Step 2 - Gate Insulating Layer

A polyamide polymer MXD-6 and m-Cresol were combined in a ratio of 50 mg of MXD-6 per 1 ml of m-Cresol and the m-Cresol heated to 50 °C and stirred to accelerate the dissolving process. Complete dissolution of MXD-6 pellets yielded a very viscous solution of MXD-6. Dissolution takes between 8 and 12 hours depending on the exact temperature of the m-Cresol. If a different form of MXD-6 were used, such as powdered MXD-6 rather than pellets, the dissolution time would be significantly less than 8 hours.

The MXD-6 solution was then hot-filtered at 70 - 80 °C through a syringe with a fastened syringe filter of 5 p.m pore diameter. The MXD-6 solution was then spun cast onto the glass-ITO substrate, which had been preheated to the same temperature as that of the solution (i.e. approximately 70 °C), at 4000 rpm for 8 minutes. Finally, the substrate with the gate insulator layer deposited thereon was placed in a vacuum oven at 1 Torr and 50 °C for 24 hours to let any remaining m-Cresol and humidity evaporate. This process provided a layer of MXD-6 of approximately 350 nm thickness with less than 5 nm surface roughness.

Step 3 - Semiconductor Layer

Pentacene was placed into a quartz basket, which in turn was placed into a compatibly shaped tungsten filament housed in an evaporation chamber. The substrate with the gate insulator deposited thereon was placed into the chamber approximately 12 cm from the quartz basket with the gate insulator side facing the opening of the basket. The chamber was then evacuated to a pressure of 2xl0"6 Torr and pentacene thermally evaporated onto the gate insulator at a rate of 0.5 nm/s.

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Step 4 - Source And Drain Electrodes

The quartz basket and tungsten filament from step 3 were replaced with a molybdenum boat and 1 cm of 0.5 mm gold wire placed into the boat. The substrate having insulator and semiconductor layers deposited thereon was placed 12 cm from the boat and a shadow mask positioned between the boat and the substrate so as to define electrode sizes of 2 mm x 2 mm (for both source and drain electrodes) and with channel lengths on one mask of 20, 40, 60, or 80 (xm to provide four pairs of electrodes. Gold was then evaporated at a pressure of 2x 10~6 Torr and a rate of 0.1 nm/s to provide gold electrodes having a thickness of approximately 100 nm.

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Claims

1. A field effect transistor comprising source and drain electrodes separated by a semiconductor body region, and a gate electrode separated from said semiconductor body region by a gate insulator region, wherein the gate insulator region comprises a noncrystalline solution-processed organic ferroelectric-like material.

2. A field effect transistor according to claim 1, wherein the ferroelectric-like material comprises at least one type of polymer.

3. A field effect transistor according to claim 2, wherein the polymer comprises hydrogen bond donor and hydrogen bond acceptor groups.

4. A field effect transistor according to claim 2 or 3, wherein the polymer is a polyamide.

5. A field effect transistor according to claim 4, wherein the polyamide is formed from the condensation of a diamine and a dicarboxylic acid.

6. A field effect transistor according to claim 5, wherein the diamine comprises an aromatic group.

7. A field effect transistor according to claim 5 or 6, wherein the diamine is xylenediamine.

8. A field effect transistor according to claim 5, 6 or 7, wherein the diamine is m-xylenediamine.

9. A field effect transistor according to any one of claims 5 to 8, wherein the dicarboxylic acid comprises an aliphatic hydrocarbon moiety linking the two carboxylic acid groups.

10. A field effect transistor according to one of claims 5 to 9, wherein the dicarboxylic acid comprises up to 13 carbon atoms.

11. A field effect transistor according to one of claims 5 to 10, wherein the dicarboxylic acid comprises a number of carbon atoms in the range 5 to 11.

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12. A field effect transistor according to one of claims 5 to 11, wherein the dicarboxylic acid comprises six carbon atoms.

13. A field effect transistor according to any preceding claim, wherein the ferroelectric-like comprises a repeating unit having the formula:

Where n = 4 - 11.

14. A field effect transistor according to claim 13, wherein n = 4.

15. A field effect transistor according to any preceding claim, wherein the insulator region has a thickness of up to approximately 350 nm.

16. A field effect transistor according to any preceding claim, wherein the insulator region has a surface roughness equal to or less than 5 nm.

17. A field effect transistor according to any preceding claim, wherein the semiconductor body region comprises an organic semiconductor material.

18. A field effect transistor according to any preceding claim, wherein the semiconductor body region comprises a p-type semiconductor material.

19. A field effect transistor according to any preceding claim, wherein the semiconductor body region comprises pentacene.

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20. A field effect transistor according to any preceding claim, wherein the transistor additionally comprises a substrate region.

21. A field effect transistor according to claim 20, wherein the substrate region comprises glass or plastic.

22. A field effect transistor according to any preceding claim, wherein the gate electrode comprises indium tin oxide or a synthetic metal.

23. A field effect transistor according to any preceding claim, wherein at least one of the source and drain electrodes comprises a material selected from the group consisting of PEDOT/PSS, emerald-phase polyaniline, gold calcium, silver, magnesium, tin, aluminium and alloys comprising one or more of the aforementioned materials.

24. A method of fabricating a field effect transistor comprising the steps of:

a) forming a gate electrode;

b) forming a gate insulator region;

wherein the gate insulator region is formed in step b) by solution processing of a noncrystalline organic ferroelectric-like material.

25. A method according to claim 24, wherein step b) comprises solution phase deposition of the ferroelectric-like material.

26. A method according to claim 24 or 25, wherein the ferroelectric-like material is deposited by spin-casting.

27. A method according to any one of claims 24 to 26, wherein the ferroelectric-like material is deposited by spin-casting at a speed in the range 100 to 10000 rpm.

28. A method according to any one of claims 24 to 26, wherein the ferroelectric-like material is deposited by spin-casting at a speed in the range 3000 to 5000 rpm.

29. A method according to any one of claims 24 to 26, wherein the ferroelectric-like material is deposited by spin-casting at a speed of approximately 4000 rpm.

30. A method according to any one of claims 24 to 29, wherein the ferroelectric-like material is deposited by spin-casting over a period of time in the range 20 seconds to 15 minutes.

31. A method according to any one of claims 24 to 29, wherein the ferroelectric-like material is deposited by spin-casting over a period of time in the range 5 to 11 minutes.

32. A method according to any one of claims 24 to 29, wherein the ferroelectric-like material is deposited by spin-casting over a period of time of approximately 8 minutes.

33. A method according to any one of claims 24 to 32, wherein a solution of the ferroelectric-like material is formed by dissolving said ferroelectric-like material in a suitable solvent prior to formation of the gate insulator region.

34. A method according to claim 33, wherein the solvent is an organic solvent.

35. A method according to claim 33 or 34, wherein the solvent is an organic acid.

36. A method according to claim 33, 34 or 35, wherein the solvent comprises an aromatic group.

37. A method according to claim 33, wherein the solvent is o-cresol or m-cresol.

38. A method according to claim 33, wherein the solvent is m-cresol.

39. A method according to any one of claims 33 to 38, wherein the ferroelectric-like material is dissolved in the solvent at a temperature in the range 20 to 70 °C.

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40. A method according to any one of claims 33 to 38, wherein the ferroelectric-like material is dissolved in the solvent at a temperature in the range 40 to 60 °C.

41. A method according to any one of claims 33 to 38, wherein the ferroelectric-like material is dissolved in the solvent at a temperature of approximately 50 °C.

42. A method according to any one of claims 33 to 41 wherein the solution of the ferroelectric-like material is filtered prior to formation of the gate insulator region.

43. A method according to any one of claims 33 to 42 wherein the solution of the ferroelectric-like material is filtered at a temperature in the range 50 to 100°C prior to formation of the gate insulator region.

44. A method according to any one of claims 34 to 43 wherein the solution of the ferroelectric-like material is filtered at a temperature in the range 70 to 80 °C prior to formation of the gate insulator region.

45. A method according to claim 42, 43 or 44 wherein the solution of the ferroelectric-like material is filtered through a syringe-mounted filter.

46. A method according to claim 45, wherein the filter has a pore diameter of approximately 5 nm.

47. A method according to any one of claims 24 to 46, wherein the semiconductor region is formed in step c) by thermal evaporation or spin casting.

48. A method according to any one of claims 24 to 47, wherein the gate electrode is formed at least in part on a substrate region.

49. A method according to any one of claims 24 to 48, wherein the gate insulator region is formed at least in part on the gate electrode.

50. A method according to any one of claims 24 to 49, wherein the semiconductor body region is formed at least in part on the gate insulator region.

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51. A field effect transistor substantially as hereinbefore described with reference to figures 1 to 5.

52. A method of fabricating a field effect transistor substantially as hereinbefore described with reference to figures 1 to 5.