JPS60113445A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS60113445A JPS60113445A JP22093883A JP22093883A JPS60113445A JP S60113445 A JPS60113445 A JP S60113445A JP 22093883 A JP22093883 A JP 22093883A JP 22093883 A JP22093883 A JP 22093883A JP S60113445 A JPS60113445 A JP S60113445A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- metal
- groove
- electrode wiring
- evaporation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子の電極配線の形成方法に関するもの
である、
近年半導体素子の応用範囲は広がシその要求性能も上が
ってきている。半導体素子の性能向上の一つの手法に微
細加工がある。これは、高周波動作あるいは集積回路の
高集積化に対応するものである。この微細化を行うと当
然金属配線パターンも微細になり配線抵抗、インダクタ
ンスが大きくなり、また、許容電流が小さくなってしま
う。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming electrode wiring of a semiconductor device. In recent years, the range of applications of semiconductor devices has expanded and the required performance has also increased. Microfabrication is one method for improving the performance of semiconductor devices. This corresponds to high frequency operation or high integration of integrated circuits. If this miniaturization is carried out, the metal wiring pattern will naturally become finer, the wiring resistance and inductance will increase, and the allowable current will become smaller.
本発明は、上記問題点を解決する手法の一つを提供する
もので、配線抵抗を低くしたい配線又は許容電流を大き
くしたい配線の下の絶縁層に溝を設けておき、金属配線
材料を蒸着或いはスパッタ等でつけた後、表面を機械的
に研磨することにより絶縁層の溝を設けた部分のみ配線
材料が残るようにし、その後で再度金属配線材料をつけ
て配線を形成する。The present invention provides one of the methods for solving the above-mentioned problems.A groove is provided in the insulating layer under the wiring for which the wiring resistance is to be lowered or the allowable current is to be increased, and a metal wiring material is deposited by vapor deposition. Alternatively, after applying by sputtering or the like, the surface is mechanically polished so that the wiring material remains only in the grooved portion of the insulating layer, and then metal wiring material is applied again to form wiring.
通常の半導体素子では一回の配線形成を行っており、一
様の厚さとなってしまう。この配線の厚さは微細化の為
には薄くする必要があシ、また配線抵抗或いは許容電流
の観点からは厚くする必要がある。本発明によれば、配
線の厚さを変えることができ、必要な部分のみ厚く形成
することが可能であり、上記通常の半導体素子の問題点
を解決することができる。In ordinary semiconductor devices, wiring is formed once, resulting in a uniform thickness. The thickness of this wiring needs to be thin for miniaturization, and also needs to be thick from the viewpoint of wiring resistance or allowable current. According to the present invention, the thickness of the wiring can be changed and only the necessary portions can be made thicker, and the problems of the above-mentioned ordinary semiconductor elements can be solved.
以下に実施例に従って説明する。Examples will be explained below.
第１図は通常の半導体素子のベレットの断面図であり、
拡散領域２のように半導体素子が拡散形成された半導体
基板１の表面に絶縁層３を介して電極配線４が形成さ扛
ている。かかる構造では電極配線４の厚さは一様になら
ざるを得ない。FIG. 1 is a cross-sectional view of a bullet of a normal semiconductor device.
Electrode wiring 4 is formed on the surface of a semiconductor substrate 1 on which a semiconductor element is diffused, such as a diffusion region 2, with an insulating layer 3 interposed therebetween. In such a structure, the thickness of the electrode wiring 4 must be uniform.
第２図に示す本発明の一実施例によれば拡散層１２を有
する半導体基板１１上の絶縁膜１３に厚さの厚い電極配
線を形成したい部分に溝１５を設け、第１回目の金属蒸
着を行い、この蒸着金属が溝５内にのみ残るように表面
研磨等により蒸着金属を除去した後、第２回目の金属蒸
着を行い、この蒸着金属を選択エツチングして所定の電
極配線１４を形成する。このようにすれば１部分的に厚
い電極配線１４を形成することが可能である。According to an embodiment of the present invention shown in FIG. 2, a groove 15 is provided in a portion of an insulating film 13 on a semiconductor substrate 11 having a diffusion layer 12 where a thick electrode wiring is to be formed, and the first metal evaporation process is performed. After removing the deposited metal by surface polishing or the like so that the deposited metal remains only in the groove 5, a second metal deposition is performed, and the deposited metal is selectively etched to form a predetermined electrode wiring 14. do. In this way, it is possible to form a partially thick electrode wiring 14.
同、金属は蒸着に限らず、スパッタによってつけてもよ
く、第１回目の蒸着金属は研磨除去に限らず、その他の
方法で除去しても良いことは明らかである。Similarly, it is clear that the metal may be applied not only by vapor deposition but also by sputtering, and the first vapor-deposited metal is not limited to removal by polishing, but may be removed by other methods.
第１図は従来の半導体素子のベレット断面図である。第
２図は本発明の一実施例によって得られる半導体素子の
ベレット断面図である。
１．１１・・・・半導体基板、２，１２ ・拡散層。
３．１３・・・・・絶縁層、４．１４・・ ・配線、１
５・・・・・溝。FIG. 1 is a sectional view of a conventional semiconductor device. FIG. 2 is a pellet cross-sectional view of a semiconductor device obtained according to an embodiment of the present invention. 1.11...Semiconductor substrate, 2,12 - Diffusion layer. 3.13... Insulating layer, 4.14... Wiring, 1
5...Groove.
Claims (1)
配線材料を蒸着或いはスパッタでつけて前記溝内に前記
第１の金属配線材料を設けた後、表面を研磨して再度第
２の金属配線材料を蒸着或いはスパッタ等でつけること
を特徴とする半導体素子の製造方法。After forming a groove in the surface insulator of the semiconductor element, a first metal wiring material is applied by vapor deposition or sputtering to provide the first metal wiring material in the groove, and then the surface is polished and a second metal wiring material is applied again. 1. A method for manufacturing a semiconductor device, characterized in that a metal wiring material is applied by vapor deposition, sputtering, or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22093883A JPS60113445A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22093883A JPS60113445A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60113445A true JPS60113445A (en) | 1985-06-19 |
Family
ID=16758906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22093883A Pending JPS60113445A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60113445A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473638A (en) * | 1987-09-14 | 1989-03-17 | Nec Corp | Semiconductor integrated circuit device |
| JPH11214508A (en) * | 1998-01-26 | 1999-08-06 | Nec Corp | Semiconductor device |
| US6849888B2 (en) | 2002-09-24 | 2005-02-01 | Renesas Technology Corp. | Semiconductor memory device, nonvolatile memory device and magnetic memory device provided with memory elements and interconnections |
| JP2011091308A (en) * | 2009-10-26 | 2011-05-06 | Denso Corp | Printed wiring board |
-
1983
- 1983-11-24 JP JP22093883A patent/JPS60113445A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6473638A (en) * | 1987-09-14 | 1989-03-17 | Nec Corp | Semiconductor integrated circuit device |
| JPH11214508A (en) * | 1998-01-26 | 1999-08-06 | Nec Corp | Semiconductor device |
| US6849888B2 (en) | 2002-09-24 | 2005-02-01 | Renesas Technology Corp. | Semiconductor memory device, nonvolatile memory device and magnetic memory device provided with memory elements and interconnections |
| JP2011091308A (en) * | 2009-10-26 | 2011-05-06 | Denso Corp | Printed wiring board |
| CN102056403A (en) * | 2009-10-26 | 2011-05-11 | 株式会社电装 | Printed wiring board |
| US8426747B2 (en) | 2009-10-26 | 2013-04-23 | Denso Corporation | Printed wiring board |
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