JPS61100950A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS61100950A
JPS61100950A JP22171384A JP22171384A JPS61100950A JP S61100950 A JPS61100950 A JP S61100950A JP 22171384 A JP22171384 A JP 22171384A JP 22171384 A JP22171384 A JP 22171384A JP S61100950 A JPS61100950 A JP S61100950A
Authority
JP
Japan
Prior art keywords
surface
insulating layer
wiring pattern
formed
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22171384A
Inventor
Yukio Tomita
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP22171384A priority Critical patent/JPS61100950A/en
Publication of JPS61100950A publication Critical patent/JPS61100950A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE:To eliminate defective slip-off on etching and a disconnection, etc. due to side etching, and to form a wiring pattern fit for the increase of frequency and fining by shaping a groove to a surface insulator in a semiconductor element, attaching a metallic wiring material through evaporation and grinding the surface without an etching process to form the wiring pattern. CONSTITUTION:A diffusion layer 12 and an insulating layer 13 are shaped onto a semiconductor substrate 11 through a known method. The insulating layer 13 is formed by using a known surface flattening technique to shape the insulating layer having a flat surface. The insulating layer is formed in slightly thick size such as approximately 2mum. Grooves 15 for a wiring pattern are shaped to the insulating layer 13 by employing a photoetching techniquie. The depth of the groove is brought to size such as 1mum. A contact hole is formed by repeating a photoetching process. An electrode material 14 consisting of Al, etc. is attached onto the whole surface through evaporation or sputtering or the like. The surface is ground without executing a photo-resist pattern forming process and an etching process, thus obtaining the wiring pattern shaped into the groove sections.
JP22171384A 1984-10-22 1984-10-22 Manufacture of semiconductor element Pending JPS61100950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22171384A JPS61100950A (en) 1984-10-22 1984-10-22 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22171384A JPS61100950A (en) 1984-10-22 1984-10-22 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS61100950A true JPS61100950A (en) 1986-05-19

Family

ID=16771098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22171384A Pending JPS61100950A (en) 1984-10-22 1984-10-22 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS61100950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102543A (en) * 1985-10-28 1987-05-13 Ibm Formation of conductive film and insulating film with same flat surface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102543A (en) * 1985-10-28 1987-05-13 Ibm Formation of conductive film and insulating film with same flat surface

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