JPS60113429A - Evaluation method of plasma etching uniformity - Google Patents

Evaluation method of plasma etching uniformity

Info

Publication number
JPS60113429A
JPS60113429A JP22111083A JP22111083A JPS60113429A JP S60113429 A JPS60113429 A JP S60113429A JP 22111083 A JP22111083 A JP 22111083A JP 22111083 A JP22111083 A JP 22111083A JP S60113429 A JPS60113429 A JP S60113429A
Authority
JP
Japan
Prior art keywords
etching
etched
substrate
plasma etching
coating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22111083A
Other languages
Japanese (ja)
Inventor
Hiroshi Koyama
浩 小山
Sunao Nishioka
西岡 直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22111083A priority Critical patent/JPS60113429A/en
Publication of JPS60113429A publication Critical patent/JPS60113429A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To evaluate etching uniformity in high sensitivity stressing uneven etching by providing a coated layer made of a material which is slower in etching speed on the upper surface of a substrate being etched and plasma-etching. CONSTITUTION:On the upper surface of a substrate 1 being etched, a coated layer 3 made of a material which is slower in etching speed than that of the substrate is formed and etched by plasma current 2. If the plasma current 2 is uneven, the etching on the coated layer 3a is also uneven. Since the etching speed of the layer 3a is slower than the etching speed of the substrate 1, etching unevenness is greatly stressed at the time when the remaining part of the layer 3a is completely removed by etching.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体素子の製造に必要なプラズマエツチン
グについて、その個々の場合のエツチング効果の均一性
を評価する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for evaluating the uniformity of etching effect in each case of plasma etching necessary for manufacturing semiconductor devices.

〔従来技術〕[Prior art]

半導体素子の製造工程においてプラズマエツチングが広
く用りられるようになっているが、プラズマ流の疎密の
存在などによって被エツチング部材の表面に微細な凹凸
が形成されることがある。
Although plasma etching has become widely used in the manufacturing process of semiconductor devices, fine irregularities may be formed on the surface of the member to be etched due to the presence of uneven plasma flow.

この凹凸は数A〜数十八へはあるが、半導体素子の集積
度の高密度化が進むにつれて、数十へのエツチングむら
は素子の特性にとって致命的欠陥を引きおこすレベルに
達している。
The unevenness ranges from several A to several tens of digits, but as the degree of integration of semiconductor devices becomes higher and higher, etching unevenness of several tens of digits has reached a level that can cause a fatal defect in the characteristics of the device.

従って、実際の素子の製造に適用に先立って。Therefore, prior to application to actual device manufacturing.

それに用いるプラズマエツチング装置のエツチング効果
の均一性の評価は必須の技術である。
Evaluation of the uniformity of the etching effect of the plasma etching equipment used for this purpose is an essential technique.

第1図は従来の評価方法を示す断面図で、実際に半導体
素子を製造する場合と同様の条件で、被エツチング基体
(1)の表面をプラズマ流(2)によってエツチングを
行う。そのプラズマ流(2)に疎密があると第2図に示
すように被エツチング基体(1)の表面に微小な凹凸Δ
1を生じる。この凹凸を高感度表面粗さ検査装置などを
用いて評価していた。
FIG. 1 is a cross-sectional view showing a conventional evaluation method, in which the surface of a substrate to be etched (1) is etched by a plasma stream (2) under conditions similar to those used in actually manufacturing semiconductor devices. If the plasma flow (2) is uneven, minute irregularities Δ will appear on the surface of the substrate to be etched (1), as shown in Figure 2.
yields 1. These irregularities were evaluated using a highly sensitive surface roughness inspection device.

ところがこの凹凸Δ、は前述のように数A〜数士Aと極
めて小さ−ので、高感度表面粗さ計で測定しても十分適
確な測定値が得られず、必要な評価が困難であった。
However, as mentioned above, this unevenness Δ is extremely small, ranging from several A to several A, so even when measured with a high-sensitivity surface roughness meter, a sufficiently accurate measurement value cannot be obtained, making the necessary evaluation difficult. there were.

〔発明の概観〕[Overview of the invention]

この発明は以上のような点に鑑みてなされたもので、被
エツチング基体の上面にこの基体より被エツチング速度
の遅い部材からなる被覆層を設けた上で、プラズマエツ
チングを施すことによって。
The present invention has been made in view of the above points, and involves providing a coating layer made of a material whose etching speed is slower than that of the substrate on the upper surface of the substrate to be etched, and then performing plasma etching.

エツチングむらを極端に強調し、高感度にエツチングの
均一性を評価できる方法を提供するものである。
The present invention provides a method that can extremely emphasize etching unevenness and evaluate etching uniformity with high sensitivity.

〔発明の実施例〕[Embodiments of the invention]

第3図はこの発明の一実施例の各段階の状態を示す断面
図で、まず、第3図Aに示すように、被エツチング基体
(1)の上面にこれより被エツチング速度の遅い部材か
らなる被覆層(3)を形成し、その上からプラズマ流(
2)によってエツチングを行うと、プラズマ流(2)に
疎密がある場合、第3図Bに被覆層(3a)として示す
ように深さΔ2のエツチングむらを生じる。この被覆1
(3a)のエツチングが早く進行した部分はエツチング
進行の遅す部分より早く被エツチング基体(1’)のエ
ツチングが開始される。
FIG. 3 is a sectional view showing the state of each stage of an embodiment of the present invention. First, as shown in FIG. A coating layer (3) is formed, and a plasma flow (
When etching is performed in accordance with 2), if the plasma flow (2) is uneven, etching unevenness with a depth Δ2 occurs as shown as a coating layer (3a) in FIG. 3B. This coating 1
In the portion (3a) where etching progresses quickly, etching of the substrate to be etched (1') starts earlier than in the portion where etching progresses slowly.

ここで、被覆層(3a)の被エツチング速度が被エツチ
ング基体(1)の被エツチング速度より遅いので。
Here, the rate at which the coating layer (3a) is etched is slower than the rate at which the substrate (1) to be etched is etched.

被覆層(3a)の残留部分が完全にエツチング除去され
る時点では、第3図Cに示されるように被エツチング基
体(1)の早くエツチングが始った部分は上記Δより大
きめΔ3の深さにエツチングを受け、エツチングむらは
大幅に強調される。
At the time when the remaining portion of the coating layer (3a) is completely etched away, the portion of the substrate to be etched (1) where etching begins earlier has a depth of Δ3, which is larger than the above Δ, as shown in FIG. 3C. The unevenness of the etching is greatly accentuated.

^ま、被エツチング基体(1)に多結晶シリコン、エツ
チングガスとして二塩化四フッ化二炭素(C2C12F
4)を用−1被覆層(3)に鉄を主成分とする膜を用h
fc場合、上記手順によって被エツチング基体(1)の
表面に生じるエツチングむらの深さΔ3は150A程度
となり、目視検査でも表面のエツチングむらを十分判定
できる。また、被覆層(3)にタングステン嘆を用いて
も良好な結果が得られる。
^ Well, the substrate to be etched (1) is polycrystalline silicon, and the etching gas is carbon dichloride tetrafluoride (C2C12F).
4) - 1 Use a film containing iron as the main component for the coating layer (3).
In the case of fc, the depth Δ3 of the etching unevenness produced on the surface of the substrate to be etched (1) by the above procedure is about 150 A, and the etching unevenness on the surface can be sufficiently determined by visual inspection. Good results can also be obtained by using tungsten for the coating layer (3).

上記説明はプラズマエツチングの均一性の評価方法とし
て述べたが、この方法によれば、従来その観察が困難で
あった、プラズマ圧力などの局所的変動を直視化するこ
ともできる。
Although the above explanation has been given as a method for evaluating the uniformity of plasma etching, this method also makes it possible to directly visualize local fluctuations in plasma pressure, etc., which have been difficult to observe in the past.

〔発明の効果〕〔Effect of the invention〕

以上発明したように、この発明では被エツチング基体に
、これよりも被エツチング速度の遅め部材からなる被覆
層を設け、その上から評価すべきプラズマエツチングを
施すので、プラズマ流のむらによるエツチングむらが強
調され、微少なエツチングの不均一性も高感度だ評価す
ることができる。
As described above, in this invention, a coating layer made of a material whose etching speed is slower than that of the substrate to be etched is provided on the substrate to be etched, and the plasma etching to be evaluated is performed on the coating layer, so that uneven etching due to uneven plasma flow is avoided. Even minute etching non-uniformities can be highlighted and evaluated with high sensitivity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の評価方法の実施状況を示す断面図、第2
図はこの従来方法によって生じるエツチングむらによる
凹凸を示す断面図、第3図A〜Cはこの発明の一実施例
の各段階の状態を示す断面図である。 図において、(1)は被エツチング基体、(2)はプラ
ズマ流、(3)は被覆層であ゛るち なお1図中同一符号は同一または相当部分を示す。 代理人 大岩増雄 第1図 第2図 第3図
Figure 1 is a cross-sectional view showing the implementation status of the conventional evaluation method;
The figure is a sectional view showing unevenness due to etching unevenness caused by this conventional method, and FIGS. 3A to 3C are sectional views showing states at each stage of an embodiment of the present invention. In the figure, (1) is the substrate to be etched, (2) is the plasma flow, and (3) is the coating layer. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)被エツチング基板の表面上に上記被エツチング基
板より被エツチング速度の遅い部材からなる被覆Iii
を形成し、上記被覆層の上から評価すべきプラズマエツ
チングを施し、上記被覆層がエツチング除去された段階
で上記被エツチング基板の表面に生じたエツチングによ
る凹凸パターンによって均一性を判定することを特徴と
するプラズマエツチングの均一性の評価方法。
(1) A coating III made of a member whose etching speed is slower than that of the substrate to be etched on the surface of the substrate to be etched.
is formed, plasma etching to be evaluated is performed on the coating layer, and uniformity is determined based on the pattern of protrusions and recesses caused by etching on the surface of the substrate to be etched at the stage when the coating layer is etched away. A method for evaluating the uniformity of plasma etching.
(2)被覆層にタングステン膜を用いることを特徴とす
る特許請求の範囲第1項記載のプラズマエツチングの均
一性の評価方法。
(2) The method for evaluating the uniformity of plasma etching according to claim 1, characterized in that a tungsten film is used as the coating layer.
(3)被覆層に鉄を主成分とする膜を用いることを特徴
とする特許請求の範囲第1項記載のプラズマエツチング
の均一性の評価方法。
(3) The method for evaluating the uniformity of plasma etching according to claim 1, characterized in that a film containing iron as a main component is used as the coating layer.
JP22111083A 1983-11-22 1983-11-22 Evaluation method of plasma etching uniformity Pending JPS60113429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22111083A JPS60113429A (en) 1983-11-22 1983-11-22 Evaluation method of plasma etching uniformity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22111083A JPS60113429A (en) 1983-11-22 1983-11-22 Evaluation method of plasma etching uniformity

Publications (1)

Publication Number Publication Date
JPS60113429A true JPS60113429A (en) 1985-06-19

Family

ID=16761635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22111083A Pending JPS60113429A (en) 1983-11-22 1983-11-22 Evaluation method of plasma etching uniformity

Country Status (1)

Country Link
JP (1) JPS60113429A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100612560B1 (en) 2005-05-25 2006-08-11 주식회사 하이닉스반도체 Method for fabricating semiconductor device
US7419534B2 (en) 2003-03-05 2008-09-02 Nec Corporation Cooler using filter with dehumidifying function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7419534B2 (en) 2003-03-05 2008-09-02 Nec Corporation Cooler using filter with dehumidifying function
KR100612560B1 (en) 2005-05-25 2006-08-11 주식회사 하이닉스반도체 Method for fabricating semiconductor device

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