JPS60112324A - Phase synchronizing oscillator - Google Patents

Abstract

PURPOSE:To decrease the number of necessary filters and to attain the miniaturization and the economical properties of a phase synchronizing oscillator, by using a monitor control means to decide whether the output frequency of a frequency dividing means of an input signal is coincident with the phase comparison frequency and controlling the division ratio of an input dividing means. CONSTITUTION:One of (n) units of input signals of frequencies f1-fn is applied to an input terminal 1 and led to an input dividing means 10 which can control a division ratio. While a phase synchronizing oscillating means 20 having a phase comparison frequency f0, i,e., a common measure of frequencies f1-fn supplies a feedback signal obtained by dividing its own output by a feedback dividing means 30 together with the output of the means 10 and performs a feedback control action to minimize the difference between said feedback signal and the output of the means 10. Furthermore a monitor control means 40 controls the division ratio of the means 10 in case the output of the means 10 is not coincident with the frequency f0. Therefore the division ratio is controlled so as to obtain the coincidence between the output of the means 10 and the frequency f0 even in case the input signal has either one of frequencies f1-fn.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked oscillation device, and more particularly to a phase-locked oscillation device that targets a plurality of input signals having all different frequencies.

The configuration of the phase-locked oscillation device that handles all failures includes a phase-locked oscillation means having a phase comparison frequency fo that is a common divisor of the n input signal frequencies f Feedback frequency dividing means arranged for the purpose of matching the phase comparison frequency fo, and frequency division ratio control arranged for the purpose of dividing the frequency of an input signal selected from the n input signals and matching the phase comparison frequency foVC. an input frequency dividing means capable of monitoring the input signal sound of the input frequency dividing means, identifying the frequency of the input signal, and generating a control signal corresponding to the identification result; Division ratio? The system is equipped with all monitoring and control means for controlling and matching the output frequency of the input frequency dividing means with the total phase comparison frequency fo. However, this supervisory control means requires a total of n independent filters that discriminate among n input signal frequencies fx fz ~f, and therefore has the disadvantage that it is extremely inferior in terms of economy and miniaturization of the device. there were.

An object of the present invention is to completely control the frequency division ratio of the input frequency dividing means by fully determining whether the output frequency of the input frequency dividing means matches the phase comparison frequency using the monitoring control means, thereby solving the above-mentioned drawbacks. Eliminate, realize economy and miniaturization? An object of the present invention is to provide a phase-locked oscillation device that achieves the following objectives.

According to the present invention, the phase synchronized oscillation means has a phase comparison frequency that is a common divisor of a plurality of input signals each having a different frequency, and a phase synchronization oscillation means arranged to completely divide the frequency of an input signal selected from the plurality of input signals. In a phase synchronized oscillation device having an input frequency dividing means whose frequency ratio can be controlled, all output frequencies of the input frequency dividing means are monitored, and it is determined whether or not the output frequency of the input frequency dividing means matches the phase comparison frequency. A phase-locked oscillator device is obtained which is characterized by a supervisory control means that fully controls the frequency division ratio.

Next, the present invention will be explained with reference to all the drawings.

FIG. 1 is a block diagram showing an embodiment of a phase-locked oscillator according to the present invention. In the figure, the frequency fr fz ~f
An input signal selected from n input signals is applied to an input terminal 1 and guided to an input frequency dividing means lO whose frequency division ratio can be controlled. Further, the input signal frequency fx fz ~f,
The phase synchronized oscillation means 20, which has a phase comparison frequency fok which is a common divisor of Feedback control operation 7 is performed so that the phase difference between the two becomes minimal. Furthermore, the supervisory control means 40 uses the output of the input frequency dividing means 100 as an input signal, and completely identifies whether or not the frequency of the input signal matches the phase comparison frequency foVc of the phase synchronized oscillation means 200. If they do not match, the input frequency dividing means Full control of IO frequency division ratio. Therefore, even if the signal applied to the input terminal l is switched to another signal with a frequency f1 fz -f, the output of the input frequency dividing means 10 will match the phase comparison frequency fa due to the operation of the supervisory control means 40. The division ratio is controlled so that

Next, FIG. 2 is a circuit block diagram showing a configuration example of the supervisory control means in FIG. 1, and FIG. 3 is a diagram showing the frequency characteristics of the filter in FIG. 2. In FIG. 2, two filters (hereinafter referred to as FI
LI, FIL2) and a judgment circuit (hereinafter referred to as DEC) that judges all the outputs of FILl and FIL2, and the input from the input frequency dividing means 10 (shown in FIG. 1) is FILI,
Guided by FIL2, the DEC fully controls the frequency division ratio of the input frequency dividing means 10 by determining whether or not the input matches the phase comparison frequency depending on whether an output signal is present in both FILL and FIL2. . FILL, FIL2 here
are, for example, low-pass filters, .
If L2i is configured to include the phase comparison frequency fok in its passband, the DEC will monitor all the outputs of both filters, and if both are output, it will match the phase comparison frequency fo, and only one of them will match the phase comparison frequency fo. If there is an output only at , it is inconsistent with the phase comparison frequency fo and F
ILI.

Information on whether to increase or decrease the frequency division ratio of the input frequency dividing means 100 depending on which FIL2 is output? It is possible to obtain. The above description is based on the case where the passbands of both filters include the phase comparison frequency fo'e, or as shown in FIG. 3(b), the filter FIL, '
, FIL2'. In this case, DEC
All outputs of both filters are monitored, and if there is no output in both filters, the phase comparison frequency folC matches, and if there is an output in either filter, it is determined that the phase comparison frequency foC does not match. Information for determining the control direction of the division ratio of the input frequency dividing means 10 can also be obtained by the same method as described above. Furthermore, as shown in FIG. 3(C), the phase comparison frequency fo'
A band-pass filter FIL3 and a band-elimination filter FILI' having a center frequency of jc.

It is also possible to configure only one of FIL2/. If a band pass filter FIL3'e is used here, if a signal exists at the output of the filter, it matches the phase comparison frequency fo, and if it does not, it means a mismatch. If they do not match, it is possible to find a condition that matches the phase ratio frequency foVC by sequentially controlling all the possible values between the upper limit and lower limit of the frequency division ratio of the input frequency dividing means 0. . Also, the band rejection filter FILl'
, FIL2'2, if no signal exists at the output of the filter, it matches the phase comparison frequency fo, and if it does, it means a mismatch. For the mismatched and @, the phase comparison frequency fo can be adjusted by performing the same control as above.
K matching condition? can be found.

As is clear from the above description, according to the phase synchronized oscillator of the present invention, the supervisory control means for controlling the frequency division ratio of the input frequency dividing means has at most two biases regardless of the number of types of input signal frequencies. One filter for 4 people? This has the effect of making the device more compact and economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the phase-locked oscillation device of the present invention, FIG. 2 is a circuit block diagram showing an example of the configuration of the monitoring control means in FIG. 1, and FIG.
), tc+ is a diagram showing the frequency characteristics of the filter in FIG. In the figure, l...input terminal, 2...
Output terminal. lO... Input frequency dividing means, 20... Phase synchronized oscillation means, 30... Feedback frequency dividing means, 40.
. . . Monitoring control means, DEC . . . Judgment circuit, FILI, F'IL2 . . . Filter. Inspection 1 National Graduation Z Diagram 31

Claims (1)

[Claims] a phase synchronized oscillation means having a phase comparison frequency that is a common divisor of a plurality of input signals each having a different frequency; and a phase synchronization oscillation means arranged to divide the entire frequency of an input signal selected from the plurality of input signals, the frequency division ratio of which is controllable. Input frequency division means? In the phase-locked oscillator device, the monitoring control means monitors the entire output frequency of the input frequency dividing means, determines whether it matches the phase comparison frequency, and controls the frequency division ratio of the input frequency dividing means. Characteristic phase-locked oscillator.