JPS60112309A - Signal processing filter - Google Patents

Abstract

PURPOSE:To reduce greatly the circuit scale and to facilitate an easy production of an IC device by decreasing greatly the number of delay circuits used for filters in comparison with the number of those delay circuits for approximation of series and at the same time setting the delay time of each delay circuit at the special and independent value. CONSTITUTION:A main filter F1 is provided with a circuit 10 which samples the instantaneous value of an analog input signal Ain sent from an input IN and synchronously with a clock having a fixed cycle, an A/D converter 12 which converts the sampled instantaneous value into an 8-bit parallel binary code, i.e., a digital input signal Din, two delay circuits Z<-1> and Z<-m> which produce three signals x0, x1 and xm having different delay times 0, DELTAtau and mDELTAtau from said signal Din, multipliers K0, K1 and Km which multiply prescribed coefficients k0, k1 and km respectively, two adders A1 and A2 which add signals k0x0, k1x1 and kmxm to each other, a gain correcting multiplier kb, etc.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a signal processing filter technology, particularly a technology that is particularly effective when applied to digital filters. This relates to techniques that are effective for use in the U.

[Background technology]

In recent years, digital signal processing technology has come to be used in various communication fields. The information to be communicated is
It's not just audio, but images, data, and more. For example - digital television is becoming a reality.

The greatest advantage of digital television receivers is their diversification of functions. That is, reception of multiplexed audio signals, still images, etc., and pay TV programs using both TV broadcast waves and telephone lines can be easily realized. Furthermore, if the signal exchange between the video cassero L/coder and the video disc is digitized, the deterioration in image quality will be much less.

Digital fill technology is the key to this kind of digitalization.

In other words, digital filter technology replaces the many coils and capacitors commonly used in traditional analog television receivers with IOs (semiconductor integrated circuit devices), and typically requires less delay, calculation, and multiplication circuitry. Become.

The present inventor has conducted various studies regarding digital filter technology and has found that there are problems as described below.

For example, the 0 luminance signal filter, which will be explained by taking the luminance signal filter in the 1o video signal processing block for color television as an example, has a peaking characteristic at high frequency (2 to 3 MHz) V, and due to this peaking, the luminance signal is Enhances the range components and makes the image clearer (hereinafter referred to as aperture correction).

However, according to the inventor of the present invention, since the video signal processing block processes high-frequency video signals, the sampling period of the analog signal is, for example, 70 nsec (3.58 subcarriers of the color signal) based on Nyquist's sampling theorem.
A fast cycle (corresponding to 4 times MHz) is required, and the signal processing speed of digital filters corresponding to this is also fast (
Therefore, an extremely small delay per delay element is required. Configuring such a high-speed digital filter is extremely difficult to achieve with so-called silicon semiconductor integrated circuit devices, and in order to meet these conditions, further circuit improvements such as parallelization of all filters are required. The inventor has clarified that a huge number of elements are required.

In other words, according to a normal digital filter, one delay element VC consisting of a shift register and a flip-flop, and an inverter with 50 to 100 gates are required, and even one adder requires as many inverters as 50 to 200 gates. is necessary. As a result, for example, in a digital filter using high-speed parallel logic, the filter alone has a gate of IOK ~ 100, and the IC chip area becomes extremely large.
The inventors have found that there is a drawback that it is difficult to reduce costs.

Here, in order to make it easier to understand the features of the present invention,
Below, while explaining the basics of digital filters, the matters studied by the inventor prior to the present invention will be explained in more detail.

First, basic matters of digital processing will be explained using FIGS. 1 and 2. Figure 1 shows the flow of digital processing.

FIG. 2 is a diagram showing the waveforms of each processed signal in FIG. 1, with the horizontal axis representing time t and the vertical axis representing amplitude Wt.

The input analog signal f(1) is first sampled into a sample sequence fn, and then converted into a binary pulse sequence fn by an A/D converter. Next, the signal is subjected to necessary filtering operations by an adder 9 multiplier and a digital filter whose basic calculation elements are unit delay elements, and gn is output and converted into an analog signal g(t) by a D/A converter.

Next, we will briefly discuss time-discrete systems and their analysis, which are the basics of digital filters. While the action of a time-continuous system (analog system) on an input signal is expressed by a differential equation, the action of a time-discrete system is expressed by a difference equation. That is, in a time-discrete system, its input signal is X(nT)' and its output signal is Y(n
T), and when ak and bk are constants, the input-output relationship is expressed by the constant coefficient winning differential equation %Formula %(1).

The above formula is the past input x ((n-k)T) and the past output y
((n-k)T) according to a predetermined rule to extract the latest output Y(nT).

There are three types of operations included in equation (1): addition, multiplication, and unit time delay. Therefore, if the adder 1 multiplier and unit delay element are considered as constituent elements, the configuration shown in FIG. 3 can be immediately obtained using these elements. Here bk=O
In the case (k=1.2...N), that is, when there is no return path, the circuit configuration is shown by the portion surrounded by a dotted line in FIG. This is called an acyclic filter. On the other hand, a circuit in which at least one of bk (k=1.2...N) is not zero is called a cyclic filter.

Next, Z transformation, which is a time-discrete signal analysis method, will be briefly explained. As a starting point at an arbitrary time, a sample value series (f(rrT)) that occurs at an interval of T seconds = f(o) + f(T)l f(zt
)i""""t f(lt)+... The integer series of complex numbers 2 is called the 2 transformation of (f(nT)).

Here, when the above formula (1) is Z-transformed, becomes.

get. In the acyclic filter described in the embodiment of the present invention, ')I*J...bK are all zero, so it can be seen that the transfer function H(z) is as follows.

Next, image processing in digital television, which is the background of the present invention, will be briefly explained.

Nikkei Electronics magazine, November 23, 1981,
As shown on pages 238 to 240, in the video signal processing block, the input signal that has passed through the A/Di converter is divided into a luminance signal and two color signals. It is designed to be supplied to The brightness filter has a variable tuning characteristic that provides peaking of, for example, +6 to -3 dB, and the peaking serves to enhance the crystal region component of the brightness signal and sharpen the image (see FIG. 4). The basic configuration example of this high-frequency emphasis (contour compensation) filter was published in 1981 (Showa 56) 5
This is shown on pages 112 and 113 of ``Digital Signal Processing of Images'' by Takahiko Fukinuki (published by Nikkan Kogyo Shimbun), published on May 25th, and the basic circuit configuration is as shown in Figure 5, a delay circuit. It is composed of z-K and adder AK. In other words, the circuit configuration is such that the input signal X is branched into two signals with different delay amounts by the delay circuit 2, the two signals are added together, and the addition result is used as the output signal Y. .

According to Kenji, the inventor of the present invention, it has been found that the digital filter shown in FIG. 5 has a so-called comb-shaped transfer characteristic in which peaks and peaks appear mutually.

In order to achieve smooth characteristics such as a low-pass filter or a bypass filter that can be obtained using passive elements such as ordinary coils and capacitors with the comb-shaped filter characteristics described above, it is necessary to An infinite series must be constructed in which one element is the comb filter characteristic. In other words, if the actually obtained transfer function is far from the desired transfer function, the desired transfer function can be obtained by constructing an infinite series whose terms are the actually obtained transfer functions. Therefore, the delay circuit Z
If k is infinitely many (to form an isometric infinite series,
Theoretically, any filter characteristic can be obtained.

However, as a practical matter, it is impossible to use an infinite number of delay circuits, so in reality.

We have no choice but to compromise by approximating the terms of the above series to a finite number. Still, in order to approximate the characteristics of, for example, a ten-ki analog filter with a finite number of delay circuits,
In order to increase the accuracy of the approximation to a practical level, it is inevitable that a considerable number of delay circuits and circuits attached to each delay circuit will be required.

From this point of view, it has the frequency characteristics shown in Fig. 4,
In order to obtain a digital filter that is suitable for practical use, the present inventor studied a circuit as shown in FIG. 6, that is, a digital filter, prior to the present invention.

That is, the digital filter shown in FIG. 6 includes a sampling circuit 10 that samples the instantaneous value of an analog input signal AIn in synchronization with a clock φ having a constant period, and a digital filter that converts the sampled instantaneous value into a digital signal consisting of, for example, 8-bit parallel binary codes. A/D converter 12 converting into input signal DIn
, n delay circuits z', z"-2, z"-", ・
-・-, Z-"color rz slow [circuit group z-X, n+1 multipliers K.l Kl l Kll 1 "'...K
A multiplier group KX consisting of n, a sword Ω consisting of n multipliers
Digital output signals obtained from the calculator group Ax and the adder group Ax. It is composed of a D/A converter 14 that converts ut into an analog output signal Aou, and the like.

The parallel digital input signals Din are each outputted by the delay circuit group zx at 0. △τ, 2△τ, 3△τ.

......n+1 signals X with a delay time of n△τ
0yxI I X2 j XA 9 . . . Divided into Xn. Signal xo output from delay circuit group Z-X
l xl-, X21XIl+ ......t Xn
are each given a predetermined coefficient k by the multiplier group KxK. l, klj key kat..., kn is multiplied. In this way, n+1 signals kOX are each given a Δτ and a coefficient Kk at a predetermined delay time.
OI kIXII )C2x2+ k3X31 ”””
1knxn are added together by the adder group Ax, and the addition result (koxo +, 181+, 2x□+, 3x30, . . . knxn) becomes an output signal Dout based on parallel digital data. And this digital output signal. By passing ut through the D/A converter 14, an analog output signal A is obtained. You can get ut.

In addition, if you want to extract the output as digital data,
Of course, the D/A converter 14 is unnecessary.

By the way, in order to use the digital filter described above to approximate the characteristics of an analog filter as shown in FIG. 4 in a practical fAf degree, the delay circuit z-
1 to zn requires at least several tens to several hundreds.

Accordingly, a multiplier K is provided for each delay circuit.
. -Kn and 710 calculators each require tens to hundreds of units. Furthermore, each delay circuit Z. Since the digital signal to be delayed by -2n is, for example, an 8-bit parallel signal, a plurality (eight) of delay element arrays are required for each delay circuit. Since each delay element constituting the delay element array is constructed using a shift register of, for example, a 71J/70 block, each requires a digital circuit of several gates.

For this reason, the number of gooses required for the digital filter as a whole inevitably becomes extremely large. In other words, the problem mentioned at the beginning occurs.

Furthermore, an attempt is made to configure a so-called aperture correction filter, which is used to enhance the outline of an image by strengthening the high-frequency portion of the luminance signal in the image signal of a color television, using the digital filter described above. Then, it is necessary to be able to handle high frequency ranges such as 2 to 3 MHz.

However, when trying to assemble filter characteristics using the series approximation described above in such a high frequency region using the huge number of digital gates described above, individual operation delays in each digital gate or circuit, especially in the 710 calculator group, occur. It has been found that there are problems in that the delay in operation becomes large, the correction circuit for compensating for it becomes complicated, and the number of gates becomes extremely large, making it extremely difficult to realize the delay.

To prevent the above problems from occurring, it is necessary to obtain a practical filter that operates in a high frequency region, such as the aperture correction filter mentioned above, or to form it within a single semiconductor integrated circuit device. This was considered hopeless in terms of circuit scale and speed.

[Object of the Invention] An object of the present invention is to provide a digital filter technology that allows a digital filter having desired characteristics to be constructed on a small scale, thereby making it possible to easily incorporate it into a semiconductor integrated circuit device. It is.

The present invention also provides a digital filter technique that can be used to perform so-called anomaly correction, which emphasizes the contours of an image by emphasizing the high-frequency portion of the luminance signal of a color television.

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows σ).

In other words, by limiting the number of delay circuits used in the filter to a much smaller number than the number required for series approximation, and by setting the delay time of each delay circuit to a special value that is independent of each other, a huge circuit size can be reduced. It is possible to obtain the desired filter characteristics without using the necessary series approximation, thereby significantly reducing the circuit scale.
Furthermore, the present invention achieves the objectives of enabling operation in a high frequency region and facilitating fabrication into a semiconductor integrated circuit device.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 6 shows an embodiment of the digital film according to the present invention. In addition to the digital filter shown in the same figure, the so-called Ano digital filter (consisting of a char correction filter and a σ) digital filter enhances the high frequency range of the luminance signal in the video signal to emphasize the outline of the image. It is now formed as an internal circuit of a video processor formed as one semiconductor integrated circuit device.

First, the outline of the digital filter shown in FIG. 7 is as follows.

In other words, input signals that have not been digitized are passed through multiple σ delay circuits to generate multiple signals with different delay amounts, and then the multiple signals are added together and output, thereby reducing the gap between input and output. In order to provide a predetermined frequency characteristic to σ), the delay amount of each of the plurality of delay circuits is independently set to a non-sequential special value, thereby achieving the above frequency characteristic. ℃・ru.

Here, multipliers are provided to perform coefficient correction on the amplitude data of the plurality of signals, respectively, and predetermined frequency characteristics can be provided by correction values set individually in these multipliers.

, - Also, particularly in this embodiment, a first signal which has a first delay amount, that is, a delay time, and whose amplitude data is multiplied by a first correction coefficient from the input signal; a second signal having a delay time and whose amplitude data is multiplied by a second correction coefficient; and a second signal which has a third delay time and whose amplitude data is multiplied by a third correction coefficient. generating a third signal;
．． The second and third signals are added together, and the first and third signals are added together. Second. each of the third delay times and the first and second delays;
．． A predetermined frequency characteristic is obtained by operating each of the third correction coefficients independently. As a result, the two delay circuits essentially constitute the main part of the digital filter. With this simple configuration, the characteristics of the aperture correction filter described above, which have flat characteristics in the low frequency range and peak characteristics in the high frequency range, can be realized.

The digital filter FI2 of the embodiment shown in FIG. 7 is composed of a main filter F and a sub-filter F. The main filter p1 constitutes the main part of the digital filter according to the present invention, and is a sampling circuit 1 that samples the instantaneous value of the analog input signal A1n derived from the input IN in synchronization with a clock φ having a constant period.
0, an A/D converter 12 that converts the sampled instantaneous value into, for example, an 8-bit parallel binary code, that is, a digital input signal Dln'VC, and 3 with mutually different delay times O1△τ9m△τ from this digital input signal DIn. One,
Two σ) delay circuits z that generate the signals Xo, XI, xm
, = l , z-m - the above three signals xQ l x,
A predetermined coefficient k for each of y and Xrn. Each signal k multiplied by a coefficient TI, into a multiplier Ko, which multiplies l'l km. Add xO, klxl, kmxm to each other 2
σ) Multipliers A, , A2+ and multiplier K for gain correction
b, etc.

The sub-filter F2 is provided as an auxiliary device, and depending on the temperature
It is configured. This subfilter F1! has a comb-shaped filter characteristic as described above.

For the delay circuits z'', zm, and zn, shift registers constituted by, for example, 70 flips are used.Furthermore, the multiplier K.

K, , Km, and Kb do not perform formal multiplication operations, but are constructed with extremely simple circuits such as logic circuits that shift each bit digit of parallel digital data to upper or lower positions, or logic circuits that take complements. ing. This makes it possible to perform arithmetic operations such as multiplication by a power of 2 and inversion of the sign on the digital data (XOtX1+Xm) VC consisting of parallel binary codes. The design method will be discussed later).

Specifically, in the digital filter FI2 having the above configuration, the delay time τ2mΔτ of the main filter F, (IQ delay circuit Z-'', z-m) is set to 1.
clock minutes (70nsec), 5 clock minutes (350nsec)
sec), and the above coefficients ko, , ,
, km are set to 5°-1, respectively.

And the coefficient k. -3, 5, -2, 7, -2
,4,-2,-1,3,O.

+4. +12 stepwise and measured the transfer characteristics in each case, as shown in Figure 7, the IM
VC2 with flat parts in the low range below Hz
A filter characteristic having a peak around ~3MH2 was obtained. The digital filter thus obtained could be fully used as the aperture correction filter. What's more, it's worth noting 4
? , the size of the peak is the above coefficient k. By simply manipulating the
This means that it was possible to variably adjust W'.

This means that the main filter 1' can not only have the desired characteristics in the high frequency range, but also that its characteristics can be varied without disturbing the balance. It means having a function. Such a function of smoothly varying characteristics is a very important function as a filter, and is extremely difficult even for ordinary analog filters. In this sense, the digital filter FI2 provides not only the negative effect of simply approximating the characteristics of analog fill, but also provides more advanced characteristics that are difficult to realize even with analog filters. This has a positive effect.

In the case of the embodiment, the main filter F is approximately 5MH
In the unused region above z, a characteristic that tends toward the peak appears again, but this portion can be easily removed by the comb-shaped characteristic of the sub-filter F. FIG. 7 shows the sub-filter 1. This shows the characteristics finally modified by.

According to the present invention, there are only three 7]0 calculators'ff:
A digital filter having desired peaking characteristics can be obtained with an extremely simple circuit configuration.

Next, a design method for obtaining a filter configuration as shown in FIG. 7 will be specifically explained.

As shown in FIG. 4, the desired characteristics are flat characteristics in the low frequency region (■) and peaking characteristics (■) at 2 MHz, for example. Note that the characteristics indicated by ■ in the figure can be obtained by reducing the force of the sub-filter F? to 0 as described above, so we will first focus on the characteristics indicated by ■ and ■ and discuss '1-''f.

Using Equation (5) described in Section 1, Background Art, the 5-cyclic filter H (support) is expressed as H(2)=anz-"+amz-m+c -...
(Set as 61.

First, to ensure flatness in the low frequency range...
・・・・・・・・・・・・・・・・・・・・・(7)(7
) By substituting the formula VCz=1 (f = O), we get -ann-
It becomes amm-0.

If we set n = 1 to simplify the circuit, an = -amm
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・(Substituting 81(8) into (6) gives C2.== ammZ +amz +c=-am(mz
-1-z"rL-) Ship H (21= Bx (mz-1z-m+o) -""・
”(9JHere, if the gain in the low frequency range is 1, Ray,
In other words, assuming that H(zl/2=1 (f=0)=', substituting equation 00) into equation (9)... ...I
get.

Here, under the condition of Bx-1, m is 2+ 3t 4t 5y
As a result of examining whether the desired peaking characteristics could be obtained by changing the number m to 5, m=5 was selected.

therefore, get.

Next, under the condition of m===5, set Bx to -3, 5, -2, 7 degrees -2, 4, -2, -1, 3, 0, +4. +12 in steps and actually measure the change in the transfer characteristics. At the same time, a sub-filter (<C-shaped filter) Ft is inserted in order to reduce the high-frequency peak and obtain the characteristic shown in Figure 4 (1+z-1
multiply).

As a result, the transfer function is.

・・・・・・・・・・・・・・・・・・・・・・・・
...(13). When this transfer function is converted into a concrete circuit configuration, it becomes a '1'' configuration as shown in FIG.

Five, =5. Kb=Bx, corresponding to z-""=z-".

The frequency characteristics of the filter were actually measured, and it was confirmed that the output of the D/A converter shown in FIG. 7 had extremely excellent peaking characteristics as shown in FIG. 8.

In this way, the present invention makes it possible to set the delay times of each delay circuit to special values that are independent of each other, and to obtain the desired filter characteristics without using series approximation that requires an enormous circuit scale. This is a major feature of

As described above, the digital output signal of the digital filter FI2 is provided with predetermined characteristics. If necessary, ut is returned to the analog signal output Aout by the D/A converter 14 and is applied, for example, to a control grid of a color CRT (cathode ray tube) as a brightness signal of a television.

FIG. 9 shows an example of a video signal processing block in which the digital filter F□ is incorporated. A video signal processing block 100 shown in the figure is responsible for the main part of image signal processing in, for example, a color television or other video equipment, and this part is incorporated into the semiconductor integrated circuit together with the digital filter Plt. This greatly advances digitalization in color televisions and other video equipment, and greatly simplifies equipment configuration.
Moreover, advantages such as cost reduction can be obtained. In particular, the video signal processing block 100 shown in FIG.
It is mainly configured to collectively process video signals of color chimps, and includes a signal separation circuit 102 that separates a color signal and a luminance signal from the video signal, a comb filter 104 that passes the luminance signal, The digital filter F12 provided for aperture correction, the multiplier 106 for contrast adjustment, the color signal filter 108, the automatic color control circuit 110, and the color killer circuit 112.
, a PAL identification circuit 114, a control bus interface 116 for exchanging data with an external OPU, a color decoder 118, a multiplier 120 for color saturation, a multiplexer 122, a phase-locked loop (PLL) for color synchronization. 124, beam current switching control circuit 12
6, etc. are integrated into one semiconductor integrated circuit device. 7℃, external A/D converter 12 and D/A
Converters 14 and 16 are connected, so that the video signal, which was an analog signal, can be processed as digital data, and the processing result can be converted back into an analog signal and used, for example, to control the ORT. There is.

The above video signal processing block can also be integrated into a semiconductor integrated circuit device using the digital filter PI2 according to the embodiment described above.
This can be achieved relatively easily. Further, FIG. 10 shows an application example that is a more specific embodiment of the embodiment shown in FIG. Here, the output of the digital-to-analog converter is configured to drive the CRT via a power amplifier. Further, G surrounded by a dotted line in the figure is a peaking amount adjuster, which allows the peaking amount to be varied. In addition, signal A. is a composite video signal, signal B. is the luminance signal.

〔effect〕

(11) The digitized input signal is passed through a plurality of delay circuits to generate a plurality of signals having different delay amounts, and the plurality of signals are added together and outputted, and By setting each delay amount of the delay circuit independently to a non-series special value, it is possible to construct a digital filter with desired characteristics on a relatively small scale. The effect is that integrated circuit devices can be easily implemented.

(2) Furthermore, it is possible to obtain the effect that the desired filter characteristics can be easily obtained especially in the high frequency region.

(3) Furthermore, after obtaining a predetermined filter characteristic, it is possible to easily provide a function that allows the characteristic to be smoothly varied without disturbing the overall balance.

(4) Therefore, it is possible to form a digital filter in a semiconductor integrated circuit device that can be used, for example, to perform so-called aperture correction, which enhances the high-frequency portion of the luminance signal of a color television to emphasize the contours of the image. Effects can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above-mentioned Examples, and various changes can be made within the scope of the invention without departing from the gist thereof. Needless to say. For example, the delay circuit may use a charge transfer element such as an OOD.

[Application field]

In the above explanation, the invention made by the present inventor was applied to the high frequency filter technology used in the video signal processing of color television, which is the field of application that formed the background of the invention, but the invention is not limited to this. For example, it can also be applied to digitization techniques for various frequency filters in communication systems. The present invention can be applied to devices in which the delay time of at least one delay element is set independently of the frequency of an input signal, ie, digital filters, comb filters, and the like.

[Brief explanation of drawings]

Fig. 4 is a diagram for explaining the flow of digital signal processing, Fig. 2 is a diagram showing the signal waveform of each signal shown in Fig. 1, Fig. 3 is a diagram illustrating the configuration principle of the digital filter, 5 is a circuit diagram showing the basic configuration of a digital filter; FIG. 6 is a circuit diagram of a digital filter considered by the inventor before this invention; Fig. 7 is a circuit diagram showing the configuration of a digital filter that is an embodiment of the present invention, Fig. 8 shows the frequency characteristics of the output signal of the digital filter shown in Fig. 7, Fig. 9 shows the present invention. FIG. 10 is a diagram showing still another example of application of the digital filter of the present invention. IN...Input signal, OUT...Output signal, z-1~
n k z-, z-, z-m-...delay circuit, Ao "'-An
, Ak. Am... blade counter, K0 to Kn, Km,... multiplier, z-X... delay circuit group, Ax... adder group,
Kx... Multiplier group, 10... Sampling interval, 1
2...Analog-to-digital converter (A, /D converter), 14.16...Digital-to-analog converter (D/D converter)
A converter), Aln...analog input, DIn...
Digital input, Dou□°゛°digital output, Aout
,,,analog output, φ...clock, FIFF2・
... Filter, k゛, 2 ... Luminance signal filter, 10
0... Video processor, 102... Signal separation circuit,
104... Comb filter, 106... Multiplier for contrast adjustment, 108... Color signal filter, 110...
...Automatic color control circuit, 112...Color killer circuit, 114...PAL identification circuit, 116...
・Control bus interface, 118...
・Color decoder, 120...color saturation multiplier, 1
22... Multiplexer, 124... Phase-locked loop for color synchronization, 126... Beam current control circuit.

Claims (1)

[Claims] 1. Input/output is achieved by passing an input signal through a plurality of delay circuits to generate a plurality of signals with different delay amounts, and then calculating and outputting the plurality of signals with each other. A signal processing filter having a predetermined frequency characteristic between the signal processing filters, wherein the delay amounts of each of the plurality of delay circuits are independently set to non-series special values,
A signal processing filter characterized in that it has the above-mentioned frequency characteristics correspondingly. 2. A patent characterized in that multipliers are provided for performing coefficient correction on the amplitude data of the plurality of signals, and predetermined frequency characteristics are provided by correction values set individually in these multipliers. A signal processing filter according to claim 1. 3. Passing the input signal through multiple delay circuits generates multiple signals with different delay amounts, and then calculates and outputs the multiple signals to create a predetermined frequency characteristic between input and output. A signal processing filter configured to provide a first signal processing filter having a first delay amount and a first signal amplitude data multiplied by a first correction coefficient from the input signal; a second signal that has a delay amount and whose amplitude data is multiplied by a second correction coefficient; and a second signal that has a third delay amount and whose amplitude data is multiplied by a third correction coefficient. A third signal is generated, and the first signal is further generated. Second. The third signals are added to each other, and the first and third signals are added together. Second. Each of the third delay amounts and the first delay amount described above. A signal processing filter characterized in that predetermined frequency characteristics are obtained by manipulating second and third correction coefficients respectively.・4. Above 1. Second. 4. The signal processing filter according to claim 3, wherein one of the third delay amounts is set to zero. 5. Above 1. Second. 5. The signal processing filter according to claim 3, wherein at least one of the third correction coefficients is set to be negative.