GB2150381A - A signal processing filter - Google Patents

Abstract

A digital filter wherein the number of delay circuits for the filter is limited to be much smaller than the number thereof for performing a series approximation, and the delay times of the respective delay circuits are set at special values independent of one another, whereby the circuit scale is sharply reduced. The digital filter (F1) includes a main filter (F1) and a sub filter (F2). A sampling circuit (10) samples the instantaneous values of an analog signal (Ain). An A/D converter (12) converts the sampled value into parallel binary codes. The filter (F1) comprises two delay circuits (Z<-1> and Z<m>) which produce three signals having unequal delay times; multipliers (Ko, Kl and Km) which multiply the three signals by predetermined coefficients; two adders (A1 and A2) which add up the signals multiplied by the coefficients; and a gain correcting amplifier (Kb). The sub filter (F2) comprises one delay circuit (Z<-n>) and one adder (A3). <IMAGE>

Description

SPECIFICATION A signal processing filter The present invention relates to a signal processing filter, and more particularly to a digital filter.

In recent years, digital signal processing techniques have come into use in various fields of communications. Information for the communications covers various items which include, not only voices, but also pictures, data, etc. For example, television of a digital system is being actualized. The most important advantage of a digital television receiver consists in the multifarious functions thereof, such as the reception of multiplexed aural signals or still pictures. Pay television which uses both television broadcast waves and a telephone circuit can be simply realized. In addition, when the exchange of signals with a video cassette recorder or a video disk is digitized, degradation in the quality of picture becomes much less. An important key to such digitization is digital filter technology.

The digital filter technology replaces large numbers of coils and capacitors often used in a conventional analog television receiver, with ICs (semiconductor integrated circuit devices), which are usually composed of delay, adder and multiplier circuits.

We have made a detailed investigation on digital filter technology, which has revealed a serious problem, which is now discussed.

By way of example, a luminance signal filter in the video signal processing block of an IC for colour television will be referred to. The luminance signal filter exhibits a peaking characteristic at high frequencies (2 - 3 MHz). Owing to the peaking, it intensifies the higher frequency component of a luminance signal so as to render a picture distinct (hereinbelow, termed "aperture correction"). We have found that, since the video signal processing block processes video signals of high frequencies, it requires on the basis of Nyquist's sampling theory such a short sampling period that the sampling period of an analog signal is, for example, 70 nsec (corresponding to quadruple of the subcarrierfrequency 3.58MHz of a colour signal).The signal processing speed of a ditigal filter corresponding thereto must be enhanced, and the digital filter whose delay per delay unit is very short is necessitated. A digital filter having such a high speed is very difficult to realize in practice with a silicon semiconductor integrated circuit device.

We have found that, in orderto fulfill the above requirement, it is necessary to provide a complete parallel arrangement of the filter, so an enormous number of elements are needed.

More specifically, with an ordinary digital filter, one delay unit constructed of a shift register and a flip-flop circuit requires as many inverters as 50-100 gates, and also one adder requires as many inverters as 50200 gates. We have found that, as a result, in a digital filter untilizing high-speed parallel logic circuits by way of example, a filter circuit requires inverters on the order of 10 k- 100 k gates, which brings about the disadvantages that the area of an IC chip becomes extremely large and that a reduction in cost is difficult.

In order to facilitate better understanding of the features of the present invention, features which were studied by us prior to the present invention will be explained along with the fundamentals of the digital filter.

Referring first to Figures 1 and 2 of the accompanying drawings, the fundamentals of digital processing will be explained. The flow of the digital processing is shown in Figure 1. Figure 2 is a diagram showing the waveforms of processing signals in Figure 1, plotted to time ton the abscissa axis.

An input analog signal f(t) is sampled into a sample series fn, which is thereafter converted into a train of binary pulses fn by an A/D (analog-to-digital) converter 1. Subsequently, the binary pulse train is subjected to a required filtering operation by a digital filter 2 whose basic operating elements are an adder, a multiplier and an elemental delay circuit. Then, a binary pulse train gn is delivered, which is converted into an analog signal g(t) by a D/A (digital-to-analog) converter 3.

Next, a time-discrete system fundamental to the digital filter and the analysis thereof will be briefly stated.

Whereas the action of a time-continuous system (analog system) on an input signal is expressed by a differential equation, the action of the time-discrete system is expressed by a difference equation. More specifically, with the time-discrete system, letting X(nT) denote the input signal thereof, Y(nT) denote the output signal thereof, and ak and bk denote constants, the relationship of inputs and outputs is expressed by the following linear difference equation with constant coefficients:

The above equation signifies that the newest output Y(nT) is taken out by combining past inputs x ((n - k) T) and past outputs y ((n - k) T) under predetermined rules. Operations included in Equation (1 ) are the three sorts of addition, multiplication and elemental time delay.Accordingly, an adder, a multiplier and an elemental delay circuit are considered as constituents, and an arrangement shown in Figure 3 is immediately obtained using these constituents. In the case where bk = 0 (k = 1,2 ..... N), namely, in the absence of a feedback path, the circuit arrangement is shown by a part enclosed with a dotted line in Figure 3. It is called a "non-circular type filter". In contrast, a circuit in which at least one of bk (k 1,2 N) is not zero is called a "circular type filter".

Next, the Z-transform which is an expedient for analyzing a time-discrete signal will be briefly explained.

when a series of sampled values which are generated at intervals of T seconds with an arbitrary time as the origin is given by: {f(nT)} = f(O), f(T), f(2T) ----, f(nT) ....., the power series of a complex number z:

is called the "Z-transform of {f(nT)} Here, when Z-transformed, Equation (1) becomes:

Since a transfer function is

the following is obtained from Equation (3):

In the transversal or non-circular type filter to be described in an embodiment of the present invention, all of bl, b2, and bk are zero.It is therefore understood that the transfer function H(Z, becomes:

Next, there will be briefly explained picture processing in the digital television which has formed the background of the proposal of the present invention.

As indicated in 'Nikkei Electronics' dated November 23, 1981, pp.238-240, in a video signal processing block, an input signal having passed through an A/D converter is distributed into a luminance signal and a colour signal and the luminance signal is fed to a luminance signal filter through a comb filter. The luminance filter has a frequency characteristic which affords peaking of, e. g., +6 - -3 dB, and the peaking intensifies the higher frequency component of the luminance signal and functions to make a picture distinct (refer to Figure 4). An example of the basic arrangement of the higher frequency emphasis (profile compensation) filter is shown on pages 112 and 113 in 'Digital Signal Processing of Picture' by Takahiko Fukinuki, published by Nikkan Kogyo Shinbunsha on May 25, 1981.As shown in Figure 5, the basic circuit arrangement is composed of a delay circuit Z-k and an adder Ak. That is, an input signal Xis branched by the delay circuit Z-k into two signals having magnitudes of delay unequal to each other, the two signals are added to each other, and the added result is provided as an output signal Y.

We have found that the digital filter shown in Figure 5 of the accompanying drawings exhibits a transfer characteristic of the so-called comb type in which dips and peaks appear alternately.

When a smooth characteristic as in a low-pass filter or high-pass filter which is manufactured by employing ordinary passive elements such as coils and capacitors is to be realized by the use of the filter characteristic of the comb type characteristic described above, an infinite series one element of which is the aforementioned comb type filter characteristic must be organized. That is, in the case where a transfer function actually obtained is widely different from a transfer function aimed at, the infinite series whose terms are such transfer functions actually obtained is organized, whereby the transfer function aimed at can be obtained. Accordingly, theoretically any filter characteristic can be attained when an equivalent infinite series is organized using the delay circuits Zk in an infinitely large number.

In practice, however, it is impossible to use the infinite number of delay circuits. In actuality, therefore, there is no other way than making a compromise by means of an approximation in which the terms of the series are in a finite number. Nevertheless, when the characteristic of the above analog filter, for example, is to be approximated by the finite number of delay circuits, a considerable number of delay circuits and circuits belonging to the respective delay circuits are inevitably required in order to raise the precision of the approximation to a practicable level.

From such viewpoint, to the end of obtaining a practicable digital filter having the frequency characteristic shown in Figure 4, we have investigated using a circuit as shown in Figure 6, of the accompanying drawings.

The digital filter shown in Figure 6 is constructed of a sampling circuit 10 which samples the instantaneous values of an analog input signals, in synchronism with a clock pr of fixed period; an A/D converter 12 which converts the sampled instantaneous value into a digital input signal Din consisting of parallel binary codes of, e.g., 8 bits; a group of delay circuis Z-" which consist of n delay circuits z-, Z-2, Z-3, ..... and Z-n; a group of multipliers Kx which consist of (n + 1) multipliers K0, K1, K2, K3 and Kn; a group of adders Ax which consist of n adders; and a D/A converter 14 which converts a digital output signal Dout derived from the group of adders Ax, into an analog output signal Aout.

The parallel digital input signal Din is divided by the group of delay circuits Zx into (n + 1) signals xO, x" x2, X3, and x0 which have delay times 0, AT, 2 AT, 3 AT, and n AT, respectively. The signals xO, X1, x2, x3 X3,.....

and x0 delivered from the group of delay circuits z-x are respectively multiplied by predetermined coefficients k0, k1, k2, k3 and k0 by means of the group of multipliers Kx. (n 1) signals koXoZ k1x1, k22, k3x3, ..... and knxn, which have been endowed with the predetermined delay times k AT and coefficients kk individually in this way, are added up by the group of adders Ax. The added result (K0x0 + kixi + k2x2 + k3x3 + ..... + knXn) becomes the output signal Dout based on the parallel digital data. By passing the digital output signal Dout through the D/A converter 14, the analog output signal Aout can be obtained.

In the case where the output is provided as the digital data, the DIA converter 14 is of course unnecessary.

When the characteristic of the analog filter shown in Figure 4, for example, is to be approximated at a practicable precision by the use of the digital filter stated above, the delay circuits Z 1 - Z-" are required in a number of, at least, several tens to several hundred. Consequently, the multipliers K0 - K0 as well as the adders which are provided for the respective delay circuits are required in the number of several tens to several hundred. Further, since the digital signal to be delayed by each of the delay circuits Z0- Z0 is the parallel signal of, e. g., 8 bits, a train of a plurality of (eight) delay units is required for each delay circuit.The individual delay unit constituting the delay unit train is constructed of a shift register composed of, for example, flip-flops, and therefore requires a digital circuit of several gates. For this reason, the number of gates needed for the whole digital filter becomes very great inevitably. That is, the problem stated before arises.

Moreover, when the digital filter described above is used with the intention of constructing a filter for the so-called aperture correction, which is employed for, e. g., intensifying the higher frequency part of a luminance signal in the picture signal of colour television so as to emphasize the profile of a picture, it needs to handle a high frequency region of 2 - 3 MHz. However, when the organization of the filter characteristic based on the foregoing series approximation is intended in such high frequency region by the use of the enormous number of digital gates mentioned above, we have found that operation lags increase in the individual digital gates or circuits, especially operation lags in the group of adders.Furthermore, if a correction circuit is provided for compensating for the operation lags it becomes complicated and the number of gates required for the correction circuit becomes very large, so the realization is very difficult.

On account of the problems thus far described, it has been very difficult in points of a circuit scale, speed, etc. to construct a practicable filter which operates in a high frequency region, for example, the filter for the aperture correction, and further to form the filter within a single semiconductor integrated circuit device.

It is an object of the present invention to provide digital filter technology according to which a digital filter having a desired characteristic can be constructed on a small scale, whereby the implementation thereof as a semiconductor integrated circuit device is easy.

Another object is to provide digital filter technology which is usable for the so-called aperture correction that intensifies the higher frequency part of the lumance signal of colour television so as to emphasize the profile of a picture.

According to the present invention there is provided a signal processing filter including: (a) an input terminal to which an input signal is applied; (b) a first delay circuit whose input is connected to said input terminal and whose output provides a signal delayed by a first delay time (T1); (c)an m-th delay circuit whose input is connected to said input terminal and whose output provides a signal delayed by an m-th delay time (Tm); (d) a first coefficient circuit whose input is connected to the output of said first delay circuit; (e) a second coefficient circuit whose input is connected to the output of said m-th delay circuit; and (f) a coupling circuit whose first input is connected to an output of said first coefficient circuit and whose second input is connected to an output of said second coefficient circuit; wherein a value (Tm/Ti) obtained by dividing the m-th delay time by the first delay time is a value (m) substantially close to an integer, and wherein another integer (n) exists between the integer 1 and the value (m), and a signal component having an n-th delay time (tun) corresponding to the integer (n) is omitted from application to said coupling circuit.

The present invention will now be described in greater detail by way of example with reference to the remaining figures of the accompanying drawings wherein: Figure 7 is a circuit and system diagram showing the arrangement of one embodiment of a digital filter according to the present invention; Figure 8 is a graph showing the frequency characteristics of output signals from the digital filter shown in Figure 7; Figure 9 is a block diagram showing a first example of the application of the digital filter shown in Figure 7; and Figure 10 is a block diagram showing a second example of application of the digital filter shown in Figure 7.

Referring first to Figure 7, the digital filter is constructed as a filter for the so-called aperture correction which intensifies the higher frequency part of a luminance signal in a video signal so as to emphasize the profile of a picture. Further, this digital filter is formed as the internal circuit of a video processor which is formed into a single semiconductor integrated circuit device.

First, the outline of the digital filter shown in Figure 7 is described.

A digitized input signal is passed through a plurality of delay circuits, thereby to produce a plurality of signals which have magnitudes of delay unequal to one another, and the plurality of signals are added to one another and then delivered as an output, thereby to establish a predetermined frequency characteristic between the input and the output. The magnitudes of delay of the plurality of delay circuits are set at non-series-based special values independently of one another, whereby the frequency characteristic is afforded.

Here, multipliers which perform coefficient corrections for the amplitude data of the plurality of signals respectively are comprised, and predetermined frequency characteristics are afforded by correction values which are individually set in these multipliers.

Particularly in this embodiment, from the input signal, there are produced a first signal which is endowed with a first delay magnitude or delay time and whose amplitude data is multiplied by a first correction coefficient, a second signal which is endowed with a second delay time and whose amplitude data is multiplied by a second correction coefficient, and a third signal which is endowed with a third delay time and whose amplitude data is multiplied by a third correction coefficient. Further, the first, second and third signals are added up, while the first, second and third delay times and the first, second and third correction coefficients are controlled independently of one another, whereby predetermined frequency characteristics are attained. Thus, the principal portion of the digital filter is constructed, in effect, of the two delay circuits.

The characteristic of the filter for the aperture correction, which exhibits a flat characteristic in a lower frequency region and a peak characteristic in a higher frequency region, is realized with the simple arrangement.

The digital filter F12 of the embodiment shown in Figure 7 is constructed of a main filter F1 and a sub filter F2. The main filter F, forms the major portion of the digital filter according to this invention. It is composed of a sampling circuit 10 which samples the instantaneous values of an analog input signal Ain introduced from an input IN, in synchronism with a clock pulse of fixed period; an AiD converter 12 which converts the sampled instantaneous value into parallel binary codes of, e.g., 8 bits or into a digital input signal D10; two delay circuits Z- and z-m which produce three signals x0, xq and xm having delay times 0, AT and may unequal to one another, from the digital input signal D10; multipliers Ko, K1 and Km which multiply the three signals x0, xi and xm by predetermined coefficients ko, ka and km, respectively; two adders A1 and A2 which add up the signals kÛxor k1x1 and kmxm multiplied by the coefficients; and a gain correcting multiplier Kb.

The sub filter F2 is composed of one delay circuit Z-" and one adder A3. This sub filter F2 exhibits a comb type filter characteristic as stated before.

Used as each of the delay circuits z-, z-m and z is a shift register which is formed of, for example, flip-flops. Each of the multipliers Ko, K" Km and kb does not perform a true multiplying operation, and it is formed of a very simple circuit, such as a logic circuit which shifts the respective bits of the parallel digital data to upper or lower places or a logic circuit which takes a complement. Thus, the digital data (x0, xa, xm) consisting of the parallel binary codes can be subjected to arithmetic operations such as the multiplication based on the power of 2 and the inversion of the codes (a design method for obtaining such arrangement of the digital filter will be described later).

In the digital filter F12 of the above arrangement, the delay times AT and mAT of the delay circuits Z-1 and z-m on the side of the main filter F7 were respectively set at 1 clock pulse period (70 nsec) and 5 clock pulse periods (350 nsec), and k1 and km among the coefficients ko, k1 and km were respectively set at 5 and --1. The magnitude of the coefficient ko was varied stepwise as -3.5, -2.7, -2.4, -2, -1.3, 0, +4 and + 12, and transfer characteristics in the respective cases were actually measured. Then, there were obtained filter characteristics each having a flat part in a lower frequency region not higher than 1 MHz and a peak part near 2 - 3 MHz, as illustrated in Figure 8. The digital filter thus obtained could be satisfactorily utilized as the filter for the aperture correction. Moreover, to be noted here is that the magnitude of the peak could be varied and regulated very smoothly without disturbing the characteristic of any other part, merely by controlling the coefficient ko. This signifies that the main filter F1, not only can have the desired characteristic in the higher frequency region, but also is furnished with the function of permitting the variation of its characteristic through the very simple operation and without disturbing the balance of the characteristic as the whole.

Such function of the smooth variation of the characteristic is a very important function for a filter, and is very difficult even in the ordinary analog filter. In this sense, the digital filter F12 brings forth, not only the negative effect that the characteristic of the analog filter is approximated, but also the positive effect that the still higher degree of property difficult of realization even in the analog filter is provided.

In the case of the present embodiment, in the main filter F1, a characteristic toward a peak appears again in an unused region higher than about 5 MHz. This part, however, can be readily eliminated by the comb characteristic of the sub filter F2. Figure 8 shows the characteristics finally revised by the sub filter F2 According to the present invention described above, the digital filter which exhibits the desired peaking characteristic can be constructed using a very simple circuit arrangement which has only the three adders.

Next, the design method for obtaining the filter arrangement as shown in Figure 7 will be explained.

As shown in Figure 4, the characteristic to be attained now includes a flat characteristic 0 in a lower frequency region and a peaking characteristic (2) at, for example, 2 MHz. A characteristic Q3 in the figure is attained by adding the sub filter F2 as stated before, and hence, note is first taken of the characteristics 0 and (2) in the description.

Using Equation (5) referred to in the background art, the circular type filter H(z) is put as follows: Hfz) = an z-" + am zm + c .......... (6) In order to secure the flatness in the lower frequency region, the following is assumed: d(H,) /z= 1(f = 0) = dz Therefore, d(Hz) = -nanz-n 1-mamz-m-1 = 0 dz - -n a0 z - m am z 1 (7) Substituting z = 1 (f = 0) into Equation (7), - a0 n - am m =O 0 holds.

Accordingly, am m a0 - n holds.

Putting n = 1 for circuit simplification, an = - am m .......... (8) Substituting (8) into (6), c Hz) = - am m z + am z m + c = - am (m z-1 - zm ) am c Here, putting - am = Bx and - c = C, am H(z) = Bx(mz-1 -z-m + C) .......... (9) Here, assuming the gain in the lower frequency region to be 1 (one), namely, Híz)/z = 1 (f = 0) = 1, C = 1 - ( m -1) ..........(10) Bx Substituting Equation (10) into Equation (9).

H(z) = Bx{mz-1 - z-m + (1 - (m - 1 ))} Bx .......... (11) is obtained.

Here, under the condition of B, = 1, m was varied as 2,3,4,5,....., and whether or not the desired peaking characteristic was obtained was studied. As a result, m = 5 was selected.

Therefore, H,i = B,(5z-' (14)} (12) B, is obtained.

Subsequently, B, is varied stepwise as -3.5, -2.7, -2.4-2, -1.3,0, -4 and + 12 under the condition of m = 5, whereupon the variations of the transfer characteristic are actually measured. Simultaneously, in order to reduce the peak of the higher frequency region and to establish the characteristic ( shown in Figure 4, the sub filter (comb filter) F2 is inserted (1 i z-1 is applied).

As a result, the transfer function becomes: H(z) = Box 15 z-' - Z-5 (ft 4)t (1 + z-1) B, (13) When this transfer function is put into a practicable circuit arrangement, the arrangement shown in Figure 7 is obtained.

The arrangement of Figure 7 corresponds to K0 = B - 4, K1 = 5, Kb = Bx and zm = z-5.

When the frequency characteristic of the filter was actually measured, it has been confirmed that the output of the DIA converter shown in Figure 7 exhibits the very excellent peaking characteristic as illustrated in Figure 8.

In this manner, it is the great feature of the present invention that the filter characteristic aimed at is attained by setting the delay times of the respective delay circuits at the special values independent of one another and without resorting to the series-based approximation which requires the enormous circuit scale.

If necessary, the digital output signal Dout of the digital filter F12 endowed with the predetermined characteristic in the above way is restored into the analog signal output Aout by the D;A converter 14. The analog signal output is applied to the control grid of a color CRT (cathode-ray tube) as, for example, the luminance signal of television.

Figure 9 shows an example fo the video signal processing block which has the digital filter F12 built therein.

The video signal processing block 100 shown in the figure takes charge of the major portion of picture signal processing in, for example, a colour television receiver or any other video equipment. This portion is implemented as a semiconductor integrated circuit device, with the digital filter F12, whereby digitization in the colour television receiver or any other video equipment can be widely promoted. Further advantages are that the arrangement of the equipment can be rendered very simple and that the cost can be lowered. In particular, the video signal processing block 100 shown in Figure 9 has been constructed principally for processing the video signal of colour television collectively.A signal separator circuit 102 which separates a colour signal and a luminance signal from the video signal, a comb filter 104 which allows the luminance signal to pass therethrough, the digital filter F12 which is provided for performing the aperture correction, a contrast adjusting multiplier 106, a colour signal filter 108, an automatic colour control circuit 110, a colour killer circuit 112, a PAL discrimination circuit 114, a control bus interface 116 which serves to perform the exchange of data with an external CPU, a colour decoder 118, a multiplier 120 for the degree of colour saturation, a multiplexer 122, a phase-locked loop (PLL) 124 for colour synchronization, and a beam current switching control circuit 126, are formed within the single semiconductor integrated circuit device.The AID converter 12 and D1A converters 140, 160 are connected outside the device, whereby the video signal having been the analog signal is processed as digital data, and the processed result is reconverted into the analog signal, which is usable for the control of the CRT by way of example.

The implementation of the video signal processing block as the semiconductor integrated circuit device as described above can be realized comparatively easily owing to the digital filter F12 according to the foregoing embodiment. Besides, Figure 10 shows an example of application in which the embodiment shown in Figure 7 is given in a more specific form. Here, the output of a digital-to-analog converter drives a CRTthrough a power amplifier. A part G1 enclosed with a dotted line in the figure is a peaking magnitude adjuster, with which the peaking magnitude can be varied. A signal Ao is a composite video signal, and a signal Bo is a luminance signal.

According to the present invention thus far described, the following effects are achieved: (a) A filter is so arranged that a plurality of signals whose magnitudes of delay are unequal to one another are produced by passing a digitized input signal through a plurality of delay circuits and that the plurality of signals are added up and then delivered, and the magnitudes of delay of the plurality of delay circuits are set at non-series-based special values independently of one another. These bring forth the effect that the digital filter having a desired characteristic can be constructed on a comparatively small scale, so the implementation as a semiconductor integrated circuit device can be easily accomplished.

(b) Also, the effect is attained that a filter characteristic aimed at can be easily obtained especially in a high frequency region.

(c) A further effect is that a predetermined filter characteristic is attained, whereupon the function of smoothly varying the characteristic without disturbing the balance as a whole can be easily afforded.

(d) Accordingly, the effect is brought forth that a digital filter usable for the so-called aperture correction which intensifies the higher frequency part of the luminance signal of colour television to emphasize the profile of a picture by way of example can be formed within the semiconductor integrated circuit device.

In a modified form, the delay circuit may be one which employs charge transfer devices such as CCDs.

Whilst, in the above description, the invention has been chiefly discussed as to the case of application to radio frequency filter technology for use in the video signal processing of colour television which forms the background field of utilization, it may also be applicable to digitization technology of various frequency filters in communication systems by way of example. The invention is applicable to filters in which the delay time of at least one delay unit is set independently of the frequency of an input signal, namely, a digital filter or a comb filter.

Claims (3)

1. A signal processing filter including: (a) an input terminal to which an input signal is applied; (b) a first delay circuit whose input is connected to said input terminal and whose output provides a signal delayed by a first delay time (71); (c) an m-th delay circuit whose input is connected to said input terminal and whose output provides a signal delayed by an m-th delay time (Tm); (d) a first coefficient circuit whose input is connected to the output of said first delay circuit; (e) a second coefficient circuit whose input is connected to the output of said m-th delay circuit; and (f) a coupling circuit whose first input is connected to an output of said first coefficient circuit and whose second input is connected to an output of said second coefficient circuit; wherein a value (Tm/T,) obtained by dividing the m-th delay time by the first delay time is a value (m) substantially close to an integer, and wherein another integer (n) exists between the integer 1 and the value (m), and a signal component having an n-th delay time (tun) corresponding to the integer (n) is omitted from application to said coupling circuit.

2. A signal processing circuit according to claim 1, wherein in order to satisfy a predetermined frequency characteristic at an output of said coupling circuit, a coefficient of said first coefficient circuit and a coefficient of said m-th coefficient circuit are set at values unequal to those of a coefficient of a first coefficient circuit and a coefficient of an m-th coefficient circuit of another signal processing filter in correspondence with the omission of the signal component; said other signal processing filter including: (a) a plurality of delay circuits which provide delays of a plurality of delay times (T2 Tom.1) corresponding to successive intergers (2, m - 1) between the interger 1 and the interger m; and (b) a plurality of coefficient circuits whose inputs are connected to respective outputs of said plurality of delay circuits.

3. A signal processing circuit constructed substantially as herein described with reference to and as illustrated in Figures 7 to 10 of the accompanying drawings.