JPS60111283U - Interface circuit for electronic clock testing equipment - Google Patents
Interface circuit for electronic clock testing equipmentInfo
- Publication number
- JPS60111283U JPS60111283U JP20256283U JP20256283U JPS60111283U JP S60111283 U JPS60111283 U JP S60111283U JP 20256283 U JP20256283 U JP 20256283U JP 20256283 U JP20256283 U JP 20256283U JP S60111283 U JPS60111283 U JP S60111283U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- interface circuit
- testing equipment
- electronic clock
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の一実施例を示す装置のブロック図、
第２図は、同上装置の接続状態を示す説明図である。
１・・・・・・変換回路、２・・・・・・第１バツフア
増幅器、３・・・・・・第２のバッファ増幅器、４・・
・・・・切り換え回路、Ｃ１，Ｃ２・・・・・・制御信
号入力端子、Ｄ□、Ｄ２・・開駆動信号入力端子、Ｐ・
・・・・・プローブ接続端子、Ｔ・・・・・・時計信号
出力端子。FIG. 1 is a block diagram of an apparatus showing an embodiment of the present invention;
FIG. 2 is an explanatory diagram showing the connection state of the above device. DESCRIPTION OF SYMBOLS 1... Conversion circuit, 2... First buffer amplifier, 3... Second buffer amplifier, 4...
...Switching circuit, C1, C2...Control signal input terminal, D□, D2...Open drive signal input terminal, P.
...Probe connection terminal, T...Clock signal output terminal.
Claims (1)
Ｆ Ｌ、て時計レベルに変換する変換回路、該回路から
の信号をバッファリングする第１のバッファ増幅器、該
増幅器からの信号を制御信号に基づいてプローブ端子に
出力する切り換え回路、及びプローブ端子からの時計レ
ベル信号をバファリングする第２のバッファ増幅器から
なる電子時計試験装置用インタフェース回路。Turn on clock level voltage by TTL level signal -0F
F L, a conversion circuit that converts the signal to a clock level, a first buffer amplifier that buffers the signal from the circuit, a switching circuit that outputs the signal from the amplifier to the probe terminal based on a control signal, and a signal from the probe terminal. An interface circuit for an electronic timepiece test device comprising a second buffer amplifier that buffers a clock level signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20256283U JPS60111283U (en) | 1983-12-28 | 1983-12-28 | Interface circuit for electronic clock testing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20256283U JPS60111283U (en) | 1983-12-28 | 1983-12-28 | Interface circuit for electronic clock testing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60111283U true JPS60111283U (en) | 1985-07-27 |
Family
ID=30765003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20256283U Pending JPS60111283U (en) | 1983-12-28 | 1983-12-28 | Interface circuit for electronic clock testing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60111283U (en) |
-
1983
- 1983-12-28 JP JP20256283U patent/JPS60111283U/en active Pending
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