JPS60109973A - Synchronizing signal separating circuit - Google Patents

Abstract

PURPOSE:To decrease externally mounted components and to decrease the production cost by obtaining digitally a horizontal/vertical synchronizing pulse from a composite synchronizing signal in a television receiver or the like. CONSTITUTION:A signal VM in synchronizing with the leading of the horizontal synchronizing signal and having a time width within a period of the horizontal synchronizing signal is obtained from the signal included in the composite synchronizing signal VA. This signal VM is compared with a reference voltage Vref so as to obtain a pulse signal Vc corresponding to the cross position with the reference voltage Vref. The horizontal synchronizing pulse VH and the vertical synchronizing pulse VV are separated digitally by using the signal Vc and the composite synchronizing signal VM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a synchronization signal separation circuit suitable for use in television receivers, VTRs, and the like.

[Background technology]

Taking a television receiver as an example, horizontal and vertical synchronization signals are separated, respectively, in order to scan the IS in both the horizontal and vertical directions. For this purpose, a horizontal and vertical synchronizing signal (composite synchronizing signal) is obtained from the color television signal by a synchronizing separation circuit, and this signal is further separated into a horizontal synchronizing signal and a vertical synchronizing signal.

Bypass filters and low pass filters have been used to separate horizontal and vertical synchronization signals from the composite synchronization signal. Each of the filter circuits uses a plurality of capacitors to obtain a predetermined time constant.

However, when a television receiver is constructed from a semiconductor integrated circuit (hereinafter referred to as an IC), the capacitor cannot be formed within the IC and must be an external component. Therefore, when integrated into an IC, the number of external connection terminals increases and the S product decreases. Furthermore, since the number of external parts increases, wiring work and the like are time-consuming, which, combined with the reduction in the degree of integration, increases production costs.

[Purpose of the invention]

An object of the present invention is to provide a synchronization signal separation circuit that eliminates external components such as capacitors and can be manufactured at low cost.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

From the horizontal synchronization signal included in the composite synchronization signal,
A signal that is synchronized with the rising edge and has a time width within the period of the horizontal synchronizing signal is obtained and compared with the reference voltage, a pulse signal corresponding to the cross position with the reference voltage is obtained, and this pulse signal is combined with the above-mentioned composite signal. This achieves the object of the present invention, which is to digitally separate the synchronization signal, the 1,000-cycle pulse, and the vertical synchronization pulse.

[Embodiment 1] Hereinafter, a first embodiment of a synchronization signal separation circuit to which the present invention is applied will be described with reference to FIGS. 1 and 2.

1 is a receiving antenna, 2 is a cheese section, and 3 is a video intermediate frequency circuit. When a desired broadcast radio wave is received, a video signal is sent from the video intermediate frequency circuit 3.

A so-called color television reception 11 including synchronization signals, audio signals, etc. is obtained. The color television signal If is processed by a video signal processing system 4° and an audio signal processing system 5. which are well known to those skilled in the art.
The signal is supplied to the synchronization separation circuit 11.

The video signal processing system 4 detects a video signal (not shown),
This is amplified and supplied to the picture tube 6. The audio signal processing system 5 also detects an audio signal (not shown), amplifies it, and supplies it to the speaker 7.

On the other hand, the synchronization separation circuit 11 receives a composite synchronization signal (2) as shown in FIG. get. Composite synchronization signal ■, 64 μs
Horizontal synchronizing signals H,, Hl, H for each ec.

is formed, and further equivalent pulse Vly Vt e Va
1V4-Vg-Va-Vy, Imk synchronization signal V, is formed. The composite synchronization signal VA is supplied to a monostable multivibrator. A monostable multi-bi break is provided outside the IC via the 1st terminal.
capacitor CI+resistor Rt.

The capacitor CI+resistor R1 determines the monostable multivibrator 120 time constant. At that time, the number of steps τ is determined as T)t:>y for the above-mentioned T=64 μsec. Therefore, the output signal V of the monostable multivibrator 12
W is the 21st! ! ! As shown in l@, the horizontal synchronization signal H, ,
The waveform is synchronized with H,,H, and rises every 64 μsec and falls corresponding to the above-mentioned τ.

Even if the monostable multivibrator 12 is supplied with the next pulse signal during operation, the monostable multivibrator 12 detects this and the operation time does not change. Therefore, if a rising operation is started every 64 μsec, the equivalent pulses L, Vs, Vs, Vs
, J! An output signal VM with a time width τ is obtained regardless of the vertical synchronization signal V.

The output signal ■ is the non-inverting input terminal 10 of the waveform conversion circuit 13 and the first differential amplifier circuit 14, and the second differential amplifier circuit 15.
is supplied to the inverting input terminal of -.

The waveform conversion circuit 13 supplies a reset terminal voltage of the R-87172 flop circuit 16 with a pulse signal (not shown) synchronized with the falling edge of the output signal VM.

The reference voltage ■ r
ef is supplied. Therefore, when Vref<vM, the output voltage VX is obtained from the first differential amplifier 14.

Capacitor C1 and resistor R1 constitute a differential circuit, and Vre
A positive differential pulse (not shown) is obtained every time f < VM K. While this differential pulse has positive polarity, the diode D is in an on state, and the differential pulse is connected to the OR circuit 16.
supply to.

On the other hand, when Vref<VM, an inverted output signal Vy+, that is, a positive output signal VY is obtained from the second differential amplifier circuit 15. The capacitor Car resistor R constitutes a differential circuit, and a positive differential pulse (not shown) is obtained every time Vref>■. Diode D operates similarly to diode D1. As a result of the above circuit operation, the OR circuit 16 supplies the clock terminal C of the D-type 7-lip 70 tube 17 as a continuous block signal as shown in FIG. 2 (Q).

A composite synchronizing signal ■□ is supplied to the D terminal of the D-type 7 lip-flop 17. Here, when comparing FIG. 2 (4) and 0, 1. At the time point, the composite synchronization signal vA and the pulse signal ■. becomes high level. Then, at a delayed time point from time point 11 to the next rising edge of the vertical synchronizing signal VP at 9, the Q output becomes high level as shown in FIG. 13 thereafter
Until one pulse before the time point, the composite synchronization signal (2) and the pulse signal (2) become high level, and the Q output maintains the high level.

At time 11, the composite synchronization signal ■□ is low level and the pulse signal ■. becomes high level. Therefore, t! At this point, the Q output of the D-type 7 lip 70 tube 17 becomes low level. In other words, the vertical synchronizing pulse (7) as shown in FIG.

While the foregoing circuit operations are being carried out, the F-87 lip prop 16 operates as described below.

That is, a high level composite synchronization signal V is applied to the set terminal S.
Since A is supplied, the Q output appears at a high level in synchronization with this. Next, after one hour has elapsed, a pulse signal synchronized with the falling edge of the signal VM is sent to the reset terminal R by the waveform conversion circuit 13.
The Q output becomes D-level in synchronization with this. Therefore, from the Q output of R-8 flip-flop 16,
A horizontal synchronizing pulse VH having a waveform as shown in FIG. 2(g) is obtained.

The above circuit operation is called #! Although the circuit operation is performed in one field (odd field), the following circuit operation is performed in the second field (even field).

The difference between the first field and the second field is the rise position of the vertical synchronization signal VP in the composite synchronization signal VA shown in FIG. 2 (2), and the rise position of the vertical synchronization signal V shown in FIG.
The reason lies in the difference between the rising position and P. Also, although the number of vertical valence pulses in the front part of the vertical synchronization signal VP' is different, the time width T11 in which the horizontal synchronization signal H1'...Ha' appears! are the same.

Therefore, regarding the composite synchronization signal Vj, FIG.
g) for each signal shown in ■M' + V (B', V,'
, Vvl, the same circuit operations as described above are performed.

Therefore, in both the first field and the second field, horizontal synchronizing pulses VH, V□' are obtained from the R-87 flip-flop 16, and vertical synchronizing pulses Vv#V, are obtained from the Dfi flip-flop 17. What should be noted here is that the time difference between the vertical synchronizing signals vP and vP' in the composite synchronizing signal VA1V□' is the vertical synchronizing pulse V,
This also appears in Vv'. Therefore, when vertical scanning of the scanning line is performed, the scanning opening position does not change.

[Example 2] Next, a second example of the present invention will be described with reference to FIGS. 3 and 4.

Note that the synchronization separation circuit 21 shown in this embodiment includes the first
It is assumed that a color television signal generator f is supplied in the same manner as in the embodiment described above, and FIG. 3 shows a synchronizing signal separation circuit, and FIG.

A composite synchronization signal vA having a waveform as shown in the fourth row is obtained from the synchronization separation circuit 21, and the input terminal a of the OR circuit 22 is
Input terminal of Dll flip 70 tube 23, j! is supplied to the waveform conversion circuit 24. 25 is a monostable multivibrator, which receives vertical pulses V'+, V*...V from the composite synchronization signal (■).

is provided to remove. The hourly number τ is determined by the capacitance of the capacitor CHI and the current supplied from the constant current circuit C8I. The output signal VM of the monostable multivibrator 25 shown in FIG.
supplied to The waveform conversion circuit 26 obtains a pulse signal PC as shown in FIG. 4 in synchronization with each falling edge of the output signal VM. The pulse signal PC is supplied to the input terminal of the OR circuit 22 via the switch SI, and also to the set terminal S of the counter 27 and the pulse selection circuit . Therefore, the monostable multivibrator 25 generates two second output signal pulses, and the waveform conversion circuit 26 generates two second output signal pulses.
The second pulse signal P. occurs. The counter 27 performs N counts for the pulse signal PC and supplies the counted value to the pulse selection circuit 28. And in the main example, N=
Upon completion of counting the second pulse signal PC, the counter 27 resets itself and at the same time switches the switch S to the OFF state.

While the above-described operation is being performed, the pulse signal PC continues to be supplied to the pulse selection circuit 28. When the counter 27 completes counting N=2, triggers PT are obtained at intervals as shown in FIG.

The trigger pulse PT is supplied to the clock signal input terminal C of the D-type flip-flop 23.

The input terminal of the D-type flip-flop 23 is supplied with the composite synchronization signal VA. Therefore, the synchronization signal VA
and the trigger pulse PT reach a high level t,
As a result, the Q output of the D-type 7-rig 7o tube 23 becomes high level as shown in FIG. 4 (G).

Then, at the time point 12 when the trigger pulse PT is at a high level and the composite synchronizing signal (2) is at a low level, the Q output becomes a p-level. The Q output (2) shown in Figure (2) of Wc4 is supplied to the next stage DW7 lip 70 tube 290 input terminal.

On the other hand, a pulse signal (not shown) synchronized with the rising edge of the composite synchronization signal VA is obtained from the waveform conversion circuit 24, and is supplied to the clock signal input terminal C of the D-type clip-flop 29. The Qal force of the type flip-flop 70 knob 29 becomes no-repel from the -111 point and becomes low level at the 14-point.
From the Q output of , a vertical synchronizing pulse 7 as shown in FIG. 4 [F] is obtained.

Next, the circuit operation in the second field (even field) will be described. The differences between the composite synchronizing signals VA and v□' are the same as those of the tenth embodiment.

When the composite synchronization signal VA' is supplied as shown in FIG. 40, the synchronization signal separation circuit operates in the same manner as described above. Therefore,
Regarding the composite synchronization signals ■ and ′, each signal K VM′ , PC′ , PT′ l V shown in Figure 4
Signals similar to those described above are obtained as indicated by Q'1 and 7'.

A vertical synchronizing pulse 7' is obtained from the D-type flip-flop 2g.

What should be noted here is that the time difference between the vertical synchronization signals in the composite synchronization signals V, , v^' is the same as the vertical synchronization pulses V, #V,
'This is also reflected in '. Therefore, when vertical scanning of the scanning line is performed, the scanning start position does not change.

〔effect〕

(1) Since the horizontal synchronization signal and vertical synchronization signal included in the composite synchronization signal are digitally separated to obtain the horizontal synchronization pulse and vertical synchronization pulse digitally, the I
When converting to C, it is possible to reduce the number of external connection terminals and external connection parts.

(2) The above (1) provides the effect of reducing production costs.

[Application field]

In the above description, the invention made by the present inventor is mainly applied to a synchronization signal separation circuit of a television receiver, which is the background field of application, but the invention is not limited thereto.

For example, the synchronization signal separation circuit of the present invention can be widely used in video equipment such as VTRs.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the main part of a TV set that shows a fourth embodiment of a synchronization signal separation circuit to which the present invention is applied; Fig. 2 (A) @ (Q (II) @ (( 1()l (
I)) is a waveform diagram showing the circuit operation of Fig. 1, Fig. 3 is a circuit diagram of the main part of a television receiver showing the second embodiment of the present invention, and Fig. wc4 is a waveform diagram showing the circuit operation of Fig. 3. FIG. 3 is a waveform diagram showing circuit operation. 11.21... Synchronous separation circuit, 12.25... Monostable multivibrator, 13, 24.26... Waveform conversion circuit, 16... 8-R flip-flop, 17゜2
3.29...D-type flip-flop, 27...Counter, 28...Pulse selection circuit, v,, vA'...
Composite synchronization signal, VH+V11'...Horizontal synchronization pulse, Vv・■7'g Mi! 2. Continued from page 1 0 Inventor Takayuki Mori 147CA, Josui Honmachi, Kodaira City
Geneering Co., Ltd. 10 Inventor Izumi Arai 147g1, Josui Honmachi, Kodaira City
Genearing Co., Ltd. 10 Inventor Makoto Furi 11111 Nishiyokote-cho, Takasaki City
1 location within Hitachi Microcomputer Systems 1 location within Hitachi Microcomputer Systems 1 location within Hitachi, Ltd. Takasaki Factory

Claims (1)

[Claims] 1. A monostable multivibrator for obtaining an output signal that changes at rising and falling points within the cycle of a horizontal synchronizing signal included in a composite synchronizing signal, and comparing the output signal with a reference voltage. a pulse signal generating means for obtaining a pulse signal of a predetermined period, a D1n71J pf quad for detecting synchronization between the composite synchronization signal and the pulse signal and obtaining a vertical synchronization pulse included in the composite synchronization signal, and the composite synchronization The force of the monostable multivibrator is set based on the signal! an R-S flip-flop circuit that obtains a horizontal synchronization pulse from the composite synchronization signal by resetting based on the signal, and digitally obtains a horizontal synchronization pulse and an electrodynamic synchronization pulse from the composite synchronization signal. A synchronous signal processing circuit characterized by: 2. A monostable multivibrator that obtains an output signal that changes rising and falling multiple times within one period of a horizontal synchronization signal included in a composite synchronization signal, and a waveform that synchronizes with the waveform changes of the output signal and obtains a companion pulse signal. a conversion circuit, a counter circuit that counts N pulse signals, and a pulse selection circuit that obtains a selection pulse every N by detecting synchronization between the counting output of the counter circuit and the pulse signal;
Comparison of the selection pulse with the vertical synchronization signal included in the composite synchronization signal (thereby comprising a D-type flip 70 tube for obtaining a vertical synchronization pulse with a time width corresponding to the vertical synchronization signal period, A synchronization signal separation circuit characterized in that a vertical synchronization pulse is obtained from.