JPS6010912A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6010912A
JPS6010912A JP58120806A JP12080683A JPS6010912A JP S6010912 A JPS6010912 A JP S6010912A JP 58120806 A JP58120806 A JP 58120806A JP 12080683 A JP12080683 A JP 12080683A JP S6010912 A JPS6010912 A JP S6010912A
Authority
JP
Japan
Prior art keywords
data
feedback loop
held
input
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58120806A
Other languages
Japanese (ja)
Inventor
Hiroshi Miyajima
宮島　博
Kingo Wakimoto
脇本　欣吾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58120806A priority Critical patent/JPS6010912A/en
Publication of JPS6010912A publication Critical patent/JPS6010912A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356069—Bistable circuits using additional transistors in the feedback circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates

Abstract

PURPOSE:To obtain a data holding circuit where data is not held because of the disconnection of a feedback loop by providing a double feedback loop. CONSTITUTION:A data is inputted to an inverter train 1 by opening a transfer gate 5 for data input to the data holding circuit in the state that a transfer gate 3 for holding data is closed. The held data of an output section 7 is fed back to an input section 6 via a feedback loop 2 by opening the gate 3 at the same time when the gate 5 is closed to keep stably a parasitic capacitor 4 to a state decided by the held data. Since the held data is fed back via a diffusion resistor 9 when the input part of the gate 3 and the feedback loop 2 are disconnected at the data holding the charge in the parasitic capacitor 4 is not discharged and the data is kept held. When the diffusion resistor 9 is disconnected, the data is held via the feedback loop 2.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はデータ保持回路の帰還ループの切断によって
も、データが保持できるようにした半導体集積回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit that can retain data even when a feedback loop of a data retention circuit is disconnected.

〔従来技術〕[Prior art]

第１図は従来の半導体集積回路を示す回路図でアシ、−
例としてダイナミック型データ保持回路を示す論理図で
ある。同図において、（１）はデータ保持のためのイン
バータ列、（２）は保持データであるインバータ列（１
）の出力端子からこのインバータ列（１）の入力端子へ
の帰還ループ、（３）はデータ保持時のみデータを帰還
させるために開閉するデータ保持用トランスフアゲ−）
、（４）はデータ保持に必要な寄生容量、（５）はデー
タ入力用トランスファゲート、（６）は入力部、（１）
は出力部、（８）は電源Ｖ［ｉ１＋である。Figure 1 is a circuit diagram showing a conventional semiconductor integrated circuit.
FIG. 2 is a logic diagram showing a dynamic data holding circuit as an example. In the figure, (1) is an inverter row for data retention, and (2) is an inverter row (1
) to the input terminal of this inverter array (1), and (3) is a data retention transfer gate that opens and closes to feed back data only when data is retained.
, (4) is the parasitic capacitance necessary for data retention, (5) is the transfer gate for data input, (6) is the input section, (1)
is an output section, and (8) is a power supply V[i1+.

次に、上記構成による半導体集積回路の動作について説
明する。まず、データ保持用トランスフアゲ−）（３）
ｅ閉じた状態において、データ保持回路へのデータ入力
用トランスファゲート（５）を開くことによって、デー
タがインバータ列（１）に入力される。次に、このデー
タ入力用トランスファゲート（５）　ｔ−閉じると同時
にデータ保持用トランスファゲートを開くことによって
、出力部（７）の保持データが帰還ループ（刀を介して
入力部（６）　ｔ＜帰還され、寄生容量（４）を保持デ
ータによって決まる状態に安定に保ち続ける。このよう
に、データの保持が行なわれるため、通常ダイナミック
型データ保持回路と定義される。Next, the operation of the semiconductor integrated circuit having the above configuration will be explained. First, data retention transfer game) (3)
e In the closed state, data is input to the inverter array (1) by opening the transfer gate (5) for inputting data to the data holding circuit. Next, by closing the data input transfer gate (5) and simultaneously opening the data retention transfer gate, the data held in the output section (7) is transferred to the input section (6) via the feedback loop (t< It is fed back and continues to stably keep the parasitic capacitance (4) in a state determined by the held data.Because data is held in this way, it is usually defined as a dynamic data holding circuit.

しかしながら、従来の半導体集積回路では保持データが
′Ｈルベルのとき、もし帰還ループやデータ保持用トラ
ンスファゲート（３）のゲート入力が製造時、あるいは
実使用時に切断されると、寄生容量（４）に充電されて
いる電荷が保持できず、データを保持できなくなる欠点
があった。However, in conventional semiconductor integrated circuits, when the held data is 'H level, if the feedback loop or the gate input of the data holding transfer gate (3) is disconnected during manufacturing or during actual use, the parasitic capacitance (4) It had the disadvantage that it could not retain the electric charge stored in it, making it unable to retain data.

〔発明の概要〕[Summary of the invention]

したがって、この発明の目的はデータ保持回路の帰還ル
ープなどが切断されたときにも、確実にデータを保持す
ることができる半導体集積回路を提供するものである。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can reliably hold data even when the feedback loop of a data holding circuit is disconnected.

このような目的を達成するため、この発明は直列に接続
された、インバータ、アンドゲート、オアゲートなどの
論理素子列と、一端がこの論理素子列の初段の素子の入
力に接続され、他端が前記論理素子列の出力に接続され
たデータ保持用トランスファゲートおよび抵抗成分を有
する素子と、前記論理素子列の初段の素子の入力に一端
が接続されたデータ入力用トランスファゲートとから構
成されたデータ保持回路を備えるものであり、以下実施
例を用いて詳細に説明する。To achieve such an object, the present invention has a series of logic elements such as inverters, AND gates, and OR gates connected in series, one end of which is connected to the input of the first stage element of the logic element series, and the other end of which is connected to the input of the first stage element of the logic element series. Data comprising a data holding transfer gate connected to the output of the logic element array, an element having a resistance component, and a data input transfer gate having one end connected to the input of the first stage element of the logic element array. It is equipped with a holding circuit, and will be described in detail below using examples.

〔発明の実施例〕[Embodiments of the invention]

第２図はこの発明に係る半導体集積回路の一実施例を示
す回路図である。同図において、（９）は前記データ保
持用トランスファゲート（３）による帰還ループ（２）
と並列に接続された拡散抵抗であシ、保持データのゞＨ
ルベルを保てるだけの十分な太きさの抵抗値を持つこと
が必要である。FIG. 2 is a circuit diagram showing an embodiment of the semiconductor integrated circuit according to the present invention. In the figure, (9) is a feedback loop (2) formed by the data holding transfer gate (3).
It is a diffusion resistor connected in parallel with ゞH of the retained data.
It is necessary to have a resistance value large enough to maintain the level.

次に、上記構成による半導体集積回路の動作について説
明する。まず、データ保持用トランスファゲート（３）
を閉じた状態において、データ保持回路へのデータ入力
用トランスファゲート（５）を開くことによって、デー
タがインバータ列（１）に入力される。次に、このデー
タ入力用トランスファゲート（５）を閉じると同時にデ
ータ保持用トラ〜へファ　１ゲート（３）を開くことに
よって、出力部（１）の保持データが帰還ループ（２）
を介して入力部（６）に帰還され、寄生容量（４）を保
持データによって決まる状態に安定に保ち続けることが
できる。次に、データ保持時に、帰還ループ（２）やト
ランスファゲート（３）のゲート入力部が切断されてい
る場合、保持データは拡散抵抗（９）を介して帰還され
るため、寄生容量（４）に充電されている電荷が放電さ
れることなく、状態を安定に保ち、データを保持し続け
ることができる。また、拡散抵抗（９）が切断された場
合には帰還ループ（２）ヲ介してデータ保持が行なわれ
ることは上述した通シであることはもちろんである。Next, the operation of the semiconductor integrated circuit having the above configuration will be explained. First, data retention transfer gate (3)
In the closed state, data is input to the inverter array (1) by opening the transfer gate (5) for inputting data to the data holding circuit. Next, by closing the data input transfer gate (5) and simultaneously opening the data retention transfer gate (3), the data retained in the output section (1) is transferred to the feedback loop (2).
The parasitic capacitance (4) can be stably maintained in a state determined by the held data. Next, when the feedback loop (2) or the gate input part of the transfer gate (3) is disconnected during data retention, the retained data is fed back via the diffused resistor (9), so the parasitic capacitance (4) It is possible to maintain a stable state and continue to retain data without discharging the electric charge stored in the device. Furthermore, it is of course the same as described above that when the diffused resistor (9) is disconnected, data is retained via the feedback loop (2).

なお、上述の実施例では拡散抵抗を設けた場合を示した
が、これに限定せず、ポリシリコン抵抗。In addition, although the above-mentioned example showed the case where a diffused resistor was provided, it is not limited to this, and a polysilicon resistor may be used.

デプレッション型トランジスタなどを使用してもよいこ
とはもちろんである。また、論理素子列としてインバー
タを用いたが、これに限定せず、アンドゲート、オアゲ
ートなどを用いてもよいことはもちろんである。Of course, a depression type transistor or the like may also be used. Furthermore, although inverters are used as the logic element arrays, the present invention is not limited to this, and it goes without saying that AND gates, OR gates, etc. may also be used.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、この発明に係る半導体集積
回路によれば二重の帰還ループを備えているので、帰還
ループの切断によってデータが保持できないような半導
体集積回路の発生を防止することができる効果がある。As explained in detail above, since the semiconductor integrated circuit according to the present invention has a double feedback loop, it is possible to prevent the semiconductor integrated circuit from being unable to retain data due to disconnection of the feedback loop. There is an effect that can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体集積回路を示す回路図、第２図は
この発明に係る半導体集積回路の一実施例を示す回路図
である。 （１）・・・・インバータ列、（２）・・・・帰還ルー
プ、（３）・・・・データ保持用トランスファゲート、
（４）・・会・寄生容量％　（５）・・・・データ入力
用トランスフアゲ−）、（６）・・・・入力部、（７）
・拳・・出力部、（８）・・・・電源Ｖｌ！８　、　（
９）・・・・拡散抵抗。 なお、図中、同一符号は同一または相当部分を示す。 代理人　大岩増雄FIG. 1 is a circuit diagram showing a conventional semiconductor integrated circuit, and FIG. 2 is a circuit diagram showing an embodiment of the semiconductor integrated circuit according to the present invention. (1)...Inverter array, (2)...Feedback loop, (3)...Data retention transfer gate,
(4)... Parasitic capacitance % (5)... Data input transfer gate), (6)... Input section, (7)
・Fist: Output section, (8): Power supply Vl! 8, (
9) Diffusion resistance. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

【特許請求の範囲】 直列に接続された、インバータ、アンドゲート。 オアゲートなどの論理素子列と、一端がこの論理素子列
の初段の素子の入力に接続され、他端が前記論理素子列
の出方に接続されたデータ保持用トランスファゲートお
よび抵抗成分を有する素子と、前記論理素子列の初段の
素子の入力に一端が接続されたデータ入力用トランスフ
ァゲートとから構成されたデータ保持回路を備えたこと
を特徴とする半導体集積回路。[Claims] An inverter and an AND gate connected in series. A logic element array such as an OR gate, a data holding transfer gate whose one end is connected to the input of the first-stage element of the logic element array, and the other end connected to the output side of the logic element array, and an element having a resistance component. , and a data input transfer gate whose one end is connected to the input of the first-stage element of the logic element array.
JP58120806A 1983-06-30 1983-06-30 Semiconductor integrated circuit Pending JPS6010912A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58120806A JPS6010912A (en) 1983-06-30 1983-06-30 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58120806A JPS6010912A (en) 1983-06-30 1983-06-30 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6010912A true JPS6010912A (en) 1985-01-21

Family

ID=14795436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58120806A Pending JPS6010912A (en) 1983-06-30 1983-06-30 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6010912A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015088198A (en) * 2013-10-29 2015-05-07 セイコーエプソン株式会社 Storage circuit, electro-optic device, semiconductor storage device, and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015088198A (en) * 2013-10-29 2015-05-07 セイコーエプソン株式会社 Storage circuit, electro-optic device, semiconductor storage device, and electronic apparatus

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