JPS6010828A - Intricate method in transmission of pulse information - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency by 100% by writing immediately at a part just after read. CONSTITUTION:A wirte half block counter 2a and a read half block counter 7a are provided and a latter half n/2 word is written in a block just after the first haft n/2 word read. Further, the required capacity of an intricate memory 1 is halved by writing the 1st half n/2 word to a block just after the read of the latter half n/2 word.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to interlacing methods in, for example, PCB4 communication, PCM recording, or other pulse information transmission.

<Prior art> For example, at present, analog signals such as music are converted into PCM and recorded on magnetic tapes, record boards, CDs (compact discs), etc. and sold. By converting the signal back to an analog signal and playing it back, erroneous signals caused by noise during recording and playback can be corrected by using an error correction code, which can be effectively prevented, resulting in better information transmission. It is well known that this can be done. Such a PCM pulse signal is further recorded by changing the pulse arrangement over time,
On the other hand, the user can return the pulse signal whose arrangement has changed to its original chronological arrangement and return it to a PCM signal.In addition, it is possible to disperse the burst error in response to the occurrence of burst errors during transmission. is possible and effective.

This method is called the interleaving method, changing the temporal arrangement of the pulse signals on the transmitting side is called interleaving, and returning the pulse signals to the original temporal arrangement on the receiving side is called dinterleaving. It is called. In other words, the interleaving method (interleave, dinterleave) is a method that uses a common error correction block when the check words and encoded information contained in a common error correction block are distributed and transmitted, and returned to the original arrangement on the receiving side. This attempts to reduce the number of error words among multiple words included in a block. The degree to which the arrangement changes over time is referred to as an interleave distance d, and the larger the interleave distance d, the better.

Such interleaving is performed by first writing a series of time-varying signals to a memory such as a RAM, and then reading the written memory in a different order or randomly. This is done by writing the data into a memory such as a RAM and reading it out in an order that restores the original signal over time.

FIG. 1 shows the configuration of an interleaving circuit according to the first conventional method. Note that the error correction circuit is not directly related to the present invention and will therefore be omitted.

FIG. 4 shows an interleaving operation according to this first conventional method. In the interleaving memory 1 shown in Figures 1 and 4, the vertical direction indicates the number of blocks, and the horizontal direction indicates the number of words. Let the interleaving distance be d blocks. Also, the number of blocks is (n
-1)Xd+1 or (n-1)Xd+1+t.

Next, the operation of this device will be explained.

Write block pulse a and write word \Ik, 1
The write block counter 2 and the write n-word color register 3 are operated by the pulse b, the write address correction circuit 4 specifies the write position in the memory 1, and the write read selection signal C causes the address selection circuit 5 to specify the write position. , memory 1 has a recording system 6 for PCM signals, etc.
The n words of encoded information are sequentially written into the memory 1 along the horizontal line 2 in FIG.

On the other hand, the read block pulse d and the read word pulse e operate the read block counter 7 and the read n word counter 8, respectively, and the read address correction circuit 9 specifies the read position of the memory 1, and the read address correction circuit 9 and the read position of the memory 1 are specified. The selection circuit 5 is designated for reading, and the data written in the memory 1 is interleaved and sequentially read out along the diagonal line (■) in FIG. 4.The read data is recorded on a medium 10 such as a tape or record board. be done.

In the above operation, the write speed and read speed of the interlacing memory need to match on average below the interlacing memory capacity, but the average write speed and read speed in block units do not need to match. . However, a control circuit is required to access the same intersecting memory. The block diagram of FIG. 1 shows a case where the average write speed and read speed are different for each block, and the write block pulse a and the read block pulse d are counted by different counters.

The real address of the interlacing memory outputted from the write address correction circuit 4 and the real address of the interlaced memory outputted from the read address correction circuit 9 are selected by the address selection circuit 5 in response to the write/read selection signal, and at one point in time. , which only one real address is added to the address input of the intersection memory.

When the above writing and reading processing for one block is completed, the same processing is performed for the next block (the block one step below). Furthermore, when the processing at the bottom of the memory is completed, the next processing is at the top, and the process cycles through the memory 1 in J@.

Next, dinterleaving according to the first conventional method will be explained. Dinterleave has exactly the same configuration as interleave, except that the reading direction is different. The circuit configuration of this dinterleave is the same as that shown in FIG. 1, and the recording system 6 serves as the medium 10 instead of the PCM signal recording system, and the PCM signal reproducing system 11 instead of the medium 10. They differ in some respects (see parentheses). FIG. 5 shows a dinterleave operation according to this first conventional method.

In FIG. 5, the horizontal line ■ indicates the write direction in which the received words received from the medium 10 are sequentially written into the memory, and the diagonal line ■ indicates the memory read direction in which interleaving is solved and the same arrangement as the information at the time of recording is created. . This read data is reproduced as, for example, a PCM signal.

In the above device, if the average write speed and read speed in block units match, one of the block counters 2 and 7 can be omitted. In this case, the memory capacity is n words in the horizontal direction and (n-1) x d+1 blocks in the vertical direction for each of the interleave and dinterleave circuits. In addition, in the dinterleave, it is necessary to provide a margin of t blocks in the vertical direction as a jitter margin.

As a second conventional method, interleaving and dinterleaving memory operations can be performed in the same interleaving memory.

The same parts as in FIG. 1 are denoted by the same reference numerals, and in this device shown in FIG. 3, the same word pulse h as the recording system write/reproduction system read block pulse g is used for the reproduction system read and the recording system write block counter I2, respectively. These output signals are input to the reproduction yarn reading/recording system write n-word counter 13, respectively, to the reproduction system reading/recording system write address correction circuit 14, and the output signals are input to the address selection circuit 5, which also includes the recording/recording system. The reproduction selection signal 1 is input. In this case, when the recording system or the reproducing system operates independently, the operation and configuration are completely unchanged from those according to the first conventional method. When the recording and reproducing systems are operated simultaneously, normal operation will only occur if the clocks of the recording and reproducing systems are synchronized. Therefore, when the recording system and the reproducing system operate simultaneously, reading from the recording system can be omitted. If we consider that the data read in the reproduction system read is written again on the same line in the recording system, the recording system write operation actually does nothing. Similarly to the first method, if the average write speed and average read speed in block units match,
It is also possible to combine the block counters 2 and 7 into one.

FIG. 6 is an explanatory diagram showing the interleave operation and dinterleave operation according to the second conventional method.
correspond to ■ and ■ in FIG. 4 and ■ and ■ in FIG. 5, respectively. That is, in interleaving, data is written along the diagonal line (■) and read out along the horizontal line (2), while in deinterleaving, data is written along the horizontal line (2) and read out along the diagonal line (2).

This allows interleaving and dinterleaving to be performed simultaneously on the same memory.

As is clear from the above explanation, in Fig. 4, the triangular part ■ surrounded by the horizontal line ■ and the diagonal line ■ is the memory in which valid data is written at that time, and the memory usage efficiency is It is.

In FIG. 5, a portion O surrounded by a horizontal line ``■'' and a diagonal line ``■'' is the memory in which valid data is written at that time, and the memory usage efficiency is below the current level.

In the second conventional method, the entire memory can be effectively used except for t blocks of memory provided as a jitter margin. However, this method requires that the clocks of the recording and reproducing systems be synchronized, making it impossible to operate the recording and reproducing functions of the device independently. Furthermore, in a recording-only machine or a playback-only machine, the memory usage efficiency is still lower than the power supply. That is, in the first conventional method, the memory used at a certain time is approximately 14 of the total memory.

The present invention was developed in view of the above circumstances, and it is an object of the present invention to reduce the memory capacity by increasing the efficiency of memory use to approximately 100 cm even in the case of interleaving and dinterleaving.

<Purpose> That is, the present invention focuses on the fact that in the above-mentioned interleaving and dinterleaving, it is necessary to store only the range from writing to reading in the memory, and there is no need to store it after reading. The usage efficiency is 100% by immediately writing to the part immediately after the data.

<Configuration> That is, the present invention includes a write half block counter and a read half block counter in the conventional device described above, writes the second half word to the block immediately after reading the first half word, and writes the second half word to the block immediately after the second half word is read. The first half of the boundary word is written to reduce the required capacity of the crossover memory by half. In addition, here 1
first half.

The "second half" is added for convenience, and since these writing and reading operations are repeated alternately, the same effect can be obtained even if the front and rear are reversed.

<Example> Explain the details.

FIG. 7 shows an interleave circuit according to the present invention, and the interleave and dinterleave circuits have the same configuration except for some differences in the writing direction and the reading direction, and the differences are as described above. Note that if the average write speed and average read speed in units of blocks are equal, either the write block counter or the read block counter can be omitted as in the conventional method shown in the second diagram.

As shown in Figure 7, the write word pulse b is the write%
The word counter 3a is input to the 7 block counter 2a, and the read word pulse e is input to the read % word counter 8a and the read half block counter 7a, respectively.

In this device, when the write % word counter 3a writes % words into the upper bits of the memory, the write direction is changed for each % word based on the output of the write half block counter 2a.

Next, the write address correction circuit 4 calculates and corrects the writing direction on the memory 1 by using it as a real address. Regarding reading, in exactly the same way, the reading half block counter 7a changes direction every % word.

The omitted real address and the read real address output from the address correction circuit 5 in this way are selected by the address selection circuit 5 by the write/read selection signal C.
It is added to the address input of the intersection memory 1.

Furthermore, the interleave and dinterleave operations of the present invention will be explained using memory maps of the interleaving memory in FIGS. 8 and 9, respectively. The solid line portion in the figure shows the interleaving and dinterleaving memory operations of the present invention, and the broken line represents the conventional method shown for comparison with the first conventional method.

In FIG. 8, ■' indicates the writing direction of the first conventional method in which n words of information encoded in the recording system are sequentially written into the memory. In order to solve this problem, in the present invention, the writing direction is changed according to the word as shown in (1) and (alpha).

Similarly to FIGS. 8 and 8, the memory read direction according to the first conventional method is shown, and 2 and 2' show the memory read direction according to the present invention. At this time, interleaving will be applied. Figures 1 and 2 show the writing direction according to the first conventional method in the reproduction system in which the received words received from the transmission system are sequentially written into the memory. On the other hand, in the present invention, the write direction is changed at the v6 word indicated by O).

Similarly, FIGS. 9 and 9 show the memory read direction according to the first conventional method, and 2 and 2' show the memory read direction according to the present invention. At this time, dinterleaves are applied.

In other words, the address of the word corresponding to the first half block of writing and reading of the interleaving memory is used as a relative address, and in the interleaving, from the end point position of the write address of the second half block (Fig. 8P) to the second half block of the second half block. Points that exceed the maximum distance apart during readout (Fig. 8Q)
) is the starting point, and the writing direction (■) of the first half is performed in the opposite direction to the reading direction (■') of the second half block, and the reading direction (2) of the first half is performed in the opposite direction to the writing direction (■') of the second half block. In dinterleave, the address of the word corresponding to the second half block of reading is set beyond the maximum distance from the starting point of the first half block (p/ in Figure 9) when writing the first half block, and in addition, the jitter margin is set. The end point is the point where the sum of Do it in the opposite direction.

Next, assuming that the configuration shown in Fig. 7 is a reproduction system dinterleave circuit (see parentheses), it corresponds to Fig. 9). including. This pulse is synchronized with the beginning or end of the write operations (2) and (2) and is used to advance the written block one step forward.The output of the write block counter 2 is, for example, It indicates the position of

The write word pulse b is a signal containing n pulses between write operations (1) and (2) for a code of n words in one block, and is a pulse synchronized with the word interval of the received signal. The output of the write next word counter 3a is shown in Fig. 9 ■, ■
′ indicates the horizontal position.

The write half block counter 2a is a binary output 1 which further counts the output of the write one word counter 3a.
This counter indicates whether the currently received word is in the first half % word (■ in FIG. 9) or the second half % word (■' in FIG. 9) of one block.

From the outputs of these counters, the write address correction circuit 4 sequentially outputs the positions ① and ②' in FIG. 9 as real addresses on the crossing memory 1.

The read block pulse d and the read word pulse e are output from a signal processing circuit connected to the subsequent stage of this circuit.
It is something that

The output of the read block counter 7 indicates, for example, the starting position of the line marked with a black square in the vertical direction in FIG. The output of the still read % word counter is shown in Figure 9■,■
′ indicates the horizontal position.

The output of the read half block counter 7a is a binary counter that further counts the output of the read % word counter 8a, and determines whether the current output word is in the first half % words (■ in FIG. 9) of one block. This indicates whether the word is in the second half % word (■' in FIG. 9).

The read address correction circuit 9 sequentially outputs the positions ① and ②' in FIG. 9 from each output of the read counter as real addresses on the intersection memory.

The address selection circuit 5 outputs the output of the write address correction circuit 4 during writing, and outputs the memory real address for read access during reading.

The case of the recording system interleave circuit can be similarly explained with reference to FIGS. 7 and 8.

In the present invention, the memory read/write lines are treated as linear lines on the memory map, but the present invention is also effective even if the lines are polygonal lines.

<Effects> As described above, by applying the memory address operation of the present invention, the width of the conventional intersecting memory in the horizontal direction is n words, whereas in the present invention, the write word counter is the current word counter, so that width is reduced. The width is in % words. If the average write speed and read speed in block units are equal, and only one block counter is required for each recording system and playback system, then in the recording system, horizontal % words (if n is an odd number, (n +
1 month word), memory capacity of vertical (n-1')
The same effect as the conventional interlacing method can be obtained with the memory capacity of the block (t is the jitter margin). Therefore, the memory capacity can be reduced to approximately half. Furthermore, in the present invention, since the recording system and the reproducing system are independent, memory usage efficiency can be improved even in a recording-only machine or a reproduction-only machine.

In the circuit block diagram of the present invention shown in FIG. 7, since the % word counter and half block counter have the same number of focus points as the conventional n word counter, the increase in the number of parts according to the present invention is due to the correction in the address correction circuit. This is only due to differences in methods.

Furthermore, the data arrangement after interleaving and gain interleaving obtained by the circuit of the present invention is completely compatible with that obtained by the conventional method. Or, conversely, it is also possible to deinterleave a data array interleaved using the circuit of the present invention using conventional methods.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interleaving circuit according to the first conventional method, FIG. 2 is a block diagram of another example of an interleaving circuit according to the first conventional method, and FIG. 3 is a block diagram of an interleaving circuit according to the conventional first method.
4 is a block diagram of an interleave/dinterleave circuit according to the conventional method, FIG. 4 is an explanatory diagram of a memory map showing interleave memory operation according to the first conventional method, and FIG. 5 is a block diagram of a dinterleave memory operation according to the conventional first method. FIG. 6 is an explanatory diagram of a memory map showing interleave/dinterleave memory operation according to the second conventional method. FIG. 7 is a block diagram of a memory operation circuit according to an embodiment of the present invention. FIG. 8 is an explanatory diagram of a memory map showing interleaved memory operations according to the present invention, and FIG. 9 is an explanatory diagram of a memory map showing interleaved memory operations according to the present invention. 1......Memory for crossing, 2,7...
...Block counter, 3a...Write word counter, 4...Write address correction circuit, 8a...Read word Counter, 9... Read address correction circuit, 5... Address selection circuit, 2
a......Book! Including half block counter, 7a... Read half block counter, ■... Read first half word, ■
′・・・・・・Last % word writing,■′・・・・
・・・・・・Last % word reading,■・・・・・・
...first half % word writing. Tough (-IF)2-

Claims (1)

[Claims] a memory for crossover, a block counter that counts the number of blocks of correction codes, a write word counter that counts the number of words written into the memory, and a write address that outputs the actual write address of the memory from the count values of the block counter and the write word counter. a correction circuit, a read word counter that counts the number of memory read words, a read address correction circuit that outputs a real read address of the memory from the count values of the block counter and the read word counter, and the write address correction circuit and read address correction. In a circuit having an address selection circuit for selectively outputting the output of the circuit according to write/read operations and inputting it to the address input of the intersecting memory, a write no block counter and a read no block counter are used. The second half % word is written in the block immediately after the first half word is read, and the first half % word is written in the block immediately after the second half % word is read, thereby reducing the required capacity of the intersecting memory by half. Features of interlacing method in pulse information transmission.