JP3080452B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device,
In particular, the present invention relates to an apparatus for receiving a digital signal during reproduction of a compact disk and performing address control when writing the digital signal to a memory and reading the digital signal from the memory.

[0002]

2. Description of the Related Art FIG. 11 shows a memory address map of a conventional signal processing device. This memory address map is 32
The kSRAM is used, and is used when error correction and deinterleaving of a digital signal read from a compact disc (not shown) are performed.
At that time, data rearrangement for performing error correction during reproduction is performed in accordance with the standard. The rearrangement of the data performed at this time needs to be performed by a method reverse to that at the time of recording.

More specifically, in a digital signal read from a compact disc, data of 32 symbols per frame (1 symbol = 8 bits) is delayed by one frame every other symbol according to the standard.
1 is written as indicated by the direction A and the line B of the memory map.

[0004] Next, C1 correction data of 32 symbols per frame is read from the memory according to the standard as shown by a direction C and a line D in FIG. As for the data after the C1 correction, only the data corrected in the operation is written to the same address. At this time, the flag of the C1 correction pointer (C1P) rises for data of the number of symbols for which error correction has not been completely performed.

Next, C2 correction data of 28 symbols per frame excluding 4 symbols of C1 correction parity is
Referring to the C1 correction pointer (C1P), the first symbol is 108-frame delayed data, the second symbol is 104-frame delayed data, and so on from the memory as shown in the direction E and line F in FIG. Is read. In this C2 correction, a flag of the C2 correction pointer (C2P) rises for data of the number of symbols for which error correction has not been completely performed. Then, this data is processed so that the interpolation processing is performed later to mute the data so that noise is not generated.

[0006]

The conventional signal processing apparatus is configured as described above. When reading C2 correction data according to the standard, data without delay is required for the 28th symbol. In the first symbol, all the data from the one-frame delay data to the 108-frame delay data are required. Therefore, in the 28th symbol of the C2 correction data, the 108th frame delay data from the 1st frame delay data, which is unnecessary data after use, is stored in the map similarly to the 1st symbol. The same applies to other symbols, and is unnecessary data after use at the time of reading the C2 correction data of the n-th symbol [# 108-4.
Since the (n-1)} +1] frame delay 108 frame delayed data from the data is a long time stored in the area G in FIG. 11, a problem that fold areas are required for actual use area H in FIG. 11 there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and does not store unnecessary data after using C2 correction data for a long time, and can effectively use a memory. It is intended to obtain a processing device.

[0008]

According to the signal processing apparatus of the present invention, the storage area of the storage circuit includes a first area for storing the digital signal read from the recording medium and the first error correction data. A second storage area for storing the second error correction data corrected by the first correction circuit, and a second storage area for storing the data corrected by the second correction circuit. And a first address control means for controlling the digital signal read from the recording medium and the first correction data and writing the first correction data into the first storage area. The second error correction data, which has been corrected by the first correction circuit, is sequentially allocated to each of the plurality of unit areas in the second storage area for each frame and written. Second mistake The correction data, reading the writing order, second to control so as to enter into the second correction circuit
Address control means.

[0009]

According to the present invention, a first area for storing a digital signal and first error correction data read from a recording medium and a second error correction data corrected by a first correction circuit are provided. A second area for writing data and a third area for writing data corrected by the second correction circuit are provided independently, and a second error after correction by the first correction circuit is provided. The correction data is sequentially distributed and written into a plurality of unit areas in the second area for each frame , and the written data is written.
The second error correction data is read out in the order of writing, and
By controlling the correction data to be input to the second correction circuit, unnecessary data after the error correction processing is sequentially deleted, and effective use of the memory can be achieved.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a signal processing apparatus according to an embodiment of the present invention. FIG. 1 is a block diagram showing a signal processing apparatus according to an embodiment of the present invention.
Is a memory address map for explaining the operation. In FIG. 1, reference numeral 1 denotes an input terminal, 2 denotes an SRAM serving as a storage device, 3 denotes a C1 correction circuit (first error correction circuit), 4 denotes a C2 correction circuit (second error correction circuit). The digital signal input to the terminal 1 is controlled by an address control circuit 5, and the data read from the memory 2 is controlled by an address control circuit 6. Reference numeral 7 denotes a control circuit which controls the writing of the data after the C1 correction into the memory 2 and the control when reading the data as the C2 correction data from the memory 2. Reference numerals 8 and 9 denote the C1 and C2 after the C1 and C2 correction, respectively. An address control circuit that performs address control when writing a pointer to the memory 2. Further, reference numeral 10 denotes an address control circuit for controlling an address at the time of writing data after C2 correction as data before D / A conversion into the memory 2, and 11 outputs data before D / A conversion from the memory 2 to an output terminal 12. This is an address control circuit that performs control when the operation is performed.

The memory address map shown in FIG. 2 is different from the conventional memory address map shown in FIG. 11 in that an area 2A for writing a digital signal read from a compact disk and an area for reading as C1 correction data are provided. 2B is configured independently.

Also, the area for each frame when writing the data after the C1 correction and the time for reading as the C2 correction data are different, and the area provided for each symbol in the frame is different. That is, reference numeral 2A denotes an area (first area) for writing data (EFM data) read from the compact disc and reading data for C1 correction, and this area has a jitter absorption area for absorbing jitter at the time of reading. An area (± 4 frames) is also provided. 2B is an area for storing data to be C2 correction data after C1 correction, and this area is further divided into four planes 4a, (4a + 1), (4a + 2),
(4a + 3). 2C and 2D are areas for storing C1 and C2 correction pointers at the time of C1 correction and C2 correction, respectively, and 2E is an area for storing D / A data after C2 correction. FIG. 3 shows the region 2A of FIG.
An example is shown below.

Next, the operation will be described. A digital signal of 32 symbols per frame read from a compact disk (not shown) and input to the input terminal 1 of the signal processing device is controlled by the address control circuit 5, and is stored in an area 2A of FIG. 2 as shown in FIG. Is written as shown in the direction A and the line B with a delay of one frame every other symbol according to the standard. Then, the written data is read out as shown is controlled from the memory 2 as C1 correction data in the address control circuit 6 from the realm 2A direction C, and line D, and the input to the C1 correction circuit 3 Then, C1 correction is performed.

Next, C1 is stored in the area 2B of the memory map shown in FIG.
The manner in which the corrected data is written to the memory map will be described with reference to FIGS. In a conventional signal processing device, C
After one correction, only the data corrected during the processing was written to the same address. However, in the signal processing device of the present invention, all the data read for the C1 correction after the C1 correction is shown as C2 correction data. The address is written in the area 2B in FIG. At this time, at the time of C2 correction according to the standard, each symbol needs data with a different delay amount, such as 108 frames of delayed data for the first symbol and 104 frames of delayed data for the second symbol.

Here, regarding the second symbol, 10
Delayed data of 5 frames or more is unnecessary. Therefore, as shown in FIG. 2, four independent areas are provided for each symbol, such as 28 bytes for the first symbol and 27 bytes for the second symbol, and four independent areas are provided for each frame. , And write data every four frames in one plane.

More specifically, the memory 2 for the C1 corrected data
At the time of writing to the first frame, the data of the first frame is (0) on the plane 4a of the area 4A in FIG.
(00, 00) The data is written as in line 4C in the direction 4B from address H. Here, the data of the first frame is represented as a delay “0” in the sense that there is no delay amount.

[0017] Then the second frame of data, (1C, 1B) of the planar region 5 A of FIG. 5 (4a + 1) are written from the H address direction 5B, as the line 5C. Here, the data 4C of the first frame is a delay “1” in the sense of the data of the previous frame, and is expressed as 5D.

Next, data of the third frame is written in the direction (6B) from the address (00, 1C) H on the plane (4a + 2) of the area 6A in FIG. Here, the data of the first frame is a delay of “2” in the sense of the data of two frames before and is represented by 6D. The data of the second frame is a delay of "1" meaning data of one frame before, and is represented by 6E.

Next, the data of the fourth frame is written in a direction 7B from the address (1C, 37) H on the plane (4a + 3) of the area 7A in FIG. Here, the data of the first frame is represented by a delay “3” in the sense of data of three frames before, and is represented by 7D. The data of the second frame is represented by a delay of “2” in the sense of data of two frames before.
The data of the third frame is represented by E, the delay is “1” in the sense that the data is one frame before, and is represented by 7F.

Next, the data of the fifth frame is stored in the direction 8B from the address (01,00) H on the plane 4a of the area 8A in FIG.
As shown in line 8C, the first to 27th symbols are written. At this time, (0) of the plane 4a of the region 8A is
0, 1B) The data at address H is 2 of the data in the fifth frame.
Rewritten with the 8th symbol. Here, the data of the first frame is a delay “4” in the sense of data of four frames before, and is represented by 8D. The data of the second frame is a delay of “3” in the sense of data of three frames before, and is represented by 8E. 3
The data of the frame is delayed by "2" in the sense of data of two frames before, and is represented by 8F. The data of the fourth frame is delayed by "1" in the sense of data of one frame before.
Expressed as 8G.

As described above, (4i-3) (i =
1, 2,..., 27, 28)
9 in the ascending order of the frame addresses on the plane 4a of the area 9A,
(4i-2) (i = 1, 2, ..., 27, 28)
The data of the frame is a frame 4a + 1 in the area 9A in FIG.
(4i-1) in ascending order of frame address and in descending order of absolute address
(I = 1, 2,..., 27, 28)
The frame address of plane 4a + 2 in area 9A of FIG.
4i (i = 1, 2, ... 27, 28)
The data of the frame is a frame 4a + 3 in the area 9A of FIG.
Frame in ascending order of address, the absolute address descending 1 accesses the different surfaces in each frame, sequentially write Murrell data every four frames in one plane. At that time, (28-n) (n:
Frame address = 0, 1, ..., 26, 27) or more
Is 4 (28-m) (m:
Symbol address = 0, 1, ..., 25, 26)
Is replaced with the m-th symbol before the frame . As shown in FIG. 9, the data of the 109th frame is the plane 4a of the area 9A.
Is written in the direction of 9E from the address (2,00) H , i.e., i = 28, n = 27 on the plane 4a.
28 symbols from the second symbol excluding the first symbol
The 28th symbol is 4 frames before, (00,
1B) Address H, the 27th symbol is 8 frames before (01,
1A) Address H,..., The third symbol is 104 frames
The previous (01,02) address H, the second symbol is 108 frames
The data at the address (00,01) H before the program is rewritten.
At this time, the planes 4a, (4a + 1), (4a + 2),
Children as (4a + 3) shown in FIG. In this figure, data indicated by "0" in the plane 4a of the area 9A is stored in the first storage area.
Address control circuit of FIG. 1 as C1 correction data from the area
C2 read at 6 and corrected by the first correction circuit
Indicates write data for correction, and the number in each plane is n
Indicates the write data before the frame. Next C1 corrected date
Data writing, that is, data of the 110th frame
Is the plane 4a + 1 of the area 10A as shown in FIG.
(1C, 1B) written in the direction of 10E from address H
The data is indicated by “0”.

Next, the manner in which the C2 correction data is read from the area 2B of FIG. 2 will be described with reference to FIGS. The reading of the C2 correction data from the memory 2 is performed for the first time at the 109th frame from the start of the writing of the C1 corrected data to the memory 2, and is read out from the memory 2 as the C2 correction data by the address control circuit 7 in FIG. Is controlled.

First, (00,
00) Symbol address in ascending order in the direction 9E from address H
Are read from the memory 2.

Reading of the next C2 correction data, that is ,
In the 110th frame , the plane (4
Data indicated by a circle in the order of ascending symbol addresses and descending absolute addresses in the direction 10E from address (1C, 1B) H of (a + 1) is read from the memory 2 . In Figure this, the data indicated by "0" in the plane of the region 10A (4a + 1) 1
The write data after the C1 correction of the tenth frame is shown.
Also, the data with parentheses in the plane 4a of the area 10D indicates the data one frame before , that is, the data after using the C2 correction reading of the 109th frame .

The address of the C1 pointer at the time of C1 correction is controlled by the address control circuit 8 in FIG. 1, and is written into the memory 2 for each frame in the area 2C in FIG.
Further, the address of the C2 pointer at the time of C2 correction is controlled by the address control circuit 9 in FIG. 1, and is written into the memory for each frame in the area 2D in FIG.

The address of the C2 corrected data is controlled by the address control circuit 10 of FIG. 1 and written into the memory as data before D / A conversion for each frame in the area 2E of FIG. This data is controlled by the address control circuit 11 in FIG. 1 and is read out from the memory 2 to the output terminal 12 as an audio signal.

As described above, according to this embodiment, the area in which the C1 corrected data (C2 correction data) is written is divided into four planes, and different planes are sequentially accessed and written for each frame. Therefore, conventionally, the read data read at the time of correction by the second correction circuit is held in the memory for a maximum of 108 frames, but the data is held for a maximum of 3 frames and the memory is effectively used. Can be.

Further, an area for storing data read from the compact disk and an area for reading C1 correction data and an area for writing C1 corrected data (C2 correction data) are independently provided on the memory 2. With the provision, the memory capacity can be increased and the jitter margin can be increased.

[0029]

As described above, according to the signal processing apparatus of the present invention, the first area for storing the digital signal and the first error correction data read from the recording medium, A second area for writing the second error correction data corrected by the correction circuit and a third area for writing the data corrected by the second correction circuit are provided independently of each other. The second error correction data corrected by the correction circuit is transmitted to the second
Is written to each of the unit areas divided into a plurality of areas within the area, unnecessary data after the second error correction processing is sequentially deleted, and the memory can be used effectively. This has the effect.

Further, since the area for writing the data read from the compact disk is provided independently, there is an effect that the jitter margin can be easily increased by increasing the memory capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an address map of a memory of the signal processing device according to one embodiment of the present invention.

FIG. 3 is a diagram partially showing an area of the memory map.

FIG. 4 is a diagram illustrating a signal processing apparatus according to an embodiment of the present invention;
FIG. 9 is a diagram for explaining an operation when writing data of a first frame after one correction.

FIG. 5 is a diagram illustrating a signal processing apparatus according to an embodiment of the present invention;
FIG. 9 is a diagram for explaining an operation when writing data of a second frame after one correction.

FIG. 6 is a diagram illustrating a signal processing apparatus according to an embodiment of the present invention;
FIG. 9 is a diagram for explaining an operation when writing data of a third frame after one correction.

FIG. 7 is a diagram illustrating a signal processing apparatus according to an embodiment of the present invention;
FIG. 9 is a diagram for explaining an operation when writing data of a fourth frame after one correction.

FIG. 8 is a diagram illustrating a signal processing apparatus according to an embodiment of the present invention;
FIG. 7 is a diagram for explaining an operation when writing data of a fifth frame after one correction.

FIG. 9 illustrates a signal processing apparatus according to an embodiment of the present invention;
FIG. 7 is a diagram for explaining an operation when reading C2 correction data of a frame.

FIG. 10 is a diagram for explaining an operation when reading out the C2 correction data of the second frame by the signal processing device according to one embodiment of the present invention.

FIG. 11 is a diagram showing an address map of a memory in a conventional signal processing device.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 memory 3 C1 correction circuit (first error correction circuit) 4 C2 correction circuit (second error correction circuit) 5, 6 address control circuit (first address control means) 7 address control circuit ( Second address control means) 12 output terminal

Continuation of the front page (56) References JP-A-60-256990 (JP, A) JP-A-61-229275 (JP, A) JP-A-63-140464 (JP, A) JP-A-1-116969 (JP) JP-A-3-181069 (JP, A) JP-A-4-232671 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/18 G11B 20/10

Claims (1)

(57) [Claims] 1. A storage circuit for storing a digital signal read from a recording medium, and a first error correction circuit for correcting an error of the digital signal read from the storage circuit as first error correction data. A signal corrected by the first error correction circuit as second error correction data, and a second error correction circuit for correcting the error again. A first storage area for storing a digital signal read from the storage medium and the first error correction data; and a second error after being corrected by the first correction circuit. A second storage area for storing the correction data, and a third storage area for storing the data corrected by the second correction circuit, wherein the digital data is read from the recording medium. First address control means for controlling a signal and the first error correction data and writing the first error correction data into the first storage area; and the second error correction data after being corrected by the first correction circuit. The data is sequentially allocated to each of the plurality of unit areas in the second storage area for each frame and written, and the written second error correction data is read out in the writing order. And a second address control means for controlling the input to the correction circuit.