JPS60107876A - Manufacture of josephson element - Google Patents

Manufacture of josephson element

Info

Publication number
JPS60107876A
JPS60107876A JP58213976A JP21397683A JPS60107876A JP S60107876 A JPS60107876 A JP S60107876A JP 58213976 A JP58213976 A JP 58213976A JP 21397683 A JP21397683 A JP 21397683A JP S60107876 A JPS60107876 A JP S60107876A
Authority
JP
Japan
Prior art keywords
film
mask
lift
throughhole
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58213976A
Other languages
Japanese (ja)
Inventor
Koji Yamada
宏治 山田
Nobuo Miyamoto
信雄 宮本
Hiroyuki Mori
博之 森
Ichisuke Yamanaka
山中 一助
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58213976A priority Critical patent/JPS60107876A/en
Publication of JPS60107876A publication Critical patent/JPS60107876A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0912Manufacture or treatment of Josephson-effect devices

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To form a throughhole for junction eliminating any burrs by a method wherein SnO2 is utilized for a throughhole insulating material for junction and an interlayer material. CONSTITUTION:A thermal oxide film 32 is formed on an Si substrate 31. Firstly a resist tensile mask 33 for forming a lower electrode is provided on the film 32. Secondly a layer to be a lower electrode 34 is formed and lifted off to form the lower electrode 34. Thirdly a throughhole forming mask 35 is formed. Fourthly an SnO2 film is evaporated to form an interlayer insulating film 36. Fifthly the film 36 with throughhole for junction is left by lift off process. Sixthly a lift off mask 37 is formed. Seventhly a tunnel barrier layer 38 is formed by plasma oxidation process. Eighthly SnO2 is evaporated for a protecting film 40. Finally the mask 37 is lifted off to form an upper electrode 39 and the protecting film 40. Through these procedures, any burrs to be generated in case of forming a minute pattern especially a throughhole for junction may be eliminated.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、Pb合金系およびNb系ジョセフソン素子の
作製に係り、竹に接合用スルーホールの作製方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the production of Pb alloy-based and Nb-based Josephson elements, and relates to a method of producing a through hole for bonding to bamboo.

〔発明の背景〕[Background of the invention]

従来のジョセフソン素子では、その接合用スルーポール
の作製方法に問題がわり、設計寸法通りのスルーホール
形成が困難で、各接合間で′1−流密腿が大幅にばらつ
き、動作マージンの低下の原因となっていた。
In the conventional Josephson element, there are problems in the method of manufacturing the through-pole for the junction, making it difficult to form the through-hole according to the design dimensions, and the '1-flow tightness varies greatly between each junction, resulting in a decrease in the operating margin. It was the cause.

まず1図面を用いて従来の作製工程とその問題点を説明
する。
First, a conventional manufacturing process and its problems will be explained using one drawing.

第1図(a)、(t))は従来のジョセフソン素子にお
ける接合用スルーホールの作製工程の説明図である。
FIGS. 1(a) and 1(t) are explanatory diagrams of the manufacturing process of a through hole for bonding in a conventional Josephson element.

図において、11は基板、12はAZ系レジスト(ヘキ
スト社製品)で形成されオーバハング部を有するステン
シルマスク(以下、リフトオフマスクと1う。)、13
はStO膜である。
In the figure, 11 is a substrate, 12 is a stencil mask (hereinafter referred to as lift-off mask) made of AZ-based resist (manufactured by Hoechst Co., Ltd.) and has an overhang, and 13
is a StO film.

第1図(a)に示すように、リフトオフマスク12を用
いて絶縁材料であるSiO膜1.3i蒸着し、リフトオ
フ処理金してパターン形成を行なっていた。
As shown in FIG. 1(a), a lift-off mask 12 was used to deposit an SiO film 1.3i as an insulating material, and a lift-off process was performed to form a pattern.

しかし、SiQは蒸着粒子の散乱が激しくリフトオフマ
スク12のオーバハングの底部および側壁まで回り込ん
で付着し、この後のリフトオフ処理においては第1図(
切に斥すようにパリ(点線丸印で示した部分)等が残存
し、設計寸法通りのスルーホールが形成できなかった。
However, the deposition particles of SiQ are strongly scattered and adhere to the bottom and side walls of the overhang of the lift-off mask 12, and in the subsequent lift-off process, as shown in FIG.
As a result, holes (indicated by dotted circles) remained, making it impossible to form a through hole according to the design dimensions.

このため、前述したように各接合間の電流密度のばらつ
き、動作マージンの低下を生じていた。
For this reason, as described above, variations in current density between the respective junctions and a reduction in the operating margin occur.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、パリ等のない設計寸法通9のジョセフ
ンン接合用スルーホールパターンヲ備工た素子およびそ
の作製方法を提供することにある。
It is an object of the present invention to provide an element having a through-hole pattern for Josephine junctions having the same design dimensions and no holes, etc., and a method for manufacturing the same.

〔発明の概要〕[Summary of the invention]

本発明では、これを央現するために絶縁材料を檀々変え
て検討を行った。すなわち%Qe。
In the present invention, in order to realize this, various insulating materials were used. That is, %Qe.

In20B 、 8nOt等を対象とした。この結果、
S n Oxは抵抗加熱法でも比較的容易に蒸着できて
、しかも%l!1lil!り込みがほとんどなく設計通
シのスルーホールパターンが形成できることが判明した
The targets were In20B, 8nOt, etc. As a result,
S n Ox can be deposited relatively easily by the resistance heating method, and moreover, the deposition rate is %l! 1 lil! It was found that a through-hole pattern consistent with the design could be formed with almost no penetration.

第2図(a)、 (b)は本発明による接合用スルーホ
ールの説明図で、(a)は従来と同様基板21上にオー
バハング部を有するリフトオフマスクを形成し。
FIGS. 2(a) and 2(b) are explanatory diagrams of a through hole for bonding according to the present invention, and FIG. 2(a) shows a lift-off mask having an overhang portion formed on a substrate 21 as in the conventional case.

8n02膜23を蒸着した断面形状を示したものである
。また、(−はリフトオフ後のスルーホールパターンの
断面形状を示したものである。図から明らかなように、
パリ等は全く無く、設計寸法通りのパターンが形成され
ている。
It shows the cross-sectional shape of the 8n02 film 23 deposited. In addition, (- indicates the cross-sectional shape of the through-hole pattern after lift-off. As is clear from the figure,
There are no cracks or the like, and the pattern is formed according to the design dimensions.

なお、ジ、′:1セフソン素子の作製工程においては、
フォトリングラフィによるパターン形成とリフトオフ工
程が、スルーホールの形成だけでなく種々の工程で繰り
返し行なわれるが、各工程で形成さnるリフトオフマス
クはいずれもオーバハング部を有するものであることが
望ましく、本発明のジョセフソンの作製工程でも1種々
の工程でそれを用いている。
In addition, in the manufacturing process of di,′:1 Cefson device,
Pattern formation by photolithography and lift-off steps are repeated in various steps in addition to forming through-holes, but it is desirable that each lift-off mask formed in each step has an overhang portion. It is also used in various steps in the Josephson fabrication process of the present invention.

オー ハハンク部ヲ・有するリフトオフマスクの形成方
法rユ公知の蚊術で69.詳細は、IBMTech B
ull、 19.4048 (1977)に記載されて
いる。
69. How to form a lift-off mask with a hank part using a known method. For details, see IBM Tech B
Ull, 19.4048 (1977).

通常、ポジ型AZ1350Jレジスト(ヘキスト社製)
、ポジ型PMMAレジスト(別名0EBRiooo、東
京応代社#!iが用いられる。前者のAZ1350Jレ
ジストは、パターン露光後、クロロベンゼン浸漬処理に
よりレジスト表面に変質層を形成し、現像処理時に嵐光
された部分の表面が現像液に対して特に溶けにくくする
ことにより、アンダカツ)f起こさせてオーバハング部
を形成している。一方、後者のPMMAは、電子線を照
射するこ七によシ基板からのパックスキック効果により
レジスト底部が無光オーバとなり、現像処理時にアンダ
カットが生じ、オーバハング部を形成することが可能で
ある。また、PMMAは遠紫外光(300nm以下の波
長)照射後、クロロベンゼン浸漬処理をした後に、現像
を行えばアンダカットを起こさせてオーバハング部を形
成することも可能である。
Normally, positive type AZ1350J resist (manufactured by Hoechst)
, a positive PMMA resist (also known as 0EBRiooo, Tokyo Ohdaisha #!i) is used.The former AZ1350J resist forms a modified layer on the resist surface by chlorobenzene immersion treatment after pattern exposure, and is exposed to storm light during development. By making the surface of the portion particularly difficult to dissolve in the developer, an undercut is formed to form an overhang portion. On the other hand, in the case of the latter PMMA, the bottom of the resist becomes lightless due to the pax kick effect from the substrate that is irradiated with the electron beam, causing undercuts during development processing, and it is possible to form an overhang part. . Furthermore, if PMMA is irradiated with far ultraviolet light (wavelength of 300 nm or less), subjected to chlorobenzene immersion treatment, and then developed, it is possible to cause undercuts and form overhang portions.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を実施例により詳細に説明する。 Hereinafter, the present invention will be explained in detail with reference to Examples.

実施例1 第3図(a)〜(0は本発明の一実施例を示す作製工程
説明図で、同図(i肋工完成したpb合金系ジョセフン
ン素子の主要部の断面図である。同図の順番(a)〜(
i)に対応させて主要工程を説明する。
Embodiment 1 FIGS. 3(a) to 3(0) are explanatory diagrams of the manufacturing process showing one embodiment of the present invention, and FIG. Diagram order (a) to (
The main steps will be explained in correspondence with i).

(ω:基板には、50m+φ、厚さ450μm。(ω: The substrate has a thickness of 50 m + φ and a thickness of 450 μm.

<100>のSi基板31を用い、その上に600nm
の熱階化謙32を雄rす一舐酸什臆321−&fT頂(
営浴形成用のレジストステンシルマスク(リフトオフマ
スク)33を設ける。す7トオフマスクはポジ型AJ1
350J レジスト(ヘキスト社製品)を厚さ800 
nm塗布後、70c、30分のプリベーク処理を行った
後、高圧水銀ランプから放つ紫外光(360〜450n
m)でパターン露光を行欧い、クロロベンゼン処理を1
O分間行ない、アルカリ系現像液によシ現像(、て形成
する。
A <100> Si substrate 31 is used, and a 600 nm
321-&fT top (
A resist stencil mask (lift-off mask) 33 for bath formation is provided. The 7-off mask is positive type AJ1.
350J resist (Hoechst product) with a thickness of 800
After applying the nanometer coating, pre-baking at 70C for 30 minutes, applying ultraviolet light (360 to 450N) emitted from a high-pressure mercury lamp.
Perform pattern exposure using step m) and chlorobenzene treatment.
0 minutes, and then developed with an alkaline developer.

(b):リフトオフマスクが形成された8i基板31を
真空槽に挿入し、熱酸化膜32の表面に吸着した水分や
よごれを取シ除くためにArでスパッタクリーニングを
行う。この時条件は、高周波1電力5W、Ar圧力3 
X 10−” Torr、 スパッタ時間5分でるる。
(b): The 8i substrate 31 on which the lift-off mask is formed is inserted into a vacuum chamber, and sputter cleaning is performed using Ar to remove moisture and dirt adsorbed on the surface of the thermal oxide film 32. At this time, the conditions were: high frequency 1 power 5W, Ar pressure 3
X 10-” Torr, sputtering time 5 minutes.

次に真空槽の真空度を5 X 1O−7Torrに減圧
した後、抵抗加熱ヒータにょj) A u 。
Next, after reducing the degree of vacuum in the vacuum chamber to 5 x 10-7 Torr, the resistance heater was turned on.

Pb、 Inの順に積層蒸着を行ない、下部電極34と
なる層を形成する。−例として、膜厚はそれぞれ4nm
、160nm、36nmである。
Pb and In are deposited in this order to form a layer that will become the lower electrode 34. - As an example, the film thickness is 4 nm each.
, 160 nm, and 36 nm.

(C)ニア七トン中でリフトオフi行ない下部電極34
を得る。
(C) Lift-off is carried out in the near seven-ton lower electrode 34
get.

(d)二次に接合用スルーホール形成マスク(リフトオ
フマスク)35を前記下部電極34の形成時と同様の工
程で形成する。使用するレジストの材質、膜厚等も前記
と同じで良い。
(d) A secondary bonding through-hole formation mask (lift-off mask) 35 is formed in the same process as in the formation of the lower electrode 34. The material, film thickness, etc. of the resist used may be the same as above.

(e):再び真空槽に訃いてArスパッタクリーニング
を行った後、砥抗加熱法によシ5nOze膜厚270 
nm蒸着した層間絶縁膜<8n02膜)36を形成する
(e): After performing Ar sputter cleaning in the vacuum chamber again, a film with a thickness of 5nOze and 270
An interlayer insulating film (<8n02 film) 36 is formed by vapor deposition.

(f):アセトン中でリフトオフを行ない、接合用スル
ホール全盲する層間絶縁膜36を残す。
(f): Lift-off is performed in acetone to leave the interlayer insulating film 36 completely covering the bonding through holes.

(g)二次に上部電極形成用のりフトオフマスク37は
、ポジPMMAレジスト(別名0EBI−LlooO。
(g) The lift-off mask 37 for secondary upper electrode formation is a positive PMMA resist (also known as 0EBI-LlooO).

東京応化製)を厚さ1.2μm塗布後、7(1゜60分
のプリベーク処理を行った後、Xe−Hg。
After applying Xe-Hg (manufactured by Tokyo Ohka) to a thickness of 1.2 μm and pre-baking for 1° 60 minutes.

ランプ500Wから放つ遠紫外光(200〜300nm
)でパターン露光を行ない、クロロベンゼン処理を15
分間行ないAIIBK(、jチル」ソ/チル亥トン):
IPA((ソプロとルχル″−ル):1:2の混合液に
より現像して形成した後、真空槽においてスルーホール
中で露出している下部電極34の表面iArのスパッタ
クリーニングを行なう。この時の条件も前の条件と同様
である。次に、真空槽内に02ガスを導入し、圧力2×
10″2’l’ o r rにしてから高周波電力5W
、加速′電圧360Vで15分間プラズマ酸化を行ない
、下s!極の酸化膜(PbO+In2O3)からなるト
ンネルバリア層38を形成する。
Far ultraviolet light (200-300nm) emitted from a 500W lamp
) pattern exposure and chlorobenzene treatment at 15
Do it for a minute AIIBK (, j chill' so/chill 亥ton):
After forming by developing with a mixed solution of IPA ((sopro and χ rule): 1:2), sputter cleaning of iAr on the surface of the lower electrode 34 exposed in the through hole is performed in a vacuum chamber. The conditions at this time are the same as the previous conditions.Next, 02 gas is introduced into the vacuum chamber, and the pressure is 2×
10″2'l' o r r then high frequency power 5W
, plasma oxidation was performed for 15 minutes at an acceleration voltage of 360 V, and the lower s! A tunnel barrier layer 38 made of a polar oxide film (PbO+In2O3) is formed.

(h)二次に真空槽の真空度を5 X 10−’ To
rrに減圧した後、抵抗力ロ熱ヒータによりP b−B
 i (29wt%)の膜(上部電極となる)31膜厚
450nm蒸着n nl蒸着する。この上に連続して保
護膜40として5nQ2を膜厚120 nm蒸着する。
(h) Second, increase the degree of vacuum in the vacuum chamber to 5 x 10-' To
After reducing the pressure to rr, P b-B is
i (29 wt %) film (to be the upper electrode) 31 to a thickness of 450 nm n nl is deposited. On top of this, 5nQ2 is continuously deposited as a protective film 40 to a thickness of 120 nm.

(i):リフトオフマスク37を前記下部電極34の形
成時と同様な方法でアセトンでリフトオフをし、上部電
極(Pb−Bi膜)39と保護膜(Sn02膜)40を
形成する。次に保−膜形成用のレジストマスク(図示せ
ず)を上部′電極形成用マスクと同様な方法で形成した
。但し、レジストマスクの膜厚は、後で核種する保護膜
4」の厚さく例えば1μm)が厚くなるので、リフトオ
フが容易で行えることを考慮し膜厚1.5μmに設定し
形成した。真空槽内に挿入し、Arスパッタクリーニン
グを行った後、snowを膜厚1μm蒸着した。リフト
オフは前述の上部電極形成と同様な方法で行ない、保護
膜41を形成した。
(i): The lift-off mask 37 is lifted off with acetone in the same manner as in the formation of the lower electrode 34, and an upper electrode (Pb-Bi film) 39 and a protective film (Sn02 film) 40 are formed. Next, a resist mask (not shown) for forming a protective film was formed in the same manner as the mask for forming the upper electrode. However, the thickness of the resist mask was set to 1.5 μm in consideration of ease of lift-off since the thickness of the protective film 4 in which the nuclide will be formed later is 1 μm, for example. After inserting it into a vacuum chamber and performing Ar sputter cleaning, snow was deposited to a thickness of 1 μm. Lift-off was performed in the same manner as for forming the upper electrode described above, and the protective film 41 was formed.

以上の工程によって、本発明のpb系ジョセフソン素子
が完成する。
Through the above steps, the pb-based Josephson device of the present invention is completed.

本発明によるジョセフソン素子は、実施例で述べたよう
に絶縁材料5nOzf:用いた結果、接合寸法は設計寸
法に対して極めて忠実であることが、SEM(走査型電
子顕微鏡)観察像により明らかとなり、特性の揃ったも
のが確認された。また、8nO211″1.、素子特性
等に対してもpbとの反応やストレス等のダメージはな
く、かつ、絶縁耐圧も十分でおり極めて安定な絶縁膜で
あることが明らかとなった。さらに、 5nOzは溶媒
液や水液に対しても溶解することなく、極めて安定であ
ることが明らかとなった。
As described in the examples, the Josephson element according to the present invention uses an insulating material of 5nOzf, and as a result, it is clear from SEM (scanning electron microscope) observation images that the junction dimensions are extremely faithful to the design dimensions. , those with the same characteristics were confirmed. In addition, it was revealed that 8nO211''1. did not cause any damage to device characteristics such as reaction with PB or stress, and had sufficient dielectric strength, making it an extremely stable insulating film.Furthermore, It became clear that 5nOz was extremely stable without dissolving in solvents or aqueous solutions.

〔発明の効果〕〔Effect of the invention〕

以上説明しfcように、本発明においては、絶縁材料と
して従来用いられていた5iOtSnOzに置き換えた
が、5n02は、Ut来のSiOと同様な方法例えば、
抵抗加熱ヒータを剛力て容易に蒸着により膜形成ができ
、作製工程においてLfqに困難なことは発生しない。
As explained above, in the present invention, 5iOtSnOz, which has been conventionally used as an insulating material, is replaced, but 5n02 can be replaced with 5iOtSnOz, for example, using the same method as SiO since Ut.
A film can be easily formed by evaporation using a resistance heater, and no difficulties arise with respect to Lfq in the manufacturing process.

そして5本発明によれば、従来微細パターンの形成、特
に接合用スルーホールの形成で問題となっていたパリは
完全に無くなり、設計寸法通りのパターンを作ることが
できるようになり、特性の揃った素子が容易に得らt、
その効果は太きい。
5. According to the present invention, the formation of fine patterns, especially the formation of through holes for bonding, has been completely eliminated, making it possible to create patterns according to the designed dimensions, and with uniform characteristics. The element can be easily obtained.
The effect is profound.

また、本発明’e、Nb系ジョセフソン素子の作製に適
用した結果、Pb系ジョセフノン素子と同様に特性の揃
った素子が再現性よく得られた。
Furthermore, as a result of applying the present invention 'e to the production of a Nb-based Josephson element, an element with uniform characteristics similar to that of a Pb-based Josephson element was obtained with good reproducibility.

なお1本発明は、ジョセフソン素子以外にもリフトオフ
工程を有する素子(例えば、バブルメモリ素子、C1a
As素子等]の作製に応用することができ、大きな効果
を発揮するものでおることは言うまでもない。
Note that the present invention is applicable to devices other than Josephson devices that have a lift-off process (for example, bubble memory devices, C1a
It goes without saying that this method can be applied to the production of As elements, etc., and has great effects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、 (b)は従来のジョセフソン素子にお
ける接合用スルーホールの作製工程説明図、第2図(a
)、(b)は本発明による接合用スルーホールの説明図
、第3図(a)〜(i)は本発明の一実施例を示す作製
工程図で、同図(i)は完成したpb系ジョセフソン素
子の主要部を模式的に示した断面である。 11.21.31・・・基板% 12.22・・・ステ
ンシルマスク(リフトオフマスク)% 13・・・si
o膜、23 ・5nO1膜、32・・・熱酸化膜、33
,35゜37・・・リフトオフマスク%34・・・下部
電極(Pb−A u −i n膜)、36・・・層間絶
縁膜(8nOa膜]、38・・・トンネルバリア層、3
9・・・上部電極、(p b冨 1 図 ¥JZ 図 第 3 図 ′fJ 3 図
Figures 1 (a) and (b) are explanatory diagrams of the manufacturing process of a through hole for bonding in a conventional Josephson element, and Figure 2 (a).
) and (b) are explanatory diagrams of the bonding through-hole according to the present invention, and Figures 3 (a) to (i) are manufacturing process diagrams showing one embodiment of the present invention, and Figure 3 (i) is a diagram of the completed PB. 1 is a cross-sectional view schematically showing the main parts of a Josephson-based Josephson element. 11.21.31...Substrate% 12.22...Stencil mask (lift-off mask)% 13...si
o film, 23 ・5nO1 film, 32... thermal oxide film, 33
, 35° 37... Lift-off mask % 34... Lower electrode (Pb-Au-i-n film), 36... Interlayer insulating film (8nOa film), 38... Tunnel barrier layer, 3
9...Top electrode, (p b 1 Figure\JZ Figure 3 Figure'fJ 3 Figure

Claims (1)

【特許請求の範囲】 1、超電導膜よりなる下部電極と上部′電極を介在分離
しジョセフソン接合を形成する接合用スルーホール絶縁
膜材料および層間絶縁膜材料に5n02’e用いること
を特徴とするジョセフソン素子の作製方法。 2、特許請求の範囲外1項記載の超電導膜材料は、Pb
合金系、Nb系、NbN、MON、N1)ssn。 Nb5AL、VaSi、N0Reであることを特徴トス
るジョセフソン素子の作製方法。
[Scope of Claims] 1. 5n02'e is used as a through-hole insulating film material and interlayer insulating film material for junction that separates a lower electrode and an upper electrode made of a superconducting film to form a Josephson junction. Method for manufacturing a Josephson device. 2. The superconducting film material described in item 1 outside the scope of claims is Pb
Alloy-based, Nb-based, NbN, MON, N1)ssn. A method for manufacturing a Josephson device characterized by being made of Nb5AL, VaSi, and N0Re.
JP58213976A 1983-11-16 1983-11-16 Manufacture of josephson element Pending JPS60107876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58213976A JPS60107876A (en) 1983-11-16 1983-11-16 Manufacture of josephson element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58213976A JPS60107876A (en) 1983-11-16 1983-11-16 Manufacture of josephson element

Publications (1)

Publication Number Publication Date
JPS60107876A true JPS60107876A (en) 1985-06-13

Family

ID=16648181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58213976A Pending JPS60107876A (en) 1983-11-16 1983-11-16 Manufacture of josephson element

Country Status (1)

Country Link
JP (1) JPS60107876A (en)

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