JPH0145218B2 - - Google Patents
Info
- Publication number
- JPH0145218B2 JPH0145218B2 JP56021542A JP2154281A JPH0145218B2 JP H0145218 B2 JPH0145218 B2 JP H0145218B2 JP 56021542 A JP56021542 A JP 56021542A JP 2154281 A JP2154281 A JP 2154281A JP H0145218 B2 JPH0145218 B2 JP H0145218B2
- Authority
- JP
- Japan
- Prior art keywords
- resist
- stencil mask
- thickness
- film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 16
- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052745 lead Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 230000007261 regionalization Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 208000031481 Pathologic Constriction Diseases 0.000 description 1
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910020174 Pb-In Inorganic materials 0.000 description 1
- 125000001797 benzyl group Chemical group [H]C1=C([H])C([H])=C(C([H])=C1[H])C([H])([H])* 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 208000037804 stenosis Diseases 0.000 description 1
- 230000036262 stenosis Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
Landscapes
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
本発明は、リフトオフ用レジストステンシルマ
スクの密着性の向上に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the adhesion of a lift-off resist stencil mask.
低温プロセスにより作成される素子としては、
ジヨセフソン接合素子、GaAsFET素子、Si半導
体素子等がある。 As an element created by a low temperature process,
There are Josephson junction devices, GaAsFET devices, Si semiconductor devices, etc.
例えば、ジヨセフソン接合素子を応用したスイ
ツチング素子は、スイツチング時間や消費電力が
Si半導体素子に比べてそれぞれ約２桁優れた性能
を有し、高速論理、メモリ素子として期待されて
いる。このジヨセフソン接合素子のパターン形成
は、リフトオフ法により作製される。プロセスの
条件は、ジヨセフソン接合素子の特性劣化を防止
するために70℃以下の低温処理で行つている。金
属層はPb合金系、層間絶縁膜はSiOを用いてい
る。リフトオフ用マスクには、ポジ型のAZ1350J
レジスト（光分解型レジストで米国シブレー社の
商品名）をクロルベンゼン処理を施こしたレジス
トステンシルマスクを用いている。 For example, switching devices based on Josephson junction devices have low switching time and power consumption.
They each have performance superior to Si semiconductor devices by about two orders of magnitude, and are expected to be used as high-speed logic and memory devices. This Josephson junction element is patterned using a lift-off method. The process conditions are low-temperature treatment below 70°C to prevent the characteristics of Josephson junction elements from deteriorating. The metal layer is made of Pb alloy, and the interlayer insulating film is made of SiO. Positive type AZ1350J is used for lift-off mask.
A resist stencil mask is used in which resist (photodegradable resist, trade name of Sibley, Inc., USA) is treated with chlorobenzene.
通常、このレジストステンシルマスクは次の工
程により作製される。 Usually, this resist stencil mask is produced by the following steps.
(1) 基板上にカツプリング材HMDS（ヘキサジメ
チルジシラザン）をスピン塗布した後、引続い
て、AZ1350Jレジスト膜を1.5μｍの厚さにスピ
ン塗布をして形成する。(1) After spin-coating the coupling material HMDS (hexadimethyldisilazane) on the substrate, successively spin-coating an AZ1350J resist film to a thickness of 1.5 μm.
(2) プリベークとして70℃、30分間処理をする。(2) Pre-bake at 70℃ for 30 minutes.
(3) 所望のパターン露光を行う。(3) Perform desired pattern exposure.
(4) クロルベンゼン液に10分間浸漬する。(4) Immerse in chlorobenzene solution for 10 minutes.
(5) AZ現像液：水＝１：１を用いて２分間処理
をする。(5) Process for 2 minutes using AZ developer:water = 1:1.
(6) 水洗後、スピン乾燥をして完了。(6) After washing with water, spin dry and complete.
上記の工程により作製したレジストステンシル
１４の断面形状を第１図に示す（例えば、特開昭
54−121114号公報）。しかし、前記の条件（レジ
ストベーク条件、70℃以下）では、下地層間絶縁
膜SiO12と接着性がきわめて悪く、現像中におい
て容易にレジストパターンが流れるという問題が
しばしば発生し安定にパターン形成が出来ない。
現状では、HMDS等のカツプリング材を併用し
ても最小線幅10μｍのパターニングが困難であ
る。この問題は、ベーク温度を70℃以上にすれ
ば、ある程度改善される。しかし、ジヨセフソン
接合素子のパターン形成は、プロセス温度の許容
温度が狭くこれが１つの大きな弊害となつてい
る。 The cross-sectional shape of the resist stencil 14 produced by the above process is shown in FIG.
54-121114). However, under the above conditions (resist bake conditions, 70°C or lower), the adhesion to the underlying interlayer insulating film SiO12 is extremely poor, and the resist pattern often flows easily during development, making stable pattern formation impossible. .
At present, it is difficult to pattern with a minimum line width of 10 μm even if a coupling material such as HMDS is used in combination. This problem can be improved to some extent by increasing the baking temperature to 70°C or higher. However, in patterning Josephson junction elements, the permissible process temperature is narrow, which is one of the major drawbacks.
本発明の目的は、このレジストパターンの流れ
を完全に防止し、低温処理においても安定にパタ
ーン形成ができるレジストステンシルマスクの作
製法を提供しようというものである。 An object of the present invention is to provide a method for manufacturing a resist stencil mask that completely prevents this flow of the resist pattern and allows stable pattern formation even during low-temperature processing.
本発明によるレジストステンシルマスクの特徴
は、基板とレジストの間にAlの層を設けること
にある。すなわち、次の工程により作製する。 A feature of the resist stencil mask according to the present invention is that an Al layer is provided between the substrate and the resist. That is, it is manufactured by the following steps.
(1) 基板上にAlを真空蒸着により10〜200Åの厚
さにカツプリング材として形成する。(1) Al is formed as a coupling material on the substrate by vacuum evaporation to a thickness of 10 to 200 Å.
(2) AZ1350Jレジスト膜を1.5μｍの厚さにスピン
塗布して形成する。(2) Spin coat an AZ1350J resist film to a thickness of 1.5 μm.
(3) プリベークとして70℃、30分間処理する。(3) Pre-bake at 70°C for 30 minutes.
(4) 所望のパターン露光を行う。(4) Perform desired pattern exposure.
(5) クロルベンゼン液に、10分間浸漬する。(5) Immerse in chlorobenzene solution for 10 minutes.
(6) AZ現像液：水＝１：１を用いて２分間処理
をする。(6) Process for 2 minutes using AZ developer:water = 1:1.
(7) 水洗後スピン乾燥をして完了。(7) After washing with water, spin dry and complete.
上記の工程により作製したレジストステンシス
マスクの断面形状を第２図に示す。 FIG. 2 shows the cross-sectional shape of the resist stenosis mask manufactured by the above process.
このマスクの特徴は、次の点にある。 The features of this mask are as follows.
(1) 金属層（Al上）の上では、AZ1350Jレジス
トは密着性が著しく改善され、これにより微細
パターンが作製できる。(1) On the metal layer (on top of Al), the adhesion of AZ1350J resist is significantly improved, which allows the creation of fine patterns.
(2) 現像液は、アルカリ系が用いられるために
Alのエツチングが可能であり、したがつて不
要部のAlが現像と同時に除去できる。(2) Since an alkaline developer is used,
Etching of Al is possible, so unnecessary Al can be removed at the same time as development.
(3) 現像中にアンダカツトが生じるために、超電
導金属を蒸着してもAlと接触することがなく
シヨートの恐れがない。(3) Since undercuts occur during development, even if the superconducting metal is vapor-deposited, it will not come into contact with Al and there is no risk of shoots.
以上のようにAlをカツプリング材として用い
ることにより、70℃プロセスにおいても安定した
レジストステンシルマスクのパターン形成が可能
となり、これにより1μｍピツチの微細なパター
ンも容易に作製できるようになつた。 As described above, by using Al as a coupling material, stable resist stencil mask pattern formation is possible even in a 70°C process, and as a result, fine patterns with a pitch of 1 μm can be easily produced.
以下に、上記のレジストステンシルマスクを用
いた線幅2.5μｍの制御線を持つジヨセフソン接合
論理素子のパターン作製について実施例で詳細に
説明する。 In the following, a detailed explanation will be given in Examples of fabricating a pattern of a Josephson junction logic element having a control line with a line width of 2.5 μm using the above-mentioned resist stencil mask.
本発明により作製したジヨセフソン接合論理素
子の断面図を第３図に示す。 A cross-sectional view of a Josephson junction logic element manufactured according to the present invention is shown in FIG.
基板には、直径40mmφ、厚さ350μｍ＜100＞の
Si基板３１を用いた。なお、Si基板上には6000Å
の熱酸化膜が施してある。このSi基板３１上に
Nb膜を電子ビーム蒸着により膜厚3000Å被着し
グランドプレーン３２とした。その後、陽極酸化
法によりNbの表面にNb2O3３３を膜厚1500Åに
形成し、ついで、層間絶縁膜としてSiO３４を膜
厚2000Å被着し、引続いて、Alを100Å被着し
た。次に、上部電極用のレジストステンシルマス
クの形成について述べる。 The substrate has a diameter of 40 mmφ and a thickness of 350 μm <100>.
A Si substrate 31 was used. In addition, there is a thickness of 6000Å on the Si substrate.
A thermal oxide film is applied. On this Si substrate 31
A Nb film with a thickness of 3000 Å was deposited by electron beam evaporation to form a ground plane 32. Thereafter, Nb 2 O 3 33 was formed to a thickness of 1500 Å on the surface of Nb by anodic oxidation, then SiO 34 was deposited to a thickness of 2000 Å as an interlayer insulating film, and then Al was deposited to a thickness of 100 Å. Next, the formation of a resist stencil mask for the upper electrode will be described.
Az1350Jレジストを前記Al膜を有する基板３１
上に1.5μｍの厚さに形成し、引続いて空気中にお
いて70℃、30分間のプリベークを行う。ついで、
所望のパターンを露光後、クロルベンゼン液に10
分間浸漬し、さらに、アルカリ系現像液を用いて
２分間の現像処理を行つた。現像液の組成は
AZ1350J現像液：水＝１：１を用いた。この現像
処理によりAlは完全に除去される。なお、上記
の条件で作製したレジストステンシルマスクのオ
ーバハングは0.3μtであつた。次に、レジストス
テンシルパターンを形成したSi基板３１を真空槽
内に挿入しSiO３４の表面に吸着した水分やよご
れを取り除くためにArでスパツタクリーニング
を行つた。この時の条件はrfパワー5W、Ar圧力
３×10-3Torr、スパツタ時間５分である。真空
槽内の真空度を５×10-7Torrに減圧した後、抵
抗加熱ヒータによりAu、Pb、Inの順に積層蒸着
を行つた。一例として、膜厚はそれぞれ40Å、
1600Å、360Åである。蒸着後、表面保護膜を形
成するために、真空槽内にO2ガスを導入し１気
圧にしてから、真空槽内の温度を60℃に保ち60分
間の酸化処理を行つた。この後、真空槽内により
基板３１を取り出して、アセトン中でリフトオフ
を行つた。この処理によつて表面に保護膜が形成
された下部電極３５とレジスト下にあつたAl膜
のみが残され、マスクに用いたレジストステンシ
ルマスクは除去される。次に、ウインド孔３７用
のレジストステンシルマスクを、下部電極と同様
に作製し、再び真空装置内においてArによるス
パツタクリーニング（この工程で前記レジスト下
にあつたAl膜は除去される）を行つた後、SiOを
膜厚2500Å被着し、連続してAlを100Å被着し
た。リフトオフは、前述の下部電極と同様な方法
で行ないウインド孔３７を形成した。次に、上部
電極用のレジストステンシルマスクを下部電極と
同様に作製し、真空槽内において、下部電極３５
面上をArのスパツタクリーニングを行つた。こ
の時の条件は、下部電極、ウインド孔の形成と同
である。引続いて、真空槽内にO2ガスを導入し
１気圧にしてから、真空槽内の温度を70℃に保ち
60分間の熱酸化処理を行ないトンネルバリア層３
６を形成した。次いで、真空槽内の真空度を５×
10-7Torrに減圧した後、抵抗加熱ヒータにより
Pb、Au、Pbの順に積層蒸着を行つた。膜厚はそ
れぞれ1500Å、50Å、1500Åである。引続いて、
この上に保護膜としてSiOを膜厚1000Åを蒸着し
た。蒸着後、真空槽内から取り出してアセトン中
でリフトオフを行ない上部電極３８と保護膜SiO
３９を形成した。次に、再びリフトオフ法を用い
て層間絶縁膜SiOを6000Åの厚さに形成した後、
連続してAlを100Å被着し、その後、真空槽より
基板３１を取り出し、リフトオフにより層間絶縁
膜４０を形成した。次に、制御線用のレジストス
テンシルマスクを下部電極、上部電極と同様な方
法で作製した。制御線の最小パターン寸法の一例
は2.5μｍである。Arによるスパツタクリーニン
グ後、ベンジル内の真空度を５×10-7Torr以下
でPb、Au、Inの順で積層蒸着を行つた。膜厚は
それぞれ5400Å、100Å、2500Åである。蒸着後、
ベルジヤ内から取り出してアセトン中でリフトオ
フを行ない制御線４１形成した。最後に保護膜４
２をSiOを1.5μｍの厚さに被着しリフトオフ法に
より形成した。以上述べたようなレジストステン
シルマスクを用いたリフトオフ法によりジヨセフ
ソン接合論理素子を作製した。 The Az1350J resist is applied to the substrate 31 having the Al film.
It is formed on the top to a thickness of 1.5 μm, and then prebaked in air at 70° C. for 30 minutes. Then,
After exposing the desired pattern, immerse it in chlorobenzene solution for 10 minutes.
The sample was immersed for 1 minute, and then developed using an alkaline developer for 2 minutes. The composition of the developer is
AZ1350J developer:water=1:1 was used. Al is completely removed by this development process. Note that the overhang of the resist stencil mask produced under the above conditions was 0.3 μt. Next, the Si substrate 31 on which the resist stencil pattern was formed was inserted into a vacuum chamber, and spatter cleaning was performed with Ar to remove moisture and dirt adsorbed on the surface of the SiO 34. The conditions at this time were RF power of 5 W, Ar pressure of 3×10 -3 Torr, and sputtering time of 5 minutes. After reducing the degree of vacuum in the vacuum chamber to 5×10 −7 Torr, layered deposition of Au, Pb, and In was performed in this order using a resistance heater. As an example, the film thickness is 40 Å,
1600Å, 360Å. After vapor deposition, in order to form a surface protective film, O 2 gas was introduced into the vacuum chamber to 1 atm, and then oxidation treatment was performed for 60 minutes while maintaining the temperature inside the vacuum chamber at 60°C. Thereafter, the substrate 31 was taken out of the vacuum chamber and lifted off in acetone. By this process, only the lower electrode 35 with a protective film formed on the surface and the Al film under the resist are left, and the resist stencil mask used as a mask is removed. Next, a resist stencil mask for the window hole 37 is made in the same way as for the lower electrode, and spatter cleaning with Ar is performed again in the vacuum apparatus (in this step, the Al film under the resist is removed). After that, SiO was deposited to a thickness of 2,500 Å, followed by Al to a thickness of 100 Å. Lift-off was performed in the same manner as for the lower electrode described above to form a window hole 37. Next, a resist stencil mask for the upper electrode is made in the same way as for the lower electrode, and the lower electrode 35 is placed in a vacuum chamber.
Ar spatter cleaning was performed on the surface. The conditions at this time are the same as those for forming the lower electrode and window hole. Subsequently, O 2 gas was introduced into the vacuum chamber to 1 atm, and the temperature inside the vacuum chamber was maintained at 70℃.
Tunnel barrier layer 3 is formed by thermal oxidation treatment for 60 minutes.
6 was formed. Next, the degree of vacuum in the vacuum chamber was increased to 5×
After reducing the pressure to 10 -7 Torr, the resistance heater
Laminated deposition was performed in the order of Pb, Au, and Pb. The film thicknesses are 1500 Å, 50 Å, and 1500 Å, respectively. Subsequently,
On top of this, SiO was deposited as a protective film to a thickness of 1000 Å. After the deposition, the upper electrode 38 and the protective film SiO are removed from the vacuum chamber and lifted off in acetone.
39 was formed. Next, after forming an interlayer insulating film SiO to a thickness of 6000 Å using the lift-off method again,
Al was continuously deposited to a thickness of 100 Å, and then the substrate 31 was taken out of the vacuum chamber and an interlayer insulating film 40 was formed by lift-off. Next, a resist stencil mask for control lines was produced in the same manner as the lower and upper electrodes. An example of the minimum pattern size of the control line is 2.5 μm. After spatter cleaning with Ar, Pb, Au, and In were deposited in this order at a vacuum level of 5×10 −7 Torr or less in the benzyl chamber. The film thicknesses are 5400 Å, 100 Å, and 2500 Å, respectively. After vapor deposition,
The control line 41 was formed by taking it out from the bell gear and performing lift-off in acetone. Finally, protective film 4
2 was formed by depositing SiO to a thickness of 1.5 μm and using a lift-off method. A Josephson junction logic element was fabricated by the lift-off method using a resist stencil mask as described above.
本発明によるレジストステンシルマスクを用い
てジヨセフソン接合素子のパターン作製を行つた
結果、レジストパターンの流れは皆無となり最小
パターン寸法2.5μｍピツチを持つ制御線が精度よ
く、かつ再現性よく得られることが実現出来た。
また、本発明によるレジストステンシルマスクを
用いれば最小パターン寸法1.0μｍのピツチも作製
することが明らかとなり低温プロセスにおける微
細パターン化が可能となつた。 As a result of fabricating a Josephson junction element pattern using the resist stencil mask according to the present invention, it was realized that there was no flow of the resist pattern and control lines with a minimum pattern size of 2.5 μm pitch could be obtained with high precision and high reproducibility. done.
Furthermore, it has become clear that pitches with a minimum pattern size of 1.0 μm can be produced by using the resist stencil mask according to the present invention, making it possible to form fine patterns in a low-temperature process.
第１図は従来のレジストステンシルマスクの断
面図、第２図は本発明の作製法により作製したレ
ジストステンシルマスクの断面図、第３図は本発
明の一実施例において作製したジヨセフソン接合
論理素子の断面図である。
１１……基板、１２……SiO膜、１３……
HMDSカツプリング材、１４……AZ1350Jレジ
スト、２１……基板、２２……SiO膜、２３……
Alカツプリング材、２４……AZ1350Jレジスト、
３１……基板（Siウエーハ、熱酸化膜も含む）、
３２……Nbグランドプレーン、３３……Nb2O3
膜、３４……層間絶縁膜、３５……下部電極
（Au−Pb−In）、３６……トンネルバリア層、３
７……ウインド孔SiO膜、３８……上部電極（Pb
−Au−Pb）、３９……保護膜SiO（上部電極用）、
４０……層間絶縁膜SiO、４１……制御線（Pb−
Au−In）、４２……保護膜SiO。
FIG. 1 is a cross-sectional view of a conventional resist stencil mask, FIG. 2 is a cross-sectional view of a resist stencil mask manufactured by the manufacturing method of the present invention, and FIG. 3 is a cross-sectional view of a Josephson junction logic element manufactured in an embodiment of the present invention. FIG. 11...Substrate, 12...SiO film, 13...
HMDS coupling material, 14...AZ1350J resist, 21...Substrate, 22...SiO film, 23...
Al coupling material, 24...AZ1350J resist,
31...Substrate (including Si wafer and thermal oxide film),
32...Nb ground plane, 33...Nb 2 O 3
Film, 34... Interlayer insulating film, 35... Lower electrode (Au-Pb-In), 36... Tunnel barrier layer, 3
7... Wind hole SiO film, 38... Upper electrode (Pb
-Au-Pb), 39...protective film SiO (for upper electrode),
40... Interlayer insulating film SiO, 41... Control line (Pb-
Au-In), 42...protective film SiO.
Claims (1)
る工程、 上記Al上にポジ型のレジスト膜を形成する工
程、 上記レジスト膜を所望のパターンに露光する工
程、および 上記レジスト膜をクロルベンゼン中に浸漬した
後アルカリ現像液を用いて現像処理することによ
り、被露光部のレジスト膜および被露光部のレジ
スト膜下のAlを除去する工程、 を有することを特徴とするリフトオフ用ステンシ
ルマスクの作成法。 ２ 上記基板がSiOであることを特徴とする特許
請求の範囲第１項記載のリフトオフ用ステンシル
マスクの作成法。[Claims] 1. A step of depositing Al with a thickness of 10 to 200 Å on a predetermined substrate. A step of forming a positive resist film on the Al. A step of exposing the resist film to a desired pattern. and a step of removing the resist film in the exposed area and Al under the resist film in the exposed area by immersing the resist film in chlorobenzene and then developing it using an alkaline developer. How to create a stencil mask for lift-off. 2. The method for producing a lift-off stencil mask according to claim 1, wherein the substrate is SiO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56021542A JPS57136321A (en) | 1981-02-18 | 1981-02-18 | Manufacture of resist stencil mask for lift-off |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56021542A JPS57136321A (en) | 1981-02-18 | 1981-02-18 | Manufacture of resist stencil mask for lift-off |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57136321A JPS57136321A (en) | 1982-08-23 |
| JPH0145218B2 true JPH0145218B2 (en) | 1989-10-03 |
Family
ID=12057860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56021542A Granted JPS57136321A (en) | 1981-02-18 | 1981-02-18 | Manufacture of resist stencil mask for lift-off |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57136321A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60130183A (en) * | 1983-12-19 | 1985-07-11 | Agency Of Ind Science & Technol | Resist stencil mask for manufacturing josephson ic |
| JPH0294807A (en) * | 1988-09-30 | 1990-04-05 | Mitsubishi Mining & Cement Co Ltd | Manufacture of surface acoustic wave device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5158072A (en) * | 1974-11-18 | 1976-05-21 | Matsushita Electric Ind Co Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS5330799A (en) * | 1976-09-01 | 1978-03-23 | Fujitsu Ltd | Resist exposure |
-
1981
- 1981-02-18 JP JP56021542A patent/JPS57136321A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5158072A (en) * | 1974-11-18 | 1976-05-21 | Matsushita Electric Ind Co Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS5330799A (en) * | 1976-09-01 | 1978-03-23 | Fujitsu Ltd | Resist exposure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57136321A (en) | 1982-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0160940B2 (en) | ||
| US4299679A (en) | Method of producing Josephson elements of the tunneling junction type | |
| JPH0145218B2 (en) | ||
| JP2682136B2 (en) | Method of manufacturing Josephson device | |
| JPS5978586A (en) | Formation of niobium pattern | |
| JPS58209183A (en) | Manufacture of josephson junction element | |
| JPH0511432B2 (en) | ||
| JPS58115835A (en) | Formation of buried wirings of semiconductor device | |
| JPH0526358B2 (en) | ||
| JPS6260835B2 (en) | ||
| JPS5961975A (en) | Josephson element and manufacture thereof | |
| JPH01168080A (en) | Manufacture of josephson junction element | |
| JPS5868994A (en) | Manufacture of josephson integrated circuit | |
| JPS62195190A (en) | Formation of planar type josephson junction device | |
| JPS6086834A (en) | Formation of pattern | |
| JPS61144083A (en) | Forming method of josephson junction element | |
| JPH0213466B2 (en) | ||
| JPH0210589B2 (en) | ||
| JPS5877268A (en) | Manufacture of tunnel type josephson junction element | |
| JPS58125884A (en) | Manufacture of josephson integrated circuit | |
| JPS5897879A (en) | Substrate for manufacturing josephson element | |
| JPH0141016B2 (en) | ||
| JPS60208874A (en) | Manufacture of josephson junction element | |
| JPS6262469B2 (en) | ||
| JPH0637365A (en) | Connecting structure for superconducting wiring |