JPS60107794A - Current switching circuit - Google Patents

Current switching circuit

Info

Publication number
JPS60107794A
JPS60107794A JP58213980A JP21398083A JPS60107794A JP S60107794 A JPS60107794 A JP S60107794A JP 58213980 A JP58213980 A JP 58213980A JP 21398083 A JP21398083 A JP 21398083A JP S60107794 A JPS60107794 A JP S60107794A
Authority
JP
Japan
Prior art keywords
current
transistor
current switching
switching circuit
small
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58213980A
Other languages
Japanese (ja)
Inventor
Kazuo Kanetani
一男 金谷
Kunihiko Yamaguchi
邦彦 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58213980A priority Critical patent/JPS60107794A/en
Publication of JPS60107794A publication Critical patent/JPS60107794A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To prevent overshoot and ringing of a current of a transistor (TR) switched from nonconduction to conduction by inserting a resistor between an emitter of the TR of a current switching circuit of a semiconductor memory and a current supply line. CONSTITUTION:In applying the circuit to a sense circuit, resistors 21-28 for current damping between the emitter of the current switching TR and the current source are connected in series and when the said TR is switched from nonconduction to conduction, the flowing of the charging current to parasitic capacitors Cs1-Cs3 is suppressed from being flowed rapidly. Thus, the overshoot of the current of the said TR is small and the ringing is less and sense output voltages VSG, V'SG are voltages with small oscillation. Moreover, the oscillation of digit line clamp voltages Vc, Vc' is small and the undershoot is small and then the saturation of a TR11 is prevented.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はバイポーラ型半導体装置の電流切換回路におい
て、電流切換え時における電流のオーツ(−シュート、
及びリンギングを防止するに好適な電流切換回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a current switching circuit for a bipolar semiconductor device.
and a current switching circuit suitable for preventing ringing.

〔発明の背景〕[Background of the invention]

バイポーラ型半導体装置の電流切換回路の例として、第
1図に示す半導体メモリのセンス回路〃工知らnている
。第1図で1はワード線、2はディジット線、3はメモ
リセル、4は情報保持用の電流源、5はティジット線ク
ランプ用の電流源、6は読み出し用の電流源である。各
ディジット線にエミッタが接続され、トランジスタ13
のヘースには参照電圧が印加さ肛ており、これらのトラ
ンジスタのコレクタが共通に接続され、それぞれトラン
ジスタ14.15のエミッタに接続されて、ワイヤード
オア接続となっている。また、7〜12はそれぞれデ・
fジット線対の選択用のトランジスタでおる。この回路
によれば読み出し電流は選択された記憶セルの情報によ
って、メモリセルとトランジスタ14か15のいずれか
一方に流れる。従ってセンス出力信号線16及び17に
電位差を生じ、差動アンプ18を介してメモリの情報が
出力される。
As an example of a current switching circuit for a bipolar semiconductor device, there is a sense circuit for a semiconductor memory shown in FIG. In FIG. 1, 1 is a word line, 2 is a digit line, 3 is a memory cell, 4 is a current source for holding information, 5 is a current source for clamping the digit line, and 6 is a current source for reading. The emitter is connected to each digit line, and the transistor 13
A reference voltage is applied to the transistors 14 and 14, and the collectors of these transistors are connected in common, and are connected to the emitters of transistors 14 and 15, respectively, forming a wired-OR connection. Also, 7 to 12 are each de
This is a transistor for selecting the f-bit line pair. According to this circuit, the read current flows through the memory cell and either transistor 14 or 15 depending on the information of the selected memory cell. Therefore, a potential difference is generated between the sense output signal lines 16 and 17, and memory information is outputted via the differential amplifier 18.

次にこの回路の欠点を説明する。ディジット線選択信号
Vy1が高電位(High)から低電位(LOW)に切
換わ’) h V Y2 カL oWカラHI gh 
K 切換わるとトランジスタ7及び9から流れていた読
み出し電流が切れ、トランジス゛り10及び12から流
れる工うになる。この時、読み出し′電流が第3図の破
線のように切換わるならは問題にならないが、■!2が
LOWからHighに切換わる時寄生容量Cmsを光電
するために第3図の実線のようなオーバーシュートのあ
る電流となり、その後エミッタホロアのリンキング現象
のようにリンギングする。前述の如く、メモリセルの記
憶情報のセンス方式は読み出し電流をトランジスタ14
か15のいずれか一方に流し、センス出力信号線に電位
差を生じさせる方式なので5例えばリンキングをともな
った振動の大きい読み出し電流がトランジスタ10と1
3を介してトランジスタ14に流れるとセンス出力信号
線16の電圧(Vsa)が第4図の実線の如く振動する
。このような振動のある信号は、差動アンプ18の出力
波形を歪ませる等、正常動作の障害となる。また、読み
出し電流はメモリセルにも流れるのでメモリセルの情報
を反転させる原因ともなる。
Next, the drawbacks of this circuit will be explained. The digit line selection signal Vy1 is switched from high potential (High) to low potential (LOW).
When K is switched, the read current flowing from transistors 7 and 9 is cut off, and begins to flow from transistors 10 and 12. At this time, if the read current changes as shown by the broken line in Figure 3, there is no problem, but ■! 2 switches from LOW to HIGH, the parasitic capacitance Cms is photoelectrically charged, resulting in a current with an overshoot as shown by the solid line in FIG. 3, and then ringing occurs as in the emitter-follower linking phenomenon. As mentioned above, the sensing method for information stored in a memory cell is such that the read current is passed through the transistor 14.
For example, the read current with large oscillations accompanied by linking is passed through either transistors 10 and 15 and creates a potential difference in the sense output signal line.
3 to the transistor 14, the voltage (Vsa) of the sense output signal line 16 oscillates as shown by the solid line in FIG. Such a vibrating signal distorts the output waveform of the differential amplifier 18, thereby interfering with normal operation. Further, since the read current also flows to the memory cell, it also causes the information in the memory cell to be inverted.

さらに別の問題として、ディジット線クランプ用電流が
トランジスタ8から11に切換わる時、寄生容量Cl1
zt充電するために、読み出し電流と同じように第3図
の実線のようなオーツく一シュートとリンギングをとも
なった’を流がトランジスタ11に流れる。このためデ
ィジット線りランゾ信号線19の電圧(Vc)が第5図
の実線のようになり、トランジスタ11が飽和したり、
Vcが振動したりして、メモリの誤動作の原因となる。
Yet another problem is that when the digit line clamping current is switched from transistor 8 to transistor 11, the parasitic capacitance Cl1
In order to charge zt, a current flows through the transistor 11 with an automatic shoot and ringing as shown by the solid line in FIG. 3 in the same way as the read current. Therefore, the voltage (Vc) of the digit line Lanzo signal line 19 becomes as shown by the solid line in FIG. 5, and the transistor 11 becomes saturated.
Vc may oscillate, causing memory malfunction.

〔発明の目的〕[Purpose of the invention]

本発明の目的は半導体メモリの%光切換回路において、
非導通から導通に切換わるトランジスタの電流のオーバ
ーシュートやリンギングを防止した電流切換回路を提供
することにある。
An object of the present invention is to provide a % optical switching circuit for a semiconductor memory.
An object of the present invention is to provide a current switching circuit that prevents overshoot and ringing of the current of a transistor that switches from non-conductive to conductive.

〔発明の概要〕[Summary of the invention]

電流切換回路において、非導通から導通に切換わるトラ
ンジスタの電流がオーバーシュートするのは、寄生容i
t Cmへの充電が急峻に行なわれるためであるので、
オーバーシュートを低減するには寄生容it Cmへの
充電をおだやかにすることで解決できる。一般に、容量
への充電をおだやかにする方法として送電端と容量の間
に抵抗を入れることが知ら扛ておシ、これを応用した。
In a current switching circuit, the overshoot of the current of a transistor that switches from non-conducting to conducting is due to the parasitic capacitance i.
This is because charging to t Cm is done rapidly, so
Overshoot can be reduced by charging the parasitic capacitance it Cm more slowly. Generally speaking, it is known that one way to slow down the charging of a capacitor is to insert a resistor between the power transmission end and the capacitor, and this was applied.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例としてメモリのセンス回路への
適用例を第2図により説明する。
Hereinafter, as an embodiment of the present invention, an example of application to a memory sense circuit will be described with reference to FIG.

図面番号1〜20は第1図に準じ、21〜28の抵抗は
本発明の特徴を成す電流ダンピング用の抵抗でるる。こ
の抵抗は電流切換え用トランジスタのエミッタと電流源
との間に直列に接続さnてしh 愉倍朽1血9田に→ン
一)フl慰凸道二i植−り道通に切換わった時、寄生容
量(061〜Csa )への充電電流が急峻に流れよう
とするの會押えている。
Drawing numbers 1 to 20 correspond to FIG. 1, and resistors 21 to 28 are current damping resistors that are a feature of the present invention. This resistor is connected in series between the emitter of the current switching transistor and the current source. This prevents the charging current from flowing steeply to the parasitic capacitors (061 to Csa) when the capacitance is turned off.

このため%電流切換え用トランジスタの電流は第3図の
破線のようなオーバシュートが小さく、す/キングも小
さい電流となり、センス出力電圧(Vgo 、 Vso
)は第4図の破線のような振動の小さい電圧となる。ま
た、ディジット線クランプ電圧(Vc 、 Vc )は
第5図の破線のような振動が小さく、かつアンダーシュ
ートの小さい電圧となり、トランジスター1の飽和も防
止されている。
Therefore, the current of the % current switching transistor has a small overshoot as shown by the broken line in Fig. 3, and a current with a small S/King.
) becomes a voltage with small oscillations as shown by the broken line in FIG. Further, the digit line clamp voltages (Vc, Vc) have small vibrations as shown by the broken line in FIG. 5, and have small undershoots, so that saturation of the transistor 1 is also prevented.

なお、ダンピング抵抗は電流切換え用トランジスタのエ
ミッタのすぐ近くに配置すべきである。エミッタとダン
ピング抵抗の間に容量が入るとダンピング抵抗の効果が
弱まる。
Note that the damping resistor should be placed very close to the emitter of the current switching transistor. If a capacitance is inserted between the emitter and the damping resistor, the effect of the damping resistor will be weakened.

以上、本実施例によれば、電流切換回路にνいて電流切
換え時における電流のオーバーシュートやリンキングを
低減でき、回路の誤動作の防止に効果がある。
As described above, according to this embodiment, it is possible to reduce current overshoot and linking during current switching by using ν in the current switching circuit, which is effective in preventing malfunction of the circuit.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、センス出力信号、及びゲイジット線ク
ランプ信号のリンギング全低減でき、さらにディジット
線クランプ用電流を切換えるトランジスタの飽和防止も
でき誤動作が起こり難くなるので回路の性能向−トに効
果がある。
According to the present invention, it is possible to completely reduce the ringing of the sense output signal and the digit line clamp signal, and also to prevent the saturation of the transistor that switches the digit line clamp current, making it difficult for malfunctions to occur, which is effective in improving the performance of the circuit. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電流切換回路を具備するセンス回路、第
2図は本発明による電流切換回路を具備するセンス回路
、第3図と第4図及び第5図は本発明の詳細な説明する
路線図である。 ′fJ+ 口 SZ 図 VJ 3 図 第 4 旧 第 5 図 仏 吟 ℃1
FIG. 1 shows a sense circuit with a conventional current switching circuit, FIG. 2 shows a sense circuit with a current switching circuit according to the present invention, and FIGS. 3, 4, and 5 provide a detailed explanation of the present invention. This is a route map. 'fJ+ 口SZ Figure VJ 3 Figure 4 Old Figure 5 Buddha Gin ℃1

Claims (1)

【特許請求の範囲】 1、電流源及びエミッタが該電流源に接続され、ベース
が各々独立の駆動線に接続された複数個のトランジスタ
を有する電流切換回路において、各々のトランジスタの
エミッタと電流供給線の間に抵抗を挿入したことを特徴
とする電流切換回路。 2、複数対のディジット線と、各ディジット線にエミッ
タがそれぞれ接続され、メモリセルとの間で電流切換動
作する読出し用トランジスタと、各対のディジット線の
一方に接続された読出しトランジスタのコレクタに共通
に接続された第1の信号線と、該第1の信号線に抵抗を
介して接続されたベース接地の第1のトランジスタと、
各対のディジット線の他方に接続された読出しトランジ
スタのコレクタに共通に接続された第2の信号線と、該
第2の信号線に抵抗を介して接続されたベース接地の第
2のトランジスタとを有する電流切換回路。
[Claims] 1. In a current switching circuit having a plurality of transistors whose current sources and emitters are connected to the current source and whose bases are connected to independent drive lines, the emitter of each transistor and the current supply A current switching circuit characterized by inserting a resistor between the wires. 2. A plurality of pairs of digit lines, a read transistor whose emitter is connected to each digit line and which performs current switching operation between the memory cell and the collector of the read transistor connected to one of the digit lines of each pair. a commonly connected first signal line; a common-base first transistor connected to the first signal line via a resistor;
a second signal line commonly connected to the collectors of the read transistors connected to the other of the digit lines of each pair; and a second transistor with a common base connected to the second signal line via a resistor. A current switching circuit with
JP58213980A 1983-11-16 1983-11-16 Current switching circuit Pending JPS60107794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58213980A JPS60107794A (en) 1983-11-16 1983-11-16 Current switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58213980A JPS60107794A (en) 1983-11-16 1983-11-16 Current switching circuit

Publications (1)

Publication Number Publication Date
JPS60107794A true JPS60107794A (en) 1985-06-13

Family

ID=16648248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58213980A Pending JPS60107794A (en) 1983-11-16 1983-11-16 Current switching circuit

Country Status (1)

Country Link
JP (1) JPS60107794A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109067220A (en) * 2018-07-16 2018-12-21 电子科技大学 A kind of circuit control device with damping Real Time Control Function
CN110098632A (en) * 2018-01-29 2019-08-06 中国电力科学研究院有限公司 A kind of virtual synchronous Generator Damping quantifies recognition methods, system and device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110098632A (en) * 2018-01-29 2019-08-06 中国电力科学研究院有限公司 A kind of virtual synchronous Generator Damping quantifies recognition methods, system and device
CN110098632B (en) * 2018-01-29 2021-08-06 中国电力科学研究院有限公司 Method, system and device for quantitatively identifying damping coefficient of virtual synchronous generator
CN109067220A (en) * 2018-07-16 2018-12-21 电子科技大学 A kind of circuit control device with damping Real Time Control Function

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