JPS6010749A - Master slice integrated circuit - Google Patents

Master slice integrated circuit

Info

Publication number
JPS6010749A
JPS6010749A JP11913183A JP11913183A JPS6010749A JP S6010749 A JPS6010749 A JP S6010749A JP 11913183 A JP11913183 A JP 11913183A JP 11913183 A JP11913183 A JP 11913183A JP S6010749 A JPS6010749 A JP S6010749A
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
master slice
wired
wiring region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11913183A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakamura
弘 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11913183A priority Critical patent/JPS6010749A/en
Publication of JPS6010749A publication Critical patent/JPS6010749A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To form the titled master slice integrated circuit with high density by a method wherein multiple types of wiring regions are provided. CONSTITUTION:Function block elements are arranged on a chip structure comprising cell rows with similar height and wiring regions 2, 3 with different height to be wired with one another. The part required of numerous wiring is wired in a wide wiring region while the part required of less wirings is wired in a narrow wiring region. In such a constitution, the overall chip space may be reduced to improve circuit integration. In other words, the circuit integration may be improved subject to conventional easy wiring process by means of providing the narrow wiring region with 1/2 time space and the wide wiring region with 1.3 times space.

Description

【発明の詳細な説明】 （１）発明の属する技術分野 本発明はマスタスライス集積回路に関し、特に配線領域
を複数種類埋め込んだ集積回路チップ構造に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a master slice integrated circuit, and more particularly to an integrated circuit chip structure in which a plurality of types of wiring regions are embedded.

（２）従来技術の説明 ディジタル集積回路の進歩に件い、チップに実現される
機能の集積度は著しく増大し、かつ多機能となっている
。更に集積回路は、その用途によシ汎用の標準集積回路
及び専用のカスタム集積回路に分化してきた。汎用の標
準集積回路は少品種大量生産という形態をとる。一方専
用のカスタム集積回路は、多品種、少量生産で従来の１
産体制では不適当である。しかしながら独自のメーカが
、そのメーカ固有の特色を有するシステムを作るために
、カスタム集積回路が適している。カスタム集積回路を
短期間にいかに効率よく作るかが、今日大きな課題にな
っている。その一つの方法としてマスタスライス方式が
ある。マスタスライス方式は、各集積回路に共通なトラ
ンジスタレベルの下地をあらかじめ作っておき、各集積
回路の個別機能を配線パターンを個有に作成することに
よって実現する方法である。マスクスライス集積回路は
第１図に示すようにトランジスタ領域（セル領域）と配
線領域は区別されている。従来配線領域の大きさは一種
類のみである。従って大規模集積回路を実現した場合、
配線領域をあらかじめ必要以上に大きく取っておく必要
があシ、チップの面積が大きくなるという欠点があった
。(2) Description of the Prior Art With the advancement of digital integrated circuits, the degree of integration of functions implemented on chips has increased significantly, and chips have become multifunctional. Furthermore, integrated circuits have been differentiated into general-purpose standard integrated circuits and specialized custom integrated circuits, depending on their use. General-purpose standard integrated circuits are produced in small quantities in large quantities. On the other hand, dedicated custom integrated circuits can be manufactured in a wide variety of products and in small quantities.
It is inappropriate for the production system. However, custom integrated circuits are suitable for unique manufacturers to create systems with features specific to that manufacturer. A major challenge today is how to efficiently produce custom integrated circuits in a short period of time. One method is the master slice method. The master slicing method is a method in which a transistor-level base common to each integrated circuit is created in advance, and individual functions of each integrated circuit are realized by creating individual wiring patterns. As shown in FIG. 1, a mask slice integrated circuit has a transistor region (cell region) and a wiring region separated. Conventionally, there is only one type of wiring area size. Therefore, when a large-scale integrated circuit is realized,
This has the disadvantage that it is necessary to reserve a wiring area larger than necessary in advance, and the area of the chip increases.

（３）発明の目的 本発明は配線領域を多種類設定し、高密度なマスタスラ
イス集積回路を実現できるようにした下地を提供するも
のである。(3) Object of the Invention The present invention provides a base that allows a high-density master slice integrated circuit to be realized by setting multiple types of wiring areas.

（４）発明の構成 本発明は、マスタスライス集積回路において、従来配線
領域が一種類のみに限定されていたため、多様なカスタ
ム集積回路に対して、配線容易性に欠けているという欠
点を、配線領域の種類を複数種類埋めこみ、配線密度が
高くなる部分を、より大きい配線領域にて配線し、配線
要求が少ない部分を、より小さい配線領域で配線可能な
よう意図して、作成した集積回路を特徴としている。(4) Structure of the Invention The present invention solves the problem of lack of ease of wiring for various custom integrated circuits, which was conventionally limited to only one type of wiring area in master slice integrated circuits. An integrated circuit is created by embedding multiple types of areas, with the intention that areas with high wiring density can be routed in a larger wiring area, and areas with less wiring requirements can be routed in a smaller wiring area. It is a feature.

（５）実施例 次に本発明の実施例について図面を参照して説明する０
第２図を参照すると、本発明の第１の実施例は、高さを
同一とするセル列１と高さの異なる配線領域２と３とを
含む。第３図を参照すると第２図のようなチップ構造に
対してファンクシ四ン・ブロック素子を配置し、各素子
間を配線している。配線要求が多い部分は広い配線領域
内で配線し、配線要求が少ない部分は狭い配線領域内で
配線している。(5) Examples Next, examples of the present invention will be explained with reference to the drawings.
Referring to FIG. 2, the first embodiment of the present invention includes a cell column 1 having the same height and wiring regions 2 and 3 having different heights. Referring to FIG. 3, four function block elements are arranged in the chip structure as shown in FIG. 2, and wiring is provided between each element. Portions with high wiring requirements are routed within a wide wiring area, and areas with low wiring requirements are routed within a narrow wiring area.

本発明で説明した構成を取った場合、全体的にチア１面
積が小さくなり、高集積化可能である。When the configuration described in the present invention is adopted, the overall area of the chia 1 is reduced, and high integration is possible.

１種類のみ配線領域を限定すると、その配線領域を、配
線容易性を考慮して設定するために、太きく取る必要が
ある。本発明では小さい配線領域を従来の半分に、大き
い方の配線領域を従来の１．３倍に設定することにより
、配線容易性を保ったままで、集積度を高めることがで
きる。If only one type of wiring area is limited, the wiring area needs to be set thick in consideration of ease of wiring. In the present invention, by setting the small wiring area to half the conventional size and setting the large wiring area to 1.3 times the conventional size, it is possible to increase the degree of integration while maintaining the ease of wiring.

（６）発明の効果 本発明は以上説明したように、マスタスライス集積回路
において、配線領域の大きさを複数理め込む構成を取る
ことにより、配線領域の有効利用及び、集積度を高める
ことができる効果がある。(6) Effects of the Invention As explained above, the present invention makes it possible to effectively utilize the wiring area and increase the degree of integration by adopting a configuration in which multiple wiring area sizes are incorporated in the master slice integrated circuit. There is an effect that can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のマスタスライス集積回路で、配　１線領
域の大きさは１種類の例、第２図は本発明の実施例で配
線領域の種類が２種類の例、第３図は配置配線の実施例
を部分的に示したもの、である０なお図において、１・
・・・・・セル領域、２・・・・・・配線領域、である
。 ５− ２　／　図 鱈　２　図 冥３図Figure 1 shows an example of a conventional master slice integrated circuit in which the size of one wiring area is one type, Figure 2 is an example of an embodiment of the present invention with two types of wiring area, and Figure 3 shows an example of the layout. This is a partial illustration of an example of wiring.In the figure, 1.
. . . cell area, 2 . . . wiring area. 5-2 / Figure cod 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] マスタスライスＬＳＩにおいて、大きさの異なる配線領
域を複数理め込んだことを特徴とする集積回路。An integrated circuit characterized in that a master slice LSI includes a plurality of wiring areas of different sizes.
JP11913183A 1983-06-30 1983-06-30 Master slice integrated circuit Pending JPS6010749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11913183A JPS6010749A (en) 1983-06-30 1983-06-30 Master slice integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11913183A JPS6010749A (en) 1983-06-30 1983-06-30 Master slice integrated circuit

Publications (1)

Publication Number Publication Date
JPS6010749A true JPS6010749A (en) 1985-01-19

Family

ID=14753702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11913183A Pending JPS6010749A (en) 1983-06-30 1983-06-30 Master slice integrated circuit

Country Status (1)

Country Link
JP (1) JPS6010749A (en)

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