JPS6010665A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6010665A JPS6010665A JP58119609A JP11960983A JPS6010665A JP S6010665 A JPS6010665 A JP S6010665A JP 58119609 A JP58119609 A JP 58119609A JP 11960983 A JP11960983 A JP 11960983A JP S6010665 A JPS6010665 A JP S6010665A
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- current value
- nicr
- semiconductor device
- programming current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体装置に係り、特に小さなチップ面積
においてヒユーズの切断電流値をモニタできるようにし
たヒユーズ型ＦＲＯＭに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a fuse type FROMM that is capable of monitoring the cutting current value of a fuse in a small chip area.
従−来、この種のヒユーズ型ＦＲＯＭとして第１図に示
すものがあった。この図において、１はヒＩＩ）
ユーズとしてＮ ｉ Ｃｒヒユーズを用いたメモリを含
む動作回路部、２はアルミ配線からなる電極取出シ用バ
ンド、３はＮｉＣｒヒユーズのプログラミング電流値を
モニタするためのパターンであり、これらはウェハチッ
プ４上に形成されている。Conventionally, there has been a fuse-type FROM of this type as shown in FIG. In this figure, 1 is an operating circuit section including a memory using a NiCr fuse as a user, 2 is an electrode extraction band made of aluminum wiring, and 3 is a band for monitoring the programming current value of the NiCr fuse. These patterns are formed on the wafer chip 4.
ＮｉＣｒヒユーズ型ＦＲＯＭはメモリ部がＮｌＣｒヒユ
ーズで構成されており、書き込みはこのＮｉ Ｃｒヒユ
ー スに一定電流を流し、ＮｉＣｒヒユーズ’＆切断す
ることにより行っている。The memory section of the NiCr fuse type FROM is composed of an NlCr fuse, and writing is performed by passing a constant current through the NiCr fuse and cutting the NiCr fuse.
メモリ部に用いられるＮｉＣｒヒユーズの特性としては
、次の２項目が必須条件である。The following two items are essential characteristics of the NiCr fuse used in the memory section.
（１）一定の書き込み条件でプログラミングできるよ５
に、一定電流にてＮｉＣｒヒユーズか切断されること。(1) Programming can be done under certain writing conditions5
The NiCr fuse must be disconnected using a constant current.
（２）使用中の動作電流によっては、Ｎ ｉ Ｃｒヒユ
ーズが切断されないこと。(2) The N i Cr fuse will not be disconnected depending on the operating current during use.
これらの２点が各ウェハチップ４で満されているかどう
かチェックするために、第１図に示したモニタ用のパタ
ーン３が備えられている、従来のＮ ｉ Ｃｒヒユーズ
型ＦＲＯＭは以上のよう（２）
に構成されているので、モニタ用のパターン３を入れる
ための面積がウェハチップ４上に必要となり、チップ面
積が大きくなるという欠点があった。In order to check whether these two points are satisfied in each wafer chip 4, the conventional N i Cr fuse type FROM is provided with the monitor pattern 3 shown in FIG. 2) Since the structure is as follows, an area is required on the wafer chip 4 to accommodate the monitor pattern 3, resulting in a disadvantage that the chip area becomes large.
この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、ウェハチップ上に形成するアル
ミ配線の電極取出し用パッド間にＮｉＣｒヒユーズを接
続することにより、小さなチップ面積でＮｉＣｒヒユー
ズの切断電流値をモニタできるようにした半導体装置ケ
提供することを目的としている。以下この発明の一実施
例な図面について説明する。This invention was made in order to eliminate the drawbacks of the conventional products as described above, and by connecting a NiCr fuse between electrode lead-out pads of aluminum wiring formed on a wafer chip, NiCr can be produced in a small chip area. The object of the present invention is to provide a semiconductor device that can monitor the cutting current value of a fuse. DESCRIPTION OF THE PREFERRED EMBODIMENTS The drawings representing one embodiment of the present invention will be described below.
第２図はこの発明の一実施例を示す半導体装置の平面図
である。この図において、５は前記電極取出し用パッド
２間にそれぞれ形成されたプログラミング電流値を検知
するＮｉＣｒヒユーズ、６は前記ＮｉＣｒヒユーズ５ビ
アルミ配線の電極取出し用パッド２にそれぞれ接続する
ためのアルミ配線である。FIG. 2 is a plan view of a semiconductor device showing an embodiment of the present invention. In this figure, 5 is a NiCr fuse formed between the electrode lead-out pads 2 to detect the programming current value, and 6 is an aluminum wire for connecting the NiCr fuse 5 to the electrode lead-out pad 2 of the via aluminum wiring. be.
上記のように、この発明による半導体装置は、アルミ配
線の電極取出し用パッド２間にメモリ用のものと同等な
Ｎ ｉ Ｃｒヒユーズ５が形成されているので、このＮ
ｉＣｒヒユーズ５の切断電流を測定することにより、プ
ログラミング電流値を測定できる。As described above, in the semiconductor device according to the present invention, the N i Cr fuse 5, which is equivalent to that for memory, is formed between the electrode lead-out pads 2 of the aluminum wiring.
By measuring the cutting current of the iCr fuse 5, the programming current value can be measured.
なお、電極取出し用パッド２間に形成されたＮ ｉ Ｃ
ｒヒユーズ５は、製品出荷前にすべて切断されるため、
電極取出し用パッド２間は電気的には絶縁状態であり、
動作時には悪影響を与えることはない。なお、ＮｉＣｒ
ヒユーズ５は一般には他のヒユーズであってもよい。Note that the NiC formed between the electrode extraction pads 2
All fuses 5 are cut before shipping the product, so
The electrode extraction pads 2 are electrically insulated,
There is no adverse effect during operation. In addition, NiCr
Fuse 5 may generally be another fuse.
以上説明したように、この発明によれば、プログラミン
グ電流値を検知するヒユーズをアルミ配線の電極取出し
用バンドにそれぞれ形成したので、チップ面積が小さく
なるとともに、精度の高いデータが得られるという効果
がある。As explained above, according to the present invention, the fuses for detecting the programming current value are formed in the electrode extraction bands of the aluminum wiring, so that the chip area is reduced and highly accurate data can be obtained. be.
第１図は従来の半導体装置の平面図、第２図はこの発明
の一実施例を示す半導体装置の平面図である。
図中、１は動作回路部、２は電極取出し用パッド、４は
ウェハチップ、５はＮ ｉ Ｃｒヒユーズ、６はＮ ｉ
Ｃｒヒユーズを電極取出し用パッドに接続するアルミ
配線である。
代理人 大 岩増雄 （外２名）
第１図
第２図FIG. 1 is a plan view of a conventional semiconductor device, and FIG. 2 is a plan view of a semiconductor device showing an embodiment of the present invention. In the figure, 1 is an operating circuit section, 2 is an electrode extraction pad, 4 is a wafer chip, 5 is a NiCr fuse, and 6 is a Ni
This is an aluminum wiring that connects the Cr fuse to the electrode extraction pad. Agent: Masuo Oiwa (2 others) Figure 1 Figure 2
Claims (1)
路部と、所要数の電極取出し用バンドと、プログラミン
グ電流値を検知するヒユーズとを備え、前記ヒユーズに
一定電流を流してこれを切断し前記メモリにプログラム
の書き込みを行うヒユーズ型ＦＲＯＭにおいて、前記各
電極取出し用パッド間にそれぞれプログラミング電流値
を検知するヒユーズを接続したこと”ｋ％徴とする半導
体装置。It is equipped with an operation circuit section including a memory equipped with a fuse on a wafer chip, a required number of electrode extraction bands, and a fuse for detecting a programming current value. 1. A semiconductor device characterized in that a fuse-type FROM is used to write a program into a memory, and a fuse for detecting a programming current value is connected between each of the electrode lead-out pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119609A JPS6010665A (en) | 1983-06-29 | 1983-06-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119609A JPS6010665A (en) | 1983-06-29 | 1983-06-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6010665A true JPS6010665A (en) | 1985-01-19 |
Family
ID=14765644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58119609A Pending JPS6010665A (en) | 1983-06-29 | 1983-06-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010665A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5788855A (en) * | 1995-05-04 | 1998-08-04 | Intel Corporation | Method of producing circuit board |
| CN104112730A (en) * | 2013-06-09 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module and manufacturing method thereof |
-
1983
- 1983-06-29 JP JP58119609A patent/JPS6010665A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5788855A (en) * | 1995-05-04 | 1998-08-04 | Intel Corporation | Method of producing circuit board |
| CN104112730A (en) * | 2013-06-09 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module and manufacturing method thereof |
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