JP2743457B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2743457B2 JP2743457B2 JP10503889A JP10503889A JP2743457B2 JP 2743457 B2 JP2743457 B2 JP 2743457B2 JP 10503889 A JP10503889 A JP 10503889A JP 10503889 A JP10503889 A JP 10503889A JP 2743457 B2 JP2743457 B2 JP 2743457B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- power supply
- semiconductor device
- fuse
- supply terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、テスト時に、過電流により、ヒューズ切断
を行ない、内部状態を選択させる機能を持った半導体装
置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a function of cutting a fuse by an overcurrent during a test and selecting an internal state.
従来のヒューズ切断機能を有する半導体装置は、第３
図Ａに示す様に、ヒューズ端子と電源端子間に過電流を
加える場合、１つの電源端子に対して、複数のヒューズ
端子を設け、各々のヒューズ端子を溶断していた。第３
図Ｂに、ヒューズ端子の回路例を示す。ヒューズ切断に
は、通常の端子の数百倍の電流が一瞬流れ、抵抗とその
電流により発生した熱によって、９が溶断する。A conventional semiconductor device having a fuse cutting function is the third type.
As shown in FIG. A, when an overcurrent is applied between a fuse terminal and a power supply terminal, a plurality of fuse terminals are provided for one power supply terminal, and each fuse terminal is blown. Third
FIG. B shows a circuit example of the fuse terminal. In cutting the fuse, a current several hundred times larger than that of a normal terminal flows for an instant, and the resistor 9 and the heat generated by the current blow the fuse 9.
ところが第３図Ａの様に複数のヒューズを有する半導
体装置の場合、各々のヒューズには１度ずつしか過電流
は流れないが、２の電源端子には、ヒューズの溶断の数
だけ、過電流が流れる可能性がある。半導体装置のテス
ト時には、端子接触用の針が付いたプロービングカード
を用いるが、その針先は、約100μ角の端子に当てるた
め、それ以下の太さの細いものである。この針先は、摩
擦、熱筆などにより摩耗してしまう。上記説明の電源端
子においては、通常の端子に比べ、回数が多く過電流が
流れるので（ヒューズ端子１ chip １回、電源端子１
chip １回流れる）、熱の発生、針先の酸化等が起こ
りやすく通常の端子に比べ針先の摩耗するスピードが急
激に速くなる。もしそのままテストを続けた場合、電源
端子の針当たりが悪くなり良品のチップを不良品と判定
してしまったり、プロービングカードの交換洗浄等を、
多くやらなければならない、交換回数が増加すると、人
の手間、テストの中断等が発生し、テスト時間の延長、
またはプロービングカードの購入等の費用が発生し、テ
ストィングコストが増加してしまう等の問題があった。However, in the case of a semiconductor device having a plurality of fuses as shown in FIG. 3A, overcurrent flows through each fuse only once, but the number of overcurrents in the two power terminals is equal to the number of blown fuses. May flow. When testing a semiconductor device, a probing card with a terminal contact needle is used, and the tip of the probe is thinner than that, because it touches a terminal of about 100 μ square. The needle tip is worn by friction, a hot brush and the like. In the power supply terminal described above, an overcurrent flows more frequently than a normal terminal (the fuse terminal 1 chip once, the power supply terminal 1
chip flows once), heat is generated, and the tip is oxidized easily, and the speed at which the tip is worn rapidly increases as compared with a normal terminal. If the test is continued as it is, the contact of the power supply terminal will become worse, and a good chip will be judged as a defective product.
If you have to do a lot, and the number of replacements increases, labor and testing will be interrupted.
Alternatively, there is a problem that a cost for purchasing a probing card or the like is generated and a testing cost is increased.
そこで本発明の半導体装置は、以上の様な問題点を解
決するもので、その目的とするところは、プロービング
カードの針先の摩耗を減らし、テストの信頼性を向上
し、テスト時間の短縮を計り、テスティングコストの低
下をもたらす事を目的としている。Therefore, the semiconductor device of the present invention solves the above problems, and its purpose is to reduce the wear of the probe tip of the probing card, improve the test reliability, and shorten the test time. The purpose is to bring down the cost of measuring and testing.
本発明の半導体装置は、過電流により溶断可能な導電
体を備えた半導体装置において、前記溶断可能な導電体
に過電流を流すための一対の端子が前記半導体装置の電
源端子とは別に設けられ、前記一対の端子は隣接して配
置されていることを特徴とする。In a semiconductor device according to the present invention, a pair of terminals for supplying an overcurrent to the fusible conductor is provided separately from a power supply terminal of the semiconductor device. The pair of terminals are arranged adjacent to each other.
第１図に、本発明の半導体装置の一実施例を示す。１
は半導体チップを示し、２は、電源端子を示し３は、ヒ
ューズ端子を示している。２の電源端子は、テスト時に
は、内部回路のファンクション試験や、DC特性、AC特性
等を測定する時に使用される。４は本発明の追加された
電源端子を示している。他の端子は、通常の入出力端子
及び、過電流のかからない方の電源端子を示している。FIG. 1 shows an embodiment of the semiconductor device of the present invention. 1
Indicates a semiconductor chip, 2 indicates a power supply terminal, and 3 indicates a fuse terminal. The second power supply terminal is used for a function test of an internal circuit, a DC characteristic, an AC characteristic, and the like during a test. Reference numeral 4 denotes an additional power supply terminal of the present invention. Other terminals indicate a normal input / output terminal and a power supply terminal to which an overcurrent is not applied.
ヒューズ切断時には、４の複数の電源端子とヒューズ
端子との間に過電流を流す事になる。４の複数の電源端
子と２の電源端子は、内部電源配線により接続されてい
る。第２図は本発明の半導体装置の実使用状態でのボン
ディングレイアウトを示すもので、４の電源端子はボン
ディングされず使用されていない事がわかる。すなわち
本実施例では、過電流の加わる電源端子が３ヶ存在する
ので、１つの電源端子に加わる過電流は1/3になる訳で
あり、プロービングカードの針先は単純に、従来の３倍
長持ちする事になる。また、２の電源端子は、過電流が
かからないので、針先の摩耗は通常の端子と同一であ
り、テスト時、針当りの悪さに起因した、ファンクショ
ン不良等の数が減少する。When the fuse is cut, an overcurrent flows between the plurality of power supply terminals 4 and the fuse terminal. The plurality of power terminals 4 and the power terminal 2 are connected by an internal power line. FIG. 2 shows a bonding layout of the semiconductor device of the present invention in an actual use state. It can be seen that the power supply terminal 4 is not bonded and is not used. That is, in the present embodiment, there are three power supply terminals to which an overcurrent is applied, so that the overcurrent applied to one power supply terminal is reduced to 1/3, and the probe tip of the probing card is simply three times the conventional one. Will last longer. Further, since no overcurrent is applied to the second power supply terminal, the wear of the needle tip is the same as that of a normal terminal, and the number of function failures and the like due to poor contact with the needle during a test is reduced.
第４図にも本発明の実施例をしめしている。この例の
場合、３のヒューズ端子各々の隣りあるいは、近辺に、
４の電源端子が配置されている。ヒューズ切断時には、
ヒューズ端子と、隣りあるいは近辺の電源端子間にの
み、過電流を印加する。この様にすれば、第１図の実施
例に比較して印加する電源端子とヒューズ端子の距離が
短いので内部の配線抵抗が極めて低くなり、印加する過
電流が少なくても、ヒューズ溶断が容易となる。したが
って本実施例では、第１図の実施例の効果プラス、プロ
ービングカード針先の熱量の低減の効果もあるので、第
１図の実施例よりも、針先を長持ちさせる事が可能であ
る。FIG. 4 also shows an embodiment of the present invention. In this example, next to or near each of the three fuse terminals,
Four power terminals are arranged. When cutting the fuse,
Overcurrent is applied only between the fuse terminal and an adjacent or nearby power supply terminal. In this case, the distance between the power supply terminal and the fuse terminal to be applied is shorter than that in the embodiment of FIG. 1, so that the internal wiring resistance becomes extremely low. Becomes Therefore, in this embodiment, the effect of the embodiment of FIG. 1 is added, and the effect of reducing the calorific value of the probing card stylus is also provided, so that the stylus can be made to last longer than the embodiment of FIG.
以上の様に本発明の半導体装置を使用すれば、たとえ
ば、プロービングカードを用いて溶断を行うとすると、
プロービングカード針先に加わる、過電流の回数の減
少、過電流低減による熱量の減少の効果を有するので、
針先の摩耗するスピードが従来に較べ極端に遅くなり、
針先が長持ちする効果を有する。したがって従来、針当
りの悪さに起因した不良品の発生が減少、プローピング
カードの交換洗浄等によるテストの中断が減少、プロー
ビングカードの購入費用の減少、等の効果を有するの
で、テストの信頼性を向上、テスト時間の短縮、テスト
コストの低下をもたらす事が可能である。If the semiconductor device of the present invention is used as described above, for example, if fusing is performed using a probing card,
Since it has the effect of reducing the number of overcurrents added to the probing card needlepoint and reducing the amount of heat by reducing the overcurrent
The speed at which the needle tip wears is extremely slower than before,
It has the effect that the needle tip lasts longer. Therefore, it has the effect of reducing the occurrence of defective products due to poor contact with the needle, reducing the interruption of the test due to replacement cleaning of the probing card, and reducing the purchasing cost of the probing card. Can improve test time, reduce test time, and reduce test cost.
第１図は本発明の構成を特徴とする半導体装置の実施例
を表わす図。 第２図は本発明の構成を特徴とする半導体装置の実使用
状態におけるボンディングレイアウトを示した図。 第３図Ａは従来の半導体装置の構成を表わす図。 第３図Ｂは、一般に使用されるヒューズ端子の回路例を
表わす図。 第４図Ａは本発明の構成を特徴とする半導体装置の実施
例を表わす図（ヒューズ端子と電源端子が対になってい
る。）。 第４図Ｂは，第４図Ａの半導体装置の実使用状態におけ
るボンディングレイアウトを示した図。 １……半導体チップ ２……内部回路用電源端子 ３……ヒューズ用端子 ４……ヒューズ切断用電源端子 ５……ボンディングワイヤー ６……電源端子（GND） ７……ヒューズ端子 ８……電源端子（プラス電位VD） ９……ヒューズ用半導体 10……プルアップ用Pch Mosトランジスタ 11……半導体内部回路 12……通常の入出力端子及び電源端子 13……擬似的なリードフレーム枠FIG. 1 is a diagram showing an embodiment of a semiconductor device characterized by the configuration of the present invention. FIG. 2 is a diagram showing a bonding layout in a practical use state of a semiconductor device characterized by the configuration of the present invention. FIG. 3A is a diagram showing a configuration of a conventional semiconductor device. FIG. 3B is a diagram showing a circuit example of a commonly used fuse terminal. FIG. 4A is a diagram showing an embodiment of a semiconductor device characterized by the configuration of the present invention (a fuse terminal and a power supply terminal are paired). FIG. 4B is a diagram showing a bonding layout in an actual use state of the semiconductor device of FIG. 4A. DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Power supply terminal for internal circuit 3 ... Terminal for fuse 4 ... Power supply terminal for fuse cutting 5 ... Bonding wire 6 ... Power supply terminal (GND) 7 ... Fuse terminal 8 ... Power supply terminal (Positive potential VD) 9: semiconductor for fuse 10: Pch Mos transistor for pull-up 11: semiconductor internal circuit 12: normal input / output terminal and power supply terminal 13: pseudo lead frame frame
Claims (1)
導体装置において、 前記溶断可能な導電体に過電流を流すための一対の端子
が前記半導体装置の電源端子とは別に設けられ、前記一
対の端子は隣接して配置されていることを特徴とする半
導体装置。1. A semiconductor device provided with a conductor which can be blown by an overcurrent, wherein a pair of terminals for flowing an overcurrent to the blowable conductor are provided separately from a power supply terminal of the semiconductor device. A semiconductor device, wherein a pair of terminals are arranged adjacent to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10503889A JP2743457B2 (en) | 1989-04-25 | 1989-04-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10503889A JP2743457B2 (en) | 1989-04-25 | 1989-04-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02283051A JPH02283051A (en) | 1990-11-20 |
| JP2743457B2 true JP2743457B2 (en) | 1998-04-22 |
Family
ID=14396839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10503889A Expired - Fee Related JP2743457B2 (en) | 1989-04-25 | 1989-04-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2743457B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669473A (en) * | 1992-08-20 | 1994-03-11 | Matsushita Electron Corp | Master slice lsi chip |
| JP2009053970A (en) | 2007-08-28 | 2009-03-12 | Toshiba Corp | Semiconductor device |
| JP5592970B2 (en) * | 2013-04-18 | 2014-09-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of fusing semiconductor device |
-
1989
- 1989-04-25 JP JP10503889A patent/JP2743457B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02283051A (en) | 1990-11-20 |
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