JPS60106205A - Monolithic fet oscillator - Google Patents

Monolithic fet oscillator

Info

Publication number
JPS60106205A
JPS60106205A JP21444983A JP21444983A JPS60106205A JP S60106205 A JPS60106205 A JP S60106205A JP 21444983 A JP21444983 A JP 21444983A JP 21444983 A JP21444983 A JP 21444983A JP S60106205 A JPS60106205 A JP S60106205A
Authority
JP
Japan
Prior art keywords
line
conductor
slot
conductors
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21444983A
Other languages
Japanese (ja)
Inventor
Tetsuo Hirota
哲夫 廣田
Hirotsugu Ogawa
博世 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP21444983A priority Critical patent/JPS60106205A/en
Publication of JPS60106205A publication Critical patent/JPS60106205A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/18Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
    • H03B5/1841Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator
    • H03B5/1847Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device
    • H03B5/1852Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device the semiconductor device being a field-effect device

Landscapes

  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

PURPOSE:To facilitate mass production, to omit a filter and to attain size reduction by forming a passive circuit and a field-effect transistor FET on the same substrate, and using a slot line. CONSTITUTION:The FET22 is formed on the semiconductor substrate 21 and conductors 26-28 connected to the gate electrode 23, drain electrode 24, and source electrode 25 of the FET22 are formed on the substrate 21. Further, the conductors 26 and 27 form a slot line 29 and the conductors 27 and 28 form a slot line 31 respectively. The line 29 is terminated in an open state at a position of finite length from the FET22 and terminated by a capacitor 32, and the line 31 is an output line. Therefore, the size and position are determined easily with high precision, the mass production is facilitated, and the size is reduced.

Description

【発明の詳細な説明】 この発明はFET (電界効果トランジスタ)を能動素
子としてモノリシック集積回路化され、マイクロ波およ
びミリ波などの発振に適するモノリシックFET発振器
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic FET oscillator which is formed into a monolithically integrated circuit using FET (field effect transistor) as an active element and is suitable for oscillation of microwaves, millimeter waves, and the like.

〈従来技術〉 第1図及び第2図は従来のハイブリッド集積回路化され
たFET発振器の例を示す。接地導体1の上に誘電体基
板2,3が設けられ、誘電体基板2゜3上にマイクロス
トリップ線路4,5、これに一端が接続されたマイクロ
ストリップの高周波阻止フィルタ6.7、そのフィルタ
の他端に接続された直流印加端子8,9などの受動回路
が形成されている。誘電体基板2,3間の接地導体1に
FETテップ11が搭載され、金属線12 、13によ
、!l) FETチップ11の電極とマイクロストリッ
プ線路4,5とが接続されている。
<Prior Art> FIGS. 1 and 2 show an example of a conventional FET oscillator formed into a hybrid integrated circuit. Dielectric substrates 2 and 3 are provided on the ground conductor 1, microstrip lines 4 and 5 are provided on the dielectric substrate 2.3, a microstrip high frequency blocking filter 6 and 7 having one end connected thereto, and the filter. Passive circuits such as DC application terminals 8 and 9 connected to the other end are formed. A FET tip 11 is mounted on the ground conductor 1 between the dielectric substrates 2 and 3, and is connected to the metal wires 12 and 13! l) The electrodes of the FET chip 11 and the microstrip lines 4 and 5 are connected.

この従来の発振器においてはFETチップ11の取りつ
け位置、金属線12 、13の長さ、金属線12 、1
3の接続位置々と製作精度を確保するのが困難な部分が
多く、このため回路組立後の調整が可可欠であるという
欠点があった。さらに、直流バイアスを供給するために
高周波阻止フィルタ6.7を必要とし、回路が大形化す
るという欠点もあった。
In this conventional oscillator, the mounting position of the FET chip 11, the length of the metal wires 12 and 13, and the length of the metal wires 12 and 1
There are many parts where it is difficult to ensure the connection positions and manufacturing accuracy of No. 3, and therefore adjustments after circuit assembly are necessary. Furthermore, a high frequency blocking filter 6.7 is required to supply a DC bias, resulting in an increase in the size of the circuit.

〈発明の概要〉 この発明の目的は比較的高い寸法2位置績度を容易に得
ることができ、しかも製造か容易で量産し易く、小形に
作ることができるモノリフツクFET発振器を提供する
ことにある。
<Summary of the Invention> An object of the present invention is to provide a monolift FET oscillator that can easily obtain relatively high dimensional two-position performance, is easy to manufacture, is easy to mass-produce, and can be made small. .

この発明によれば半導体基板上にFETを形成し、その
FETを形成した半導体基板上にスロット線路によりF
ETを含む発振回路を形成する。
According to this invention, an FET is formed on a semiconductor substrate, and an FET is formed on the semiconductor substrate on which the FET is formed by a slot line.
Form an oscillation circuit including ET.

〈実施例〉 第3図及び第4図はこの発明の実施例を示し、半導体基
板21上にFET 22が形成される。FET 22の
ゲート電極23.ドレイン電極24及びノース電、極2
5とそれぞれ接続された導体26 、27及び28がそ
れぞれ半導体基板21上に形成される。導体26及び2
7によりスロット線路29が構成され、導体27及び2
8によりスロット線路31が構成される。スロット線路
29のFET22と反対側の端はキャパシタ32で終端
される。即ちスロット線路31のこの端部はそのスロッ
ト線路を構成する両側の導体26 、27が絶縁fTg
E33を介して重ね合わされてキャパシタ32がft’
4 成すれる。同様々キャパシタ34によりスロット線
路31ヲ構成する一方の導体27はそのドレイン電極2
4側27aと出力ボート35側27bとて直流的に分離
される。導体26 、27及び28にそれぞれFET 
22に対する直流バイアス印加端子36 、37及び3
8が接続される。
<Embodiment> FIGS. 3 and 4 show an embodiment of the present invention, in which an FET 22 is formed on a semiconductor substrate 21. In FIG. Gate electrode 23 of FET 22. Drain electrode 24 and north electrode, pole 2
Conductors 26, 27 and 28 connected to the semiconductor substrate 21 are formed on the semiconductor substrate 21, respectively. conductors 26 and 2
7 constitutes a slot line 29, and the conductors 27 and 2
8 constitutes a slot line 31. The end of the slot line 29 opposite to the FET 22 is terminated with a capacitor 32. That is, at this end of the slot line 31, the conductors 26 and 27 on both sides constituting the slot line are insulated fTg.
The capacitor 32 is ft'
4 It will be accomplished. Similarly, one conductor 27 constituting the slot line 31 by the capacitor 34 has its drain electrode 2.
The 4 side 27a and the output boat 35 side 27b are separated in terms of direct current. FETs on conductors 26, 27 and 28, respectively
DC bias application terminals 36, 37 and 3 for 22
8 is connected.

ここで、FET22からスロット線路29をみたインピ
ーダンスが誘導性となる位置にキャパシタ32をおけば
発振条件が満たされ、スロット線路31より出力ポート
35だ発振出力が得られる。この発振の原理は第1図及
び第2図に示した従来の発振器と同一である。なお、ス
ロット線路29は、キャパシタ32で終端する代わりに
、適当な長さで開放終端してもよい。高周波電界はスロ
ット線路29 、31の近傍に集中するため、直流バイ
アス印加端子36〜38をスロット線路28.31から
離して各導体に接続することにより高周波阻止用フィル
タは不要となる。
Here, if the capacitor 32 is placed at a position where the impedance seen from the FET 22 to the slot line 29 becomes inductive, the oscillation condition is satisfied, and an oscillation output can be obtained from the slot line 31 to the output port 35. The principle of this oscillation is the same as that of the conventional oscillator shown in FIGS. 1 and 2. Note that instead of terminating with the capacitor 32, the slot line 29 may have an open termination with an appropriate length. Since the high frequency electric field is concentrated in the vicinity of the slot lines 29 and 31, a high frequency blocking filter is not required by connecting the DC bias application terminals 36 to 38 to each conductor apart from the slot lines 28 and 31.

第5図、第6図はこの発明の第2の実施例を示し、第2
高調波を取り出す発振器である。第3図及び第4図に示
したものと同様の構造をもつ2個の発振回路41 、4
2が同一半導体基板21上に対称に配置される。発振回
路41の第3図、第4図と対応する部分には同一符号を
付け、発振回路42の対応する部分には同一番号にダッ
シュ「′」を付けである。スロット線路29 、29’
 を対向平行させ、スロット線路31 、31’ も同
様に対向平行させ、ド1/イン?[1,極24 、24
’ と接続された導体27 、27’は共通の導体どさ
れである。スロット線路31 、31’ )FET 2
2 、22’と反対側はコプレーナ線路43の一端に接
続される。コプレーナ線路43も半導体基板21上に形
成され、コプレーナ線路43の内導体43aに、スロッ
ト線路31 、31’ 肌の導体27が延長接h;され
、コプレーナ線路43の両側の外導体は導体28 、2
8’が延長して形成される。スロット線路31 、31
’とコプレーナ線路43との接続部において、コプレー
ナ線路43の両側の外導体28 、28’が短絡導体4
4で接続される。
FIG. 5 and FIG. 6 show a second embodiment of the present invention.
This is an oscillator that extracts harmonics. Two oscillation circuits 41, 4 having a structure similar to that shown in FIGS. 3 and 4
2 are arranged symmetrically on the same semiconductor substrate 21. Parts of the oscillation circuit 41 that correspond to those in FIGS. 3 and 4 are given the same reference numerals, and corresponding parts of the oscillation circuit 42 are given the same numbers and a dash "'". Slot lines 29, 29'
are parallel to each other, and the slot lines 31 and 31' are also made to be parallel to each other in the same way. [1, pole 24, 24
The conductors 27 and 27' connected to ' are a common conductor. Slot line 31, 31') FET 2
2 and 22' are connected to one end of a coplanar line 43. The coplanar line 43 is also formed on the semiconductor substrate 21, and the slot lines 31, 31' skin conductors 27 are extended to the inner conductor 43a of the coplanar line 43, and the outer conductors on both sides of the coplanar line 43 are the conductors 28, 2
8' is extended. Slot lines 31, 31
At the connection between the outer conductor 28 and the coplanar line 43, the outer conductors 28 and 28' on both sides of the coplanar line 43 are connected to the short-circuit conductor 4.
Connected at 4.

ここで、スロット線路31 、31’の長さを適当に選
べば、第5図に電界の向きを矢印で示すように2つの発
振回路41 、42の出力は互いに逆相で同期し、出力
波のうち基本周波数成分は短絡導体44により短絡され
、出力線路のコプレーナ線路43へは現れない。一方、
第2高調波成分は互いに同相になるためコプレーナ線路
43よシ出力ポート35に取りだすことができる。
Here, if the lengths of the slot lines 31 and 31' are appropriately selected, the outputs of the two oscillation circuits 41 and 42 will be synchronized in opposite phases to each other, as shown by the arrows indicating the direction of the electric field in FIG. Among them, the fundamental frequency component is short-circuited by the short-circuit conductor 44 and does not appear on the coplanar line 43 of the output line. on the other hand,
Since the second harmonic components are in phase with each other, they can be extracted from the coplanar line 43 to the output port 35.

これらの実施例においては、スロット線路を用いること
によ、!2 FETと受動回路を接続するワイヤがなく
、また高周波耐重のだめのフィルタが不要であるため、
再現性が良好であるとともに極めて小形に作ることがで
きる。
In these embodiments, by using slot lines! 2. There are no wires to connect the FET and passive circuit, and there is no need for a high-frequency heavy-duty filter.
It has good reproducibility and can be made extremely small.

〈効 果〉 以上説明したように、この発明の発振器においては受動
回路とFETを同一半導体基板上に形成し、かつスロッ
ト線路を用いているため、量産性尾富むとともにフィル
タを省略でき回路寸法を小形化できる利点がある。
<Effects> As explained above, in the oscillator of the present invention, the passive circuit and the FET are formed on the same semiconductor substrate, and the slot line is used, so it is easy to mass produce, and the filter can be omitted, reducing the circuit size. It has the advantage of being compact.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のFET発振器を示す平面図、第2図は第
1図の正面図、第3図はこの発明の第1の実施例を示す
平面図、第4図は第3図のAA’線断面図、第5図はこ
の発明の第2の実施例を示す平面図、第6図は第5図の
BB’線断面図である。 21・半導体基板、22−FET、 23・・ゲート電
極、24・・トレイン電極、25・・ソース電極、26
 、27 、28・・導体、29 、31・・・スロッ
ト線路、32 、34・・キャパシタ、35・・・出力
ボート、36 、37 、38−・バイアス印加端子、
41 、42−発振回路、43 コプレーナ線路、44
・・・短絡導体。 特許出願人 日本電信電話公社 代理人 草野 卓 布 1 (支) オ 2 臣 11 1 オ 3圓 7 汗4囮 沙 5図 十 〇 図
FIG. 1 is a plan view showing a conventional FET oscillator, FIG. 2 is a front view of FIG. 1, FIG. 3 is a plan view showing a first embodiment of the present invention, and FIG. 5 is a plan view showing a second embodiment of the present invention, and FIG. 6 is a sectional view taken along the line BB' in FIG. 21. Semiconductor substrate, 22-FET, 23.. Gate electrode, 24.. Train electrode, 25.. Source electrode, 26
, 27, 28...Conductor, 29, 31...Slot line, 32, 34...Capacitor, 35...Output port, 36, 37, 38--Bias application terminal,
41, 42-oscillation circuit, 43 coplanar line, 44
...Short conductor. Patent Applicant Nippon Telegraph and Telephone Public Corporation Agent Takufu Kusano 1 (branch) O 2 Omi 11 1 O 3 En 7 Kan 4 Yoshisa 5 Figure 10 〇 Figure

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上KFETC電界効果トランジスタ)
が形成され、そのFETのゲート電極を、ドレイン電極
及びソース電極とそれぞれ接続された第1、第2.及び
第3の導体が上記半導体基板上に形成され、これら第1
の導体と第2の導体とによシ第1のスロット線路が構成
され、第2の導体と第3の導体とにより第2のスロッ)
 Kl路が構成され、上記第1のスロット線路は上記F
ETから有限長の位置で開放終端、あるいはキャパシタ
により終端され、上記第2のスロット線路が出力線路と
されているモノリシックJi’ET発振器。
(1) KFETC field effect transistor on semiconductor substrate)
is formed, and the gate electrode of the FET is connected to the drain electrode and the source electrode, respectively. and a third conductor are formed on the semiconductor substrate, and these first conductors are formed on the semiconductor substrate.
A first slot line is formed by the conductor and the second conductor, and a second slot line is formed by the second conductor and the third conductor.
Kl path is configured, and the first slot line is connected to the F
A monolithic Ji'ET oscillator which is terminated with an open termination or a capacitor at a position of a finite length from the ET, and the second slot line is used as an output line.
(2)半導体基板上に、特許請求範囲第1項記載の発振
器が2細膜られ、そのドレイン電極に接続された導体が
共通され、かつスロット線路からなる2本の出力線路の
方向が同一となるように対称に配置され、その2本の出
方線路は1本のコプレーナ線路に接続され、そのコプレ
ーナ線路が共通の出力線路とされ、かつそのコプレーナ
線路の2つの外側導体が短絡導体で接続されていること
を特徴とする特許請求の範囲第1項記載のモノリシック
FET発振器。
(2) Two thin films of the oscillator according to claim 1 are formed on a semiconductor substrate, the conductor connected to the drain electrode is common, and the direction of the two output lines consisting of slot lines is the same. The two output lines are connected to one coplanar line, which is used as a common output line, and the two outer conductors of the coplanar line are connected by a shorting conductor. A monolithic FET oscillator according to claim 1, characterized in that:
JP21444983A 1983-11-14 1983-11-14 Monolithic fet oscillator Pending JPS60106205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21444983A JPS60106205A (en) 1983-11-14 1983-11-14 Monolithic fet oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21444983A JPS60106205A (en) 1983-11-14 1983-11-14 Monolithic fet oscillator

Publications (1)

Publication Number Publication Date
JPS60106205A true JPS60106205A (en) 1985-06-11

Family

ID=16655944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21444983A Pending JPS60106205A (en) 1983-11-14 1983-11-14 Monolithic fet oscillator

Country Status (1)

Country Link
JP (1) JPS60106205A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2839219A1 (en) * 2002-03-29 2003-10-31 Murata Manufacturing Co HIGH FREQUENCY CIRCUIT DEVICE USING A SLOT LINE AND COMMUNICATION APPARATUS COMPRISING A HIGH FREQUENCY CIRCUIT DEVICE.
US6737687B2 (en) * 2002-02-27 2004-05-18 Murata Manufacturing Co., Ltd. Field-effect transistor device having a uniquely arranged gate electrode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6737687B2 (en) * 2002-02-27 2004-05-18 Murata Manufacturing Co., Ltd. Field-effect transistor device having a uniquely arranged gate electrode
FR2839219A1 (en) * 2002-03-29 2003-10-31 Murata Manufacturing Co HIGH FREQUENCY CIRCUIT DEVICE USING A SLOT LINE AND COMMUNICATION APPARATUS COMPRISING A HIGH FREQUENCY CIRCUIT DEVICE.
US6778031B2 (en) 2002-03-29 2004-08-17 Murata Manufacturing Co. Ltd High-frequency circuit device using slot line and communication apparatus having high frequency circuit device

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