JPS60102733A - Forming method of ohmic electrode - Google Patents

Forming method of ohmic electrode

Info

Publication number
JPS60102733A
JPS60102733A JP20996683A JP20996683A JPS60102733A JP S60102733 A JPS60102733 A JP S60102733A JP 20996683 A JP20996683 A JP 20996683A JP 20996683 A JP20996683 A JP 20996683A JP S60102733 A JPS60102733 A JP S60102733A
Authority
JP
Japan
Prior art keywords
layer
ohmic
auge
thickness
type gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20996683A
Other languages
Japanese (ja)
Inventor
Toshio Nonaka
野中 敏夫
Toshimasa Ishida
俊正 石田
Masanori Sumiya
角谷 昌紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP20996683A priority Critical patent/JPS60102733A/en
Publication of JPS60102733A publication Critical patent/JPS60102733A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To lower contact resistance, to improve the morphology of the surface of an ohmic electrode and to reduce the area of the electrode by forming a first layer for the ohmic electrode having multilayer structure to an N type GaAs layer in an AuGe layer and bringing the thickness of the first layer to 350Angstrom or less. CONSTITUTION:An N type GaAs layer 2 is formed on a semi-insulating GaAs substrate 1. The N type GaAs layer 2 is formed by implanting Si ions at 1.5X 10<13>does/cm<2>.100keV and activating the ions. An AuGe layer 3, an Ni layer 4 and an Au layer 5 are shaped on the layer 2. These layers 3, 4, 5 are formed through several evaporation in thickness of 300Angstrom , 300Angstrom and 1,000Angstrom and patterning by a lift-off method. An ohmic contact is obtained between the N type GaAs layer 2 and the AuGe layer 3 through ohmic heat treatment. The morphology of the surface is improved by bringing the thickness of the AuGe layer 3 to 350Angstrom or less.

Description

【発明の詳細な説明】 (技術分野) この発明はn形GaAs層へのオーミック電極形成方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for forming an ohmic electrode on an n-type GaAs layer.

(従来技術) この種のオーミック電極形成方法の一つとして、n形G
aAs層の表面にAu Ge層を被着し、その後オーミ
ック処理を行ってn+形領領域あるアロイ層を形成し、
これによってn形GaAs層とのオーミック接触を得る
方法が公知である。
(Prior art) As one of the methods for forming this type of ohmic electrode, n-type G
An Au Ge layer is deposited on the surface of the aAs layer, and then ohmic treatment is performed to form an alloy layer with an n+ type region,
A method of obtaining ohmic contact with the n-type GaAs layer by this is known.

また、AuGe層の表面モホロジーを改善するため(1
) に、もしくはボール・アラf (Ball up)軽減
のために、Niやptなとの被覆層を有する2層構造、
あるいは更にその被覆層の酸化防止等のために、Au層
ガとを有する3層構造をなすことも知られている。
In addition, in order to improve the surface morphology of the AuGe layer (1
), or a two-layer structure with a coating layer of Ni or PT to reduce ball up.
Alternatively, it is also known to form a three-layer structure including an Au layer and an Au layer in order to further prevent oxidation of the coating layer.

典型例においては、12 wt% GeoAuGe層を
1000λ被着し、その上にNi層を300X被着し、
その上にAuを1oool被着し、その後400℃〜4
50℃の温度で1分間程度のオーミック熱処理を行う。
In a typical example, a 12 wt% GeoAuGe layer is deposited at 1000λ, on top of which a Ni layer is deposited at 300X;
On top of that, 10ool of Au was deposited, and then 400℃~400℃
Ohmic heat treatment is performed at a temperature of 50° C. for about 1 minute.

この方法によれば、低抵抗のオーミック接触が得られる
が、電極の表面モホロジーはオーミック処理温度に敏感
であり、また最も低抵抗となるオーミック処理温度での
表面モホロジーは必ずしも良好でなく、ICなどの微細
な電極形状を必要とする場合などに問題点を含んでいる
According to this method, a low-resistance ohmic contact can be obtained, but the surface morphology of the electrode is sensitive to the ohmic processing temperature, and the surface morphology at the ohmic processing temperature where the lowest resistance is obtained is not necessarily good. This includes problems when a fine electrode shape is required.

本発明者らは、AuGe合金によるオーミック接触は、
AuGe/n形GaAsとの合金化反応による当該Au
Ge/n形GaAs界面にn+層を形成するという現象
を利用するものであるため、AuGe層の厚みによシ(
2) GaAsとの反応層厚は異なり、それはオーミック接触
の諸物性の制御要因となり得るとの想定のもとに実験し
た結果、AuGe厚は表面モホロゾーの支配的要因であ
るとの確信を持つに至った。
The present inventors believe that the ohmic contact made by the AuGe alloy is
The Au by alloying reaction with AuGe/n-type GaAs
Since it utilizes the phenomenon of forming an n+ layer at the Ge/n-type GaAs interface, it depends on the thickness of the AuGe layer (
2) As a result of experiments based on the assumption that the thickness of the reaction layer with GaAs is different and that this can be a factor controlling the physical properties of ohmic contact, we are confident that the AuGe thickness is the dominant factor for the surface moholozor. It's arrived.

(発明の目的) 本発明は、このような知見に基づいて達成されたもので
あシ、その目的は、良好なオーミック接触抵抗と良好々
電極表面モホロノーをもったオーミック電極の形成方法
を提供することにあり、又オーミック処理温度変動の許
容範囲が広くしかも安定性に優れた方法を提供すること
にある。
(Object of the Invention) The present invention has been achieved based on such knowledge, and its object is to provide a method for forming an ohmic electrode having good ohmic contact resistance and good electrode surface moholonau. In particular, it is an object of the present invention to provide a method that has a wide tolerance range for ohmic processing temperature fluctuations and is excellent in stability.

(発明の構成) 本発明はこのような目的を、AuGe合金を用いてn形
GaAs層にオーミック接触を形成する方法において、
Au GeO層厚を350X以下に設定することによっ
て達成したものであり、以下詳細に説明する。
(Structure of the Invention) The present invention achieves the above object in a method of forming an ohmic contact to an n-type GaAs layer using an AuGe alloy.
This was achieved by setting the AuGeO layer thickness to 350X or less, and will be described in detail below.

(実施例) 第1図はこの発明の詳細な説明するだめに示しだ断面図
であり、第1図において、lは半絶縁性GaAs基板、
2はn形GaAs層である。n形GaAs層2は、St
イオンを1−、5 X 1.015doesAyn2.
1. O0keVの条件で注入し、活性化して形成する
。第1図において、3〜5は3層構造のオーミック電極
であシ、3はAuGe、4はN:、5はAuである。こ
れらAuGe/Ni/Auの3層は、それぞれ300X
/300X/100OXの厚さに連続的に蒸着しリフト
オフ法によりパターンニングすることによって形成する
。その後n形GaAsとAuGe層とのオーミック接触
を得るためにオーミック熱処理を行う。
(Example) FIG. 1 is a cross-sectional view for explaining the present invention in detail, and in FIG. 1, l is a semi-insulating GaAs substrate;
2 is an n-type GaAs layer. The n-type GaAs layer 2 is made of St
ion 1-, 5 X 1.015doesAyn2.
1. It is formed by implanting and activating it under the condition of 0 keV. In FIG. 1, 3 to 5 are ohmic electrodes having a three-layer structure, 3 is AuGe, 4 is N:, and 5 is Au. These three layers of AuGe/Ni/Au are each 300X
It is formed by continuous vapor deposition to a thickness of /300X/100OX and patterning using a lift-off method. Thereafter, ohmic heat treatment is performed to obtain ohmic contact between the n-type GaAs and AuGe layers.

第2図は、AuGe/Ni/Auの3層構造を有するオ
ーミック電極のオーミック熱処理における温度を横軸に
とシ、縦軸に接触抵抗値をプロットした場合を示し、特
性(、)はAuGe層の厚さが300Xの場合であシ、
特性(b)はAuGe層の厚さが100OXの場合であ
り、Ni/Au (D厚さは共に3ooX/1oooX
であり、オーミック熱処理時間は1分である。この第2
図から明らかなように、AuGe層の厚みを300Xと
した場合の方が接触抵抗率は低く、且つ広いオーミック
処理温度の範囲にわたって、はぼ一定の接触抵抗率が得
られる。
Figure 2 shows the case where the temperature during ohmic heat treatment of an ohmic electrode having a three-layer structure of AuGe/Ni/Au is plotted on the horizontal axis and the contact resistance value is plotted on the vertical axis. If the thickness of is 300X,
Characteristic (b) is for the case where the AuGe layer thickness is 100OX, and the Ni/Au (D thickness is 3ooX/1oooX)
The ohmic heat treatment time is 1 minute. This second
As is clear from the figure, the contact resistivity is lower when the thickness of the AuGe layer is 300X, and a more or less constant contact resistivity can be obtained over a wide range of ohmic processing temperatures.

第3図は250℃でエーシングを行い、接触抵抗率の時
間的変化を示したものであり、特性(a)はAuGe層
の厚さを300Xとした場合でちシ、特性(b)はAu
Ge層の厚さを100OXとした場合であり、この第3
図から明らかなように、AuGe層の厚さを300Xと
しだ方エージング試験においても優れ、接触抵抗率が安
定であることがわかる。
Figure 3 shows the change in contact resistivity over time when acing was performed at 250°C. Characteristic (a) is for the case where the thickness of the AuGe layer is 300X, and characteristic (b) is for the case where the thickness of the AuGe layer is 300X.
This is the case where the thickness of the Ge layer is 100OX, and this third
As is clear from the figure, when the thickness of the AuGe layer is 300X, it is excellent even in the aging test, and the contact resistivity is stable.

第4図と第5図は、オーミック熱処理後のAu層5の表
面モホロジーを示すものであり、光学顕微鏡写真を模写
して示したものである。
FIGS. 4 and 5 show the surface morphology of the Au layer 5 after the ohmic heat treatment, and are copies of optical micrographs.

第4図(a)は、AuGe層の厚さが300Xで430
℃で1分間のオーミック熱処理を行った場合の表面を示
しておシ、第4図(b)はAuGe層の厚さを1000
又とし、他は同じ条件とした場合の表面を示している。
In Figure 4(a), the thickness of the AuGe layer is 300X and 430X.
Figure 4(b) shows the surface after ohmic heat treatment for 1 minute at ℃.
In addition, the surface is shown under the same conditions as above.

第5図(、)は、AuGe層の厚さが300Xで450
℃で1分間のオーミック熱処理を行った場合の表面を示
しており、第5図(b)はAuGe層の厚さを1000
又とし他は同じ条件とした場合の表面を示してい(5) る。
Figure 5 (,) shows that the thickness of the AuGe layer is 300X and 450X.
Figure 5(b) shows the surface after ohmic heat treatment at ℃ for 1 minute.
In addition, the surface is shown under the same conditions (5).

第4図と第5図から明らかなように、AuGe層を10
00Xとした場合には、オーミック熱処理温度を430
℃で行なった場合、6μ大の変質領域が16チ程度を占
めることが観察され、オーミック熱処理を450℃で行
なうと、全表面で凝集を起こし凸凹が発生して表面モホ
ロゾーが極端に悪化するのに対し、AuGe層を300
Xとした場合に、500倍の光学顕微鏡では変質領域は
全く観察されない。
As is clear from Figures 4 and 5, the AuGe layer is
When set to 00X, the ohmic heat treatment temperature is set to 430
When ohmic heat treatment is carried out at 450°C, it is observed that a 6μ-sized altered region occupies about 16 inches, and when ohmic heat treatment is carried out at 450°C, agglomeration occurs on the entire surface, causing unevenness and extremely deteriorating the surface mohorozo. On the other hand, the AuGe layer is 300
When X is used, no altered region is observed under a 500x optical microscope.

以上の実施例はGaAs層を300Xとした場合につい
て説明しだが100X厚に設定しても一1350又に設
定しても同様の効果が得られる。なお、AuGe層は4
00X程度でも比較的良好であるが、500X厚で43
0℃、1分間のオーミック熱処理を行うと11係程度の
変質領域が発生する。したがって、AuGe層の層厚変
動を考慮した場合、AuGe層は350X以下に設定す
べきである。
In the above embodiments, the GaAs layer is 300X thick, but the same effect can be obtained even if the thickness is 100X or 11350X. Note that the AuGe layer is 4
00X thickness is relatively good, but 500X thickness is 43
When ohmic heat treatment is performed at 0° C. for 1 minute, a deterioration region of about 11 coefficients is generated. Therefore, when considering the thickness variation of the AuGe layer, the thickness of the AuGe layer should be set to 350X or less.

(発明の効果) 以上説明したように、本発明は、n形GaAs層(6) の表面にAuGe層を最下層とする2層あるいは3層構
造のオーミック電極形において、AuGe層を十分に薄
くしたものであり、低い接触抵抗率と良好な表面モホロ
ジーがオーミック処理温度の広い範囲で得られ、更に接
触抵抗率の安定性も良好であるため、高集積化に伴いオ
ーミック電極面積の縮少化が必要とされる場合、本発明
によるオーミック電極形成方法は充分に有効である。
(Effects of the Invention) As explained above, the present invention provides an ohmic electrode type with a two-layer or three-layer structure in which an AuGe layer is the bottom layer on the surface of an n-type GaAs layer (6), by making the AuGe layer sufficiently thin. As a result, low contact resistivity and good surface morphology can be obtained over a wide range of ohmic processing temperatures, and the stability of contact resistivity is also good, making it possible to reduce the ohmic electrode area with higher integration. The method for forming an ohmic electrode according to the present invention is fully effective when the following is required.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるオーミック電極の構造断面図、 第2図はオーミック処理温度に対するオーミック接触抵
抗率を示す図、 第3図は250℃でエージングを行い、オーミック接触
抵抗率の時間的変化を示した図、第4図及び第5図は、
Au膜の表面モホロジーを示すもので光学顕微鏡写真を
模写した図である。 1・・・半絶縁性GaAs基板、2・・・n形GaAs
層、3・・・AuCxe膜、4 ・−・Ni膜、5−A
u膜。 (7) 第2図 オーミ・ツク処理温度FCI
Figure 1 is a cross-sectional view of the structure of the ohmic electrode according to the present invention, Figure 2 is a diagram showing the ohmic contact resistivity versus ohmic treatment temperature, and Figure 3 is a diagram showing the temporal change in ohmic contact resistivity after aging at 250°C. The figures shown, Figures 4 and 5, are
It is a diagram illustrating the surface morphology of an Au film and is a reproduction of an optical micrograph. 1... Semi-insulating GaAs substrate, 2... N-type GaAs
Layer, 3...AuCxe film, 4...Ni film, 5-A
u membrane. (7) Figure 2 Ohmi Tsuk treatment temperature FCI

Claims (1)

【特許請求の範囲】 n形GaAs層へのオーミック電極構成として、AuG
e層を第1層とした2層または多層構造のオーミック電
極を形成する方法において、 第1層のAuGe層厚を350X以下にすることを特徴
とするオーミック電極形成方法。
[Claims] As an ohmic electrode structure for the n-type GaAs layer, AuG
A method for forming an ohmic electrode with a two-layer or multilayer structure in which the e-layer is the first layer, the method comprising making the AuGe layer thickness of the first layer 350X or less.
JP20996683A 1983-11-10 1983-11-10 Forming method of ohmic electrode Pending JPS60102733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20996683A JPS60102733A (en) 1983-11-10 1983-11-10 Forming method of ohmic electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20996683A JPS60102733A (en) 1983-11-10 1983-11-10 Forming method of ohmic electrode

Publications (1)

Publication Number Publication Date
JPS60102733A true JPS60102733A (en) 1985-06-06

Family

ID=16581625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20996683A Pending JPS60102733A (en) 1983-11-10 1983-11-10 Forming method of ohmic electrode

Country Status (1)

Country Link
JP (1) JPS60102733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001047038A1 (en) * 1999-12-22 2001-06-28 Lumileds Lighting U.S., Llc Multi-layer highly reflective ohmic contacts for light-emitting semiconductor devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57106087A (en) * 1980-11-03 1982-07-01 Siemens Ag Light reflective ohmic contact and method of producing same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57106087A (en) * 1980-11-03 1982-07-01 Siemens Ag Light reflective ohmic contact and method of producing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001047038A1 (en) * 1999-12-22 2001-06-28 Lumileds Lighting U.S., Llc Multi-layer highly reflective ohmic contacts for light-emitting semiconductor devices
US6992334B1 (en) 1999-12-22 2006-01-31 Lumileds Lighting U.S., Llc Multi-layer highly reflective ohmic contacts for semiconductor devices

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