JPS60102574A - Programmable timer test circuit - Google Patents

Abstract

PURPOSE:To facilitate the testing of data stored in RAM, by inputting a test signal only for a predetermined time corresponding to data at the intermediate level between first and second levels. CONSTITUTION:A test signal is inputted to a comparator 84 only for a predetermined time corresponding to data at an intermediate level while power source voltage divided by resistors 85, 86 are applied to separate terminals as reference voltages to output an input signal only at the time of the intermediate level. The output thereof is inverted by an inverter 87 to open an AND gate 88 and a clock pulse is guided to a counter 89 to start the measurement of the clock pulse. This measuring output is supplied to a programmable logic array circuit 90 which in turn outputs a load signal (b) for loading the counting output of the counter 89 to an adder 91 when the count value reaches a predetermined value. The adder 91 generates a bit pattern signal same to data stored in RAM4 when counting output is loaded and the content of RAM4 can be easily tested on the basis of this signal.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a programmable timer test circuit, and more particularly, to a programmable timer test circuit having a limited number of pins and, for example, a multi-pin circuit.
- A built-in RAM that converts the data stored in the RAM into serial data and outputs the C output.
I will.

Explanation of the prior art Figure 1 shows a general LS with a built-in multi-pit [(8M)
FIG. 1 is a schematic block diagram of I. In Figure 1 [, L31'
IO is timing signal generation circuit 1, frequency divider circuit 2 and goo 1
- Built-in circuit 3, address circuit 4, RAM 5, etc. An oscillation circuit 6 and a keyboard 7 are connected to LSllo. The oscillation circuit 6 generates clock pulses, and is connected to the frequency dividing circuit 2 built into the LSI 10.
Divide the frequency of the beam Utsuk pulse and generate the timing circuit generator circuit 1.
Give the divided output to . The timing signal generation circuit 1 generates a predetermined timing signal based on the frequency-divided output and supplies it to the gate circuit 3. A key input signal is given to the gate circuit 3 from the keyboard 7. In response to the timing signal, the gates 1 and 3 supply data to the RAM 5 corresponding to the key signals inputted from the keyboard 7/J). The address circuit 4 calculates t' RAM 5 based on the output of the frequency divider circuit 2.
gives an address signal to.

The RAM 5 stores data input from the keyboard 7 at a predetermined address based on an address signal from the address circuit 4. Data stored in the RAM 5 is read out in response to signals from the keyboard 7. Such a combination of LSIs is often used in electronic type Nakachi meters and the like.

By the way, in 18110 as shown in FIG.
1 (When testing data stored in 8M5,
It is necessary to specify the address of the RAM 5 by the address circuit 4, but since the number of terminals is limited in a 1-deep LSI, the test terminals for manually inputting the address signal from the outside are required.) Unable to do so, R
It wasn't easy to write down the contents of AM5.

OBJECTS OF THE INVENTION Therefore, the main object of the present invention is to provide a programming timer test circuit that can easily test the contents of a multi-bit RAM, for example, without providing any special test terminals. It is to write.

SUMMARY OF THE INVENTION To summarize the present invention, a terminal of an electronic circuit receiving IMl is provided with a signal at an intermediate level between the first level and the second level for a predetermined time depending on the data. The test signal is manually counted during the period when the test signal is at the intermediate level, and based on the counted value, a pattern signal of arbitrary bits representing the C pulse is generated. Testing the circuit: This is a programmable timer circuit made up of a combination of sea urchins.

The above-mentioned objects and other objects and features of this invention will become clearer from the detailed description given above with reference to the two drawings.

Description of examples FIG. 2 is a schematic block diagram of one embodiment of Jin's invention.

2, one embodiment of the present invention will be explained. The input terminal 81 is connected to the L S shown in FIG. 1.
This is an input terminal to which a control signal necessary for the normal operation of I'I.0 is input, and is used as a test signal for the desist I-circuit 8. When a control signal is input to the input terminal 81, the LSI l
The control signal is applied to other circuits within 0. but,
When LSllo is set to DES, a test value of 15 yen is input to this input terminal 81. This DES+-4= signal is set to the high level as the first level, depending on the content of RAM4 to be tested. There is a signal which has an intermediate level between the low level and the second level for a certain period of time Fli. This dest signal is applied to the comparison input terminal of the comparator 84.

A reference voltage obtained by dividing the power supply voltage by resistors 85 and 86 is input to the reference input terminal of the comparator 84.

Therefore, the comparator 84 outputs a J-level signal only when the signal input to the input terminal 81 is at an intermediate level. The output of this inverter 84 is inverted by an inverter 87 and applied to one input terminal of an AND gate 1-88. A beam lock pulse is applied to the input terminals of the NO gate 1-88. Therefore, [,AN
The D gate 8B closes the gate (gives a clock pulse to the counter 89) only when the comparator 84 determines the intermediate level.

Counter 89 counts the clock pulses and provides the fil value to programmable logic array circuit 90.

This programmable logic array circuit 90 sets the flip-flop 92 when the count value of the counter 89 reaches a predetermined value.
B and the rotary information for loading the count output of the counter 89 into the counter 9'l, output the reset signal P3C for resetting the counter 89 and the Noritsubu flop 92. It is something that When the counting horn of the counter 89 is loaded, the adder 91 outputs a signal having the same bit pattern as the data stored in the RAM 4. The output of the booster 9-1 is given to the UEXOR gate 96 through a buffer 1 circuit 93.94 with a 1-Rice i-to-Rice circuit 93, 96, respectively. EX
The other input terminal of OR goo h95.96 has RAM 4
The successive outputs of J-i are obtained. Therefore, [, E
If the signal read from the adder 91 and the signal read from RΔM4 match [1
- level signal)], and if different, outputs high L/bell 5 times a month. EX OR goo 1-95.9G
The output of O] is applied to a display circuit 98 via a gate 97. The display circuit 98 is constructed in such a way that if the data consecutively outputted from the pins 1 to 1 of the stressor 91 and the data successively outputted from 1<ΔM4 match, then the birth month will be displayed.

Furthermore, sl? Is there a beam 1 on the foot force terminal 83? The TS1~(No.8 is given.This reset) signal passes through the OR circuit 99 to the counter 89, and also resets the flip knob L1 knob 92 through 0[KUGU 1~+00. , programmable logic array circuit 90
) Reset I/Shin J"Jc that was J is also OR gate 9
The counter 89 is reset to 1 through 9, and O
11 Gate 1oO through Flipf [Reset Kotup 92 1~! do.

FIG. 3 is a waveform diagram for explaining the operation of FIG. 2.

Next, the operation shown in FIG. 2 will be explained with reference to the third factor. Ma! I゛, as shown in Figure 3 (a), the death ire
No matter what I do, it's 10m5ec and I'm at an intermediate level. ] When the comparator 84 detects that the dest signal has become an intermediate level, it changes its output to a low level. This low level signal is inverted by the inverter 87 at J and -J to open the AN IJ tag--88.

When the A N D signal 88 is heard, a clock pulse is applied to the counter 09, which counts the 81 number of clock pulses. The counting output of the counter 89 is applied to the P1'' grammar pull logic array circuit 9°. In the programmable logic array circuit 90, the count value of the counter 89 is 5000 zu 10m sca $1
After that, a set signal a is given to the 7-lip 1" knob 92. The knob 70 and the knob 92 are activated by the set signal a.
- and enables the tri-stated Butts 1 circuit 93.9/I.

Next, test Shinkyu l i m sec I! Between IJ and intermediate level 4, but 1 classable logic circuit 90 has a reduction value of counter 89 of 11+++se.
It turned out to be c! E''-Toy No. 5 is given to the adder 91.

As a result, the 81 number output of the counter 89 is input to the rifer 91. In addition, 2 olls have faith in Dest.
When the ea 19J interval reaches 1, the progera 7 logic array circuit V890 again outputs the load signal and inputs the HL number output j of the counter 89 to the adder 9-1. . The adder 91 adds the crystal 1 number output of l'1tsec and the 61 number output of 20m5ec, and adds n output 31.
Bin 1 to pattern signals corresponding to i sec are output. These P1-pattern signals correspond to the f-event read out from RA tvl4.

Therefore (the 1T XOR gates 95 and 96 are
Bit pattern No. 13 output from 1 and RA tvl
It is determined whether or not the data successively output from 4 match. If they do not match, the display circuit 98 is displayed.
z'a'I! 6゜shi I:ga-)ri-1 input terminal 8
``Ikm'' is inputted manually by the mid-level dead signal.

Since it is possible to output the same bit pattern signal, the contents of 1<Δ to 14 can be easily destroyed.

According to this invention, the electronic circuit No. 1g is manually operated at the intermediate level between the first level and the second level. The first thing that happened was the visit of Shir, who built the Novust IJJ by hand (from the second, it was an intermediate level of reading time [Noval Sui Uno was Akira 1 number, and t's i! 1 number V11.-Based on ( Random human bassine 1c
generate a number. 1, ) and I5 [, By using this pattern signal, it is possible to easily 1-strike data such as 1 stored in 1c anything R/\8.・'”−’% J strike signal manually;
I don't need the end of the terminal
Is it possible to apply it to a limited number of tests such as LSI?

[Brief explanation of drawings]

11i11J is a schematic block diagram of a conventional LSI. ! Figure 12 is a schematic 1179 diagram of an embodiment of this invention. FIG. 3 is a waveform diagram for explaining the operation of FIG. 2. Figure kjj (, 81 is the input terminal, No. 84 is the converter, 88 is the A N l) Goo 1-189 is the counter, 90
is a put 1 non-7 nor logic array circuit, 91 is an adder, 92 is a noripf 1 tip 1.93.94 is a 1-ler (
/'%7-1・f・1 pan 7 door circuit, 9! :+, 96 is E(01<n"-1,97+, tOR gate, 98 is a display circuit. 1""Di Rjy':i l/-7"f:%"ゞQ 21 47.・Representative Patent Attorney Hisashi Fuka
Part Jin・' 1 (and 2 others)''

Claims (1)

[Claims] 1- at an intermediate level between the first level and the second level.
By setting the dest signal for a predetermined time in the IC according to a signal input terminal used in parallel; a detection means for detecting whether the taste signal is at the intermediate level; a group number means for counting the period during which the detection means is at the intermediate level or pulse signals; J3; and a programmable timer circuit comprising pattern signal generating means for generating a pattern 219 of arbitrary bits representing the data based on the 81 numerical value of the counting means.