JPS5999823A - ロジツクアレイ - Google Patents

ロジツクアレイ

Info

Publication number
JPS5999823A
JPS5999823A JP57208861A JP20886182A JPS5999823A JP S5999823 A JPS5999823 A JP S5999823A JP 57208861 A JP57208861 A JP 57208861A JP 20886182 A JP20886182 A JP 20886182A JP S5999823 A JPS5999823 A JP S5999823A
Authority
JP
Japan
Prior art keywords
gate circuit
array
input
gate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57208861A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0137009B2 (enExample
Inventor
Junichi Iwasaki
岩先　純一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57208861A priority Critical patent/JPS5999823A/ja
Publication of JPS5999823A publication Critical patent/JPS5999823A/ja
Publication of JPH0137009B2 publication Critical patent/JPH0137009B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
JP57208861A 1982-11-29 1982-11-29 ロジツクアレイ Granted JPS5999823A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57208861A JPS5999823A (ja) 1982-11-29 1982-11-29 ロジツクアレイ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57208861A JPS5999823A (ja) 1982-11-29 1982-11-29 ロジツクアレイ

Publications (2)

Publication Number Publication Date
JPS5999823A true JPS5999823A (ja) 1984-06-08
JPH0137009B2 JPH0137009B2 (enExample) 1989-08-03

Family

ID=16563329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57208861A Granted JPS5999823A (ja) 1982-11-29 1982-11-29 ロジツクアレイ

Country Status (1)

Country Link
JP (1) JPS5999823A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6211323A (ja) * 1985-07-09 1987-01-20 Matsushita Electric Ind Co Ltd 半導体記憶装置
US5634061A (en) * 1990-05-24 1997-05-27 Kabushiki Kaisha Toshiba Instruction decoder utilizing a low power PLA that powers up both AND and OR planes only when successful instruction fetch signal is provided

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596629A (ja) * 1982-07-02 1984-01-13 Matsushita Electric Ind Co Ltd プログラマブルロジツクアレイ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596629A (ja) * 1982-07-02 1984-01-13 Matsushita Electric Ind Co Ltd プログラマブルロジツクアレイ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6211323A (ja) * 1985-07-09 1987-01-20 Matsushita Electric Ind Co Ltd 半導体記憶装置
US5634061A (en) * 1990-05-24 1997-05-27 Kabushiki Kaisha Toshiba Instruction decoder utilizing a low power PLA that powers up both AND and OR planes only when successful instruction fetch signal is provided

Also Published As

Publication number Publication date
JPH0137009B2 (enExample) 1989-08-03

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