JPS5999713A - Manufacture of substrate for thin-film transistor - Google Patents
Manufacture of substrate for thin-film transistorInfo
- Publication number
- JPS5999713A JPS5999713A JP57208639A JP20863982A JPS5999713A JP S5999713 A JPS5999713 A JP S5999713A JP 57208639 A JP57208639 A JP 57208639A JP 20863982 A JP20863982 A JP 20863982A JP S5999713 A JPS5999713 A JP S5999713A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- glass substrate
- silicon nitride
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02683—Continuous wave laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は薄膜トランジスタ用基板の１．製造方法Ｃ二線
り１．特（二窒素イオン注入による窒化胆ユ形、成を用
、ＩＪまた薄膜トランジスタ用基板の製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to 1. a substrate for a thin film transistor; Manufacturing method C double line 1. In particular, the present invention relates to a method for manufacturing substrates for IJ and thin film transistors using nitrided bilayer formation by dinitrogen ion implantation.
［従来技術とその間照点〕
従来、厚さ１μ程度のポリシリコン等の半導体掩に￥４
膜トランジスタ等液晶テレビ用素子を形成する事が知ら
れていた。しかし、移動度が０．１ｉ／ｌ、１０００程
度と悪く、性能が悪かった。この理由はボ刃シリコンの
粒径が小さい７ｉ径を大きくスる仏法としてレーザーア
ニールが馬えられていた。[Prior art and its highlights] Conventionally, a semiconductor cover made of polysilicon or the like with a thickness of about 1 μm costs ¥4.
It has been known to form elements for liquid crystal televisions such as film transistors. However, the mobility was poor at 0.1 i/l, about 1000, and the performance was poor. The reason for this is that laser annealing was considered a Buddhist method to greatly reduce the 7i diameter, which has a small grain size.
その方法は、耐熱性を持つ石英ガラス基板上５二酸化珪
素（Ｓ１０ｇ）膜を被着し、周期的な溝切りを行なって
ポリシリコンを被着し、レーザーアニールにより再結晶
化する方法であった○
しかしながら、５ｉ０２は溝切部の耗′度が悪く、かつ
耐熱、性が恋いため、アニールのしλ結晶成長が不均質
であった。父、アニールの際・ポリ・シリコンＣコクラ
ンクが匈、数に生して、基板の歩留りが低下すること・
があった。これに対しｈ’ ５１ｏ２ｆｉりの代わりに
懐化珪累膜を用いる事が本発明者によって考えられたが
、その膜形成泥層が、６３０℃程度等高いため石英ガラ
ス等高’ｍｉｉで機械加工性が蝋しい基板を用いなけれ
ばならないという問題があった。The method was to deposit a silicon dioxide (S10g) film on a heat-resistant quartz glass substrate, make periodic grooves, deposit polysilicon, and recrystallize it by laser annealing. ○ However, 5i02 had poor wear of the grooved portion and poor heat resistance and properties, resulting in non-uniform λ crystal growth during annealing. During annealing, polysilicon C cracks form in large numbers, reducing the yield of the substrate.
was there. In response to this, the present inventor considered using a silica film instead of h'51o2fi, but since the film-forming mud layer was at a high temperature of about 630°C, it was difficult to machine the silica glass with a height of 'mii'. There was a problem in that a substrate with low properties had to be used.
このような欠点を改良するために本発明がなさＶｔ、た
も、のであり、結晶の成長を歩留り良く行なうと−に、
安価で加工精度の良いガラス基板を用いることができる
ようにする事を目的とするものである。The present invention was developed to improve these drawbacks, and in order to grow crystals with high yield,
The purpose is to make it possible to use a glass substrate that is inexpensive and has good processing precision.
本発明は透明ガラス基板又はその表面に酸化珪素膜が設
けられた基板に窒素のイオン注入を行なって窒化珪素膜
を形成し、この窒化珪素膜上に半導体膜な被着し、ガラ
ス軟化点より低い温度（二於加この半導体膜なアニール
して再結晶化させ層口１〔発明の効果〕
本発明によれは従来のものよりも大きな結晶が均−ｆ二
得られる。又、窒素イオン注入により窒化珪素膜を得る
ようにしているので、低温で窒化珪素膜が形成出来、ガ
ラス基板として安価で機械的精度の良いものを使用でき
るようＣ二なる。In the present invention, a silicon nitride film is formed by implanting nitrogen ions into a transparent glass substrate or a substrate having a silicon oxide film on its surface, and a semiconductor film is deposited on the silicon nitride film, and the glass softening point is [Effects of the Invention] According to the present invention, larger crystals can be uniformly obtained than in the conventional method. Since the silicon nitride film is obtained by using C2, the silicon nitride film can be formed at a low temperature, and a glass substrate that is inexpensive and has good mechanical precision can be used.
第１図、第２図はこの発明の一実施例であり、透明ホウ
珪酸ガラス基板１上の飴化珪素膜（ｓｉｇＮ４）２にレ
ジストハターンを用いたフレオンガスによるプラズマエ
ソナングによりストンイブ状の肩（深さ−０，２μ９幅
−２μ）を設けた。これは例えば透明ホウ珪酸ガラス基
板１に窒素のイオン注入（３０ＫｅＶ、 １０”、／ｃ
Ｊ）を行い４００°Ｃ２０分加熱反応させて（ＳｉとＮ
とが反応する）窒化珪素膜２を設ける。溝切りは精度良
く行なうことかで＠た。さらにポリシリコン膜３をＬＰ
Ｃ！ＶＤ法で被着して、所要部【ニイオンビーム（ψり
えばＰ＋ ）を照射した後〜コＷ−Ａｒレーザービーム
な、ここではスポット四ｒｒ。FIGS. 1 and 2 show an embodiment of the present invention, in which stone-ive shaped shoulders are formed by plasma ethoning with Freon gas using a resist pattern on a candied silicon film (sigN4) 2 on a transparent borosilicate glass substrate 1. (depth -0, 2μ9 width -2μ) was provided. For example, nitrogen ion implantation (30KeV, 10", /c
J) and heated to react at 400°C for 20 minutes (Si and N
A silicon nitride film 2 is provided. Groove cutting must be done with precision. Furthermore, polysilicon film 3 is LP
C! After applying the film using the VD method and irradiating the desired area with a two-ion beam (P+ if ψ), a W-Ar laser beam (here, spot 4) is applied.
１→ｍ走五幅５０μｍで所望のパターンで走査田る。Scan the desired pattern in a 1->m scan with a width of 50 μm.
アニール時のガラス基板温度はヒーターで加譜すること
（二より５００℃ｆ二する。イオン注入を全面に行ない
、全面Ｃニレーザーピームを走査するよう（二してもよ
い。これ（二よりポリシリコン膜のレーザー照射部Ｃ：
ｌ−は大きなドープ再結酩が生じる。結晶粒径は約１０
μであった。第２図はガラス基板１′に５ｉｏ２２’を
つけ、この上から窒素のイオン注入を２０ＫｅＶ、 １
０ ” ／ｃｒｌのドーズ倹で打こみ、後４００℃２０
分加熱し、窒化膜を形成する。この膜に溝切り（深１０
．２μ、ｒｉ］２μ）を設は上からＬＰ−ＣＶＤ法Ｃよ
ってポリシリコン３′をつける。そして第１図と同様（
二この上から１０ｗアルゴンレーザーでアニールし、結
晶成長させる。The temperature of the glass substrate during annealing must be increased with a heater (500°C from Laser irradiation part C of silicon film:
l- causes large dope reconsolidation. The grain size is approximately 10
It was μ. In Figure 2, 5io22' is attached to a glass substrate 1', and nitrogen ions are implanted from above at 20 KeV, 1
0”/crl dose sparingly, then heated to 400℃20
The nitride film is formed by heating for 10 minutes. Cut a groove in this membrane (depth 10
．． 2μ, ri]2μ), polysilicon 3' is applied from above by LP-CVD method C. And similar to Figure 1 (
Second, annealing is performed from above using a 10W argon laser to grow crystals.
従来のグラフオエビにょる粒径が２〜３μに対し、本ポ
リシリコンの粒径は１０−１２μｍ＋二も達した。而る
後このグラフエピタキシャルガラス基板のドーピング領
域ｌ二Ｐ−チャンネルＦＥＴを製作した。この素子のホ
ール移動度はμＨ＝ ８５ｃｒｌ／ｖ・ｓｅｅであり、
グラフオエピタキシャルガラス基板の比抵抗は８００傷
であり比抵抗のばらつきも±５係以内（二納まっていた
。アニール時の基板上のポリシリコンのクラックは全く
なく、はぼ均質ｆ二粒径の１゛ろった多結晶が多数成長
していた０又基板の辿−１７りも９０％以上でめった。While the grain size of conventional graphite shrimp is 2 to 3 μm, the grain size of this polysilicon has reached 10-12 μm+2. Thereafter, a P-channel FET was fabricated using the doped region of this graph epitaxial glass substrate. The Hall mobility of this element is μH = 85 crl/v·see,
The resistivity of the graphite epitaxial glass substrate was 800 scratches, and the variation in resistivity was within ±5 coefficients (within 2).There were no cracks in the polysilicon on the substrate during annealing, and it was almost homogeneous with two grain sizes. More than 90% of traces of the zero-shaped substrate on which a large number of polycrystals of 100% were grown were also unsuccessful.
従ってこの基板はＦＥ’ｌ’作製のための半導体グラフ
オエピタキシー基板と〕て工業的にすぐれたものである
ということがで艷る。Therefore, it can be concluded that this substrate is industrially excellent as a semiconductor graphoepitaxy substrate for producing FE'l'.
上記実施ψりではホウ珪酸ガラスを用いたが、アルミシ
リケートガラス又は半硬質ガラスを使用し刊る。Although borosilicate glass was used in the above implementation, aluminum silicate glass or semi-hard glass may also be used.
これらは安ｉｊｔ＋で機械的加工精度も良い。又、窒し
なくても窒化珪素膜を作成する事が可能である。These are cheap and have good mechanical processing accuracy. Furthermore, it is possible to form a silicon nitride film without nitriding.
又、レーザービーム（二よるアニールの他に全体を加熱
炉中でアニールするようにしてもよい。In addition to laser beam annealing, the entire structure may be annealed in a heating furnace.
第１図及び第２図は本発明の入流Ｖすを説明する断面図
で４うる。図において、
１、１′・−・ホウ珪酸ガラス基板
２・・・窒化珪素膜 ２・・・５ｉｏ２膜３．３′
・・ポリシリコン膜FIGS. 1 and 2 are cross-sectional views illustrating the inflow valve of the present invention. In the figure, 1, 1' -- Borosilicate glass substrate 2... Silicon nitride film 2... 5io2 film 3.3'
・Polysilicon film
Claims (1)
基板【二窒素のイオン注入を行なって窒化珪素膜、を形
成し、この窒化珪素膜上に半導体鰹を被着し、ガラス軟
化点より低い温度に於てこの半[Claims] A transparent glass substrate or a substrate on which a silicon oxide film is provided [a silicon nitride film is formed by ion implantation of dinitrogen, and a semiconductor bonito is deposited on this silicon nitride film. , at a temperature lower than the glass softening point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57208639A JPS5999713A (en) | 1982-11-30 | 1982-11-30 | Manufacture of substrate for thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57208639A JPS5999713A (en) | 1982-11-30 | 1982-11-30 | Manufacture of substrate for thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999713A true JPS5999713A (en) | 1984-06-08 |
Family
ID=16559565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57208639A Pending JPS5999713A (en) | 1982-11-30 | 1982-11-30 | Manufacture of substrate for thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999713A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01157437A (en) * | 1987-12-15 | 1989-06-20 | Nippon Sheet Glass Co Ltd | Method for modifying surface of glass |
| FR2648454A1 (en) * | 1989-06-19 | 1990-12-21 | Nippon Sheet Glass Co Ltd | METHOD FOR MODIFYING THE SURFACE OF A GLASS SUBSTRATE |
| US7226817B2 (en) | 2001-12-28 | 2007-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing |
-
1982
- 1982-11-30 JP JP57208639A patent/JPS5999713A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01157437A (en) * | 1987-12-15 | 1989-06-20 | Nippon Sheet Glass Co Ltd | Method for modifying surface of glass |
| FR2648454A1 (en) * | 1989-06-19 | 1990-12-21 | Nippon Sheet Glass Co Ltd | METHOD FOR MODIFYING THE SURFACE OF A GLASS SUBSTRATE |
| US7226817B2 (en) | 2001-12-28 | 2007-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing |
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