JPS5997472U - Logic analyzer trigger setting circuit - Google Patents
Logic analyzer trigger setting circuitInfo
- Publication number
- JPS5997472U JPS5997472U JP19264482U JP19264482U JPS5997472U JP S5997472 U JPS5997472 U JP S5997472U JP 19264482 U JP19264482 U JP 19264482U JP 19264482 U JP19264482 U JP 19264482U JP S5997472 U JPS5997472 U JP S5997472U
- Authority
- JP
- Japan
- Prior art keywords
- setting circuit
- logic analyzer
- trigger setting
- circuit
- analyzer trigger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示すブロック図である。
１・・・・・・入カブローブ、２・・・・・・設定条件
入力、３・・・・・・設定条件入力、４・・・・・・比
較回路、５・・・・・・比較回路・６°゛°゛°°一致
体号５”／ｆ出り・７°°°°°°一致信号出力。FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Input probe, 2...Setting condition input, 3...Setting condition input, 4...Comparison circuit, 5...Comparison Circuit: 6°゛°゛°° Matching body number 5"/f output. 7°°°°°° Matching signal output.
Claims (1)
るロジックアナライザのトリガ設定回路において、あら
かじめ設定できる複数入力の条件を複数種持ち、それら
の入力条件が順次溝たされた時にトリガ信号が発生させ
られることを特徴とするロジックアナライザの！・リガ
設定回路。The logic analyzer's trigger setting circuit, which includes a sampling circuit, logic circuit, and memory, has multiple types of multiple input conditions that can be set in advance, and a trigger signal is generated when those input conditions are met in sequence. A logic analyzer featuring this!・Register setting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19264482U JPS5997472U (en) | 1982-12-20 | 1982-12-20 | Logic analyzer trigger setting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19264482U JPS5997472U (en) | 1982-12-20 | 1982-12-20 | Logic analyzer trigger setting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5997472U true JPS5997472U (en) | 1984-07-02 |
Family
ID=30414534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19264482U Pending JPS5997472U (en) | 1982-12-20 | 1982-12-20 | Logic analyzer trigger setting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5997472U (en) |
-
1982
- 1982-12-20 JP JP19264482U patent/JPS5997472U/en active Pending
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