JPS5997223A - Load driving circuit - Google Patents

Abstract

PURPOSE:To drive surely a load with one kind of power source, by boosting a binary signal which is supplied to an input terminal by a boosting circuit to control a semiconductor driving element in follower-connection and lowering the on-state resistance of the semiconductor driving element. CONSTITUTION:A binary signal (a) for switching control is supplied to an input terminal 4. An output (b) of an oscillating circuit 5 is subjected to gate control in a NAND gate 6 by the signal (a), and a charge pump circuit 7 is driven by an output (c). An inverter 8 of the circuit 7 repeats the inverting operation in a high speed by the output (c). In accordance with this inversion, charge to a capacitor 9 through a diode 10 and discharge of the capacitor 9 through a diode 11 are repeated. The electric charge of the capacitor 9 is supplied to a follower- connected transistor TR13 through a resistance 12. As the result, the TR13 is driven with a double voltage of a power source voltage +VDD.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a load drive circuit suitable for controlling a load (such as a vehicle headlamp) whose one side is grounded on and off using a semiconductor drive element connected as a follower.

Among the loads for private electric vehicles, there are many loads that are grounded on one side, such as headlamps.

As shown in FIG. 1, such a single-side grounded load 1 is connected to a follower-connected semiconductor drive element 2 (in the figure, it is an n-channel MOS transistor, but in the case of a bipolar transistor, it is an np
n l- transistor), the binary signal for switching control supplied to the input terminal 4 is
Even if the voltage applied to the load 1 is raised to the voltage Voo supplied to the power supply terminal 3, the voltage applied to the load 1 is only vl, as shown in the graph of FIG. There may be cases where it cannot be driven.

On the other hand, if the "l-1" level of the switching control binary signal is not raised above the power supply voltage +Voo, the drive element 2
The on-resistance of is reduced and sufficient voltage can be supplied to load 1, but in order to do so, a high-voltage power supply must be prepared separately from the power supply +Voo, which leads to an increase in the cost of the entire device. be.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to control on/off of a single-side grounded load using a follower-connected semiconductor drive element, by using one type of power supply. The purpose is to drive it reliably.

In order to achieve the above object, the present invention increases the binary signal supplied to the input terminal to a level higher than the power supply voltage via a booster circuit, and connects the binary signal after this increase to a follower. The device controls the on/off state of the semiconductor drive element.

Hereinafter, some embodiments of the present invention will be described in detail with reference to FIGS. 3 to 5.

FIG. 3 is an electric circuit diagram showing the configuration of an embodiment of the load drive circuit (hereinafter referred to as the first embodiment) according to the present invention. In the same figure, a binary signal a for switching control (hereinafter referred to as switching input) is supplied to the input terminal 4, and the # of this switching input a is supplied.
The H11 level is approximately set to -VDDG,:.

Oscillation circuit 5 is a theory]! T! Inverter 5 consisting of I.C.
1°52, a resistor 53, and a capacitor 54.This oscillation circuit 5 outputs an oscillation output that is sufficiently high-speed for the expected minimum pulse width of the switching force a. Output.

Then, this oscillation output is sent to the NAND gate 6.
After being gate-controlled by the switching power a, the charge pump circuit 7 is driven by the output C thereof.

The charge pump circuit 7 includes a CMOS inverter 8 that is invertedly driven by the output C of the NAND gate 6, and a diode on the inlet side that is forward biased in accordance with the "L11 period" of the inverter 8 and allows charging current to the capacitor 9. 10 and a discharge side diode 11 which is forward biased corresponding to the 1'' period of the inverter 8 and discharges the charge charged in the capacitor 9.

The output side of the charge pump circuit 7 is connected to the gate of an n-channel power MO3t transistor 13 via a resistor 12, and this transistor 13 has a train connected to a power supply terminal 17, and a load 14 through a source follower connection. configured to drive.

Moreover, between the gate of the transistor 13 and the ground,
An n-channel MOS transistor 15 is connected with its source being grounded, and the gate of this transistor 15 is connected via an inverter 16 configured with 0MO3 in this example.
The switching power a is reversed and supplied.

In the following configuration, when the value of the switching power a supplied to the input terminal 4 rises from L'' to ``Tobi'', the output of the oscillation circuit 5 passes through the NAND gate 6, and then It is supplied as an output C to the charge pump circuit 7.

Then, the inverter 8 repeats a high-speed inversion operation in synchronization with the output C, and each time the inverter 8 performs a high-speed inversion operation, charging of the capacitor 9 via the diode 10 and discharging of the capacitor 9 via the diode 11 are repeated.

In this way, the charge of the capacitor 9 discharged from the charge pump circuit 7 is stored in the gate capacitance ff1co of the transistor 13 via the resistor 12, and the gate voltage of the transistor 13 gradually increases. Finally, the power supply voltage -V o o □) is twice as high as +2V
It reaches oo.

Therefore, the gate-source voltage V of the transistor 13
Approximately 10Voo is applied to GS, and the on-resistance value is set sufficiently small, and at the same time, approximately the power supply voltage → -Voo is applied to the load 14, thereby making it possible to reliably drive the load 14. becomes.

On the other hand, when the value of the switching input a supplied to the input terminal 4 falls from '11' to 'L', the operation of the charge pump circuit 7 is interrupted and the transistor 15 is turned on. The charge stored in the gate capacitor ICo is rapidly discharged via the transistor 15,
Transistor 13 will be turned off immediately.

Furthermore, according to the first embodiment, in addition to the original effect of the invention that the semiconductor drive element connected as a follower can be reliably driven by one type of power supply, the switching input Δ is In response, the output of the oscillation circuit 5 is supplied to the charge pump circuit 7, thereby driving the charge pump circuit 7 at high speed. 1'1
F) It is also possible to integrate the booster circuit part, which also has a built-in power supply capacitor 9.
Great cost reduction effect.

41-Well, since the charging capacitor is several pF, we can convert it into MOS gate capacitance (3.54 x 10' pF).
F/'μ? ) on a silicon substrate using
It can be realized with a size of μll12, and therefore a booster circuit including a charge capacitor and a 0 channel for load driving.
vl OS +- transistors can be integrated on the same semiconductor chip. In addition, the booster circuit part is [Idit
7 channel power MOS transistor (horizontal or vertical)
It is extremely small compared to the chip area of
Since the process is the same, even if the booster circuit part is added by 1, it will hardly affect the cost increase.

Also, one side is grounded! If an n-channel MOS transistor is used as an element for driving the 1'4 load 14, the following will occur compared to when the single-side grounded load 14 is driven by a source-grounded p-channel MOS transistor. In other words, when comparing the mobility of an n-channel MOS transistor and an n-channel MOS transistor, normally μp = 200cll12/V-s
ec, un = about 6000 m2/V-sec, which is larger for the 3x n-channel 1yn channel MOS transistor.

Therefore, in order to obtain the same drain current ros, the value of channel width W/channel length 1- must be made 1) three times larger for the channel MO3l- transistor than for the n-channel MO31- transistor.

In other words, since the channel length 1- is almost constant, 1)
Channel MO8I - transistor is p channel MO8
This means that the area occupied by the chip can be reduced to one-third of that of a transistor.

Next, FIG. 4 is a circuit diagram showing the configuration of a third embodiment (hereinafter referred to as the second embodiment) of the load driving circuit according to the present invention. In FIG. 4, the same components as those in FIG. 3 are designated by the same reference numerals, and the explanation thereof will be omitted.

The feature of this a''
In addition, an EDMOS inverter is used as an inverter constituting each charge pump circuit, thereby increasing switching speed.

That is, in FIG. 4, the first charge pump circuit 1
8 boosts the voltage up to +2Vo o, and 1. :
One second charge pump circuit is capable of boosting the voltage up to +3DD.

The first charge pump circuit 18 includes a NAND group 1-6.
E D lv performs high-speed inversion operation in synchronization with the output C of
l OS inverter 20 and l l of this inverter 20
The inlet diode 22 is forward biased in correspondence with the L II output period and allows charging current to the capacitor 21.

Further, one second charge pump circuit performs a high-speed inversion operation in synchronization with a signal d obtained by inverting the output C of the NAND gate 6 with an inverter 23.
An inverter 24, a suction side diode 26 which is forward biased corresponding to the "L" output period of the inverter 24 and allows charging current to the capacitor 25, and a suction side diode 26 corresponding to the "H" period of the inverter 24. The discharge side diode 27 is biased forward in the forward direction and discharges the charge stored in the capacitor 25.

Therefore, the first charge pump circuit 18 and the second charge pump circuit 19 are 180 degrees apart from each other in synchronization with the signal C.
The capacitor 2 of the first charge pump circuit is driven in the first half of each cycle of the signal C.
The charge charged to 1 is phase-shifted to the capacitor 25 of the second charge pump circuit 19 in the second half of the cycle, and then the gate capacitance of the transistor 13 is shifted to the capacitor 25 in the first half of the next cycle.
It will be stored repeatedly.

As a result, if the above operations are repeated at high speed,
The gate voltage of the transistor 13 gradually increases and finally reaches 13 Vo o, which is three times the power supply voltage + Vo o, and the on-resistance of the transistor 13 further decreases, and the voltage with respect to the load 14 increases. can apply a higher voltage than in the first embodiment, keep the power consumption of the load 14 constant, reduce the value of the drain current ros, and reduce the power loss in the run raster 13. This makes it possible to avoid further reductions.

Thus, according to the second embodiment, in addition to the effects of the first embodiment, the amount of heat generated is reduced by reducing the power loss in the transistor 13, and the size of the heat sink can be reduced. This contributes to reducing wasteful power consumption in the transistor 13 and increasing the battery life.

In addition, the above-mentioned No. 1. In the second embodiment, a CMOS inverter and an EDMOS inverter are shown as the inverters that drive the charge pump circuit, but it goes without saying that a normal impark consisting of a resistor and a transistor connected in series may be used instead. It is.

Next, FIG. 5 shows another example of the oscillation circuit 5, in which N is used as the second stage inverting cable I constituting the oscillation circuit.
By using the OR gate 55 and supplying switching power a to the parentheses, the oscillation operation itself can be directly turned on.
It is designed to be turned off.

In this way, the oscillation operation will be stopped unless rr L u is supplied to the input terminal 4, and therefore the power consumption in the oscillation circuit 5 can be significantly reduced, especially when the oscillation frequency is increased. can be reduced to

In the above embodiment, a unipolar transistor was used as the semiconductor drive element for driving the load, but it is of course possible to obtain the same on-resistance reduction effect with a bipolar transistor as the semiconductor drive element. .

Hereinafter, as is clear from the description of each embodiment of J2, the load drive circuit according to the present invention operates after the two signals for switching control supplied to the input terminal are raised to a voltage higher than the power supply voltage via the voltage circuit. Since this is supplied to a semiconductor drive element that drives a load through a follower connection, it is possible to sufficiently reduce the on-resistance of the semiconductor drive element and drive the load reliably.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram for explaining the conventional problem, Fig. 2 is a graph showing the operating curve in the same circuit, Fig. 3 is a circuit diagram showing the first embodiment of the present invention, and Fig. 4 is a circuit diagram of the present invention. A circuit diagram showing the second embodiment, and FIG. 5 is a circuit diagram showing an example of an oscillation circuit. 4... Input terminal 5... Oscillation circuit 7... Charge pump circuit 13... n channel power MO8l ~ transistor 1
4...Load 18...First charge pump circuit 19...Second charge pump circuit Patent applicant Nissan Motor Co., Ltd.

Claims (1)

[Claims] (1) An input circuit to which a binary signal for switching control is supplied = 1 child: A booster circuit that boosts the 21"1 signal supplied to the input terminal to a voltage higher than the power supply voltage; and an output of the booster circuit. A load drive circuit characterized by comprising a semiconductor drive element that is controlled to be on and off and that drives a load through a follower connection.