JP2899892B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device.

[Summary of the Invention]

According to the present invention, in a semiconductor device having a MOS transistor, a current drive source for charging a capacity of a control gate of an output MOS transistor for driving an external load supplies two DC voltages for turning on or off the output MOS transistor to the control gate. And a charge current drive source for charging the control gate via a capacitor, thereby providing an output MOS transistor. Without delaying the change start time, the DC characteristics and the AC characteristics required for the practical use of the MOS transistor are set independently of each other, and the output current value at the time of driving the capacitive load is reduced, and The purpose is to make the output current change gradual to prevent malfunction and noise.

[Conventional technology]

In a conventional so-called complementary MOS transistor composed of a P-channel type and an N-channel type, as a measure for preventing malfunction and noise caused by the MOS output transistor, a P-channel transistor and an N-channel transistor are used when the control gate voltage changes. There is a technique for preventing a through current from flowing between power supplies due to simultaneous conduction of transistors. This is mainly to reduce the current in the semiconductor device, for example, by slightly shifting the time at which the control gate voltage of each of the MOS transistors changes by some method,
In particular, it was insufficient as a technique considering the capacitive external load.

[Problems to be solved by the invention]

Generally, a MOS transistor for driving an external load is designed in consideration of a DC driving capability and an AC driving capability. The DC driving capability is defined as a voltage drop in a MOS transistor when a DC output current flows to drive a load. The AC driving capability is defined by a rise time or a fall time of the voltage of the output terminal of the MOS transistor when driving a capacitive load. In recent years, with the advancement of miniaturization technology in semiconductor devices, the speed has increased, and as the capability of the output transistor has improved, the DC drive capability and the AC drive capability have been increased.
It is becoming difficult to simultaneously set appropriate values for the capabilities required for actual use.

As an example, as a DC characteristic, when a DC current of 15 mA flows through a pure low-configuration load, the voltage drop in the MOS transistor is
0.3V or less, AC load is 100P as AC load
At F, consider a MOS transistor whose rise time or fall time is within 25 NS.

Assuming a specific MOS manufacturing process and deciding the size of an N-channel MOS transistor as a practical example, if the DC characteristics are given priority so that they have an appropriate value, the AC characteristics will have a fall time of 9NS and an appropriate value of 25NS. It will be less than half.

FIG. 6 shows the above-mentioned output drive circuit as a conventional example. 2
Is fixed to a high level by the control gate of one P-channel transistor, and one P-channel MOS transistor is OFF. 4 is 3 N-channel MOS
A low to high transition at the control gate of the transistor. 3 N-channel MOS transistors from OFF
When it starts to conduct to ON, the charge of the capacitor 5 initially charged to a high level is discharged, and the output terminal 6,
It changes from a high level to a low level.

FIG. 7 shows the change in the voltage of the gate 4 and the drain 6 of the three N-channel transistors in the above case in the conventional example. The vertical axis is voltage and the horizontal axis is time.

When setting according to one of the characteristics in this way, the other characteristics often become excessive. This excess characteristic did not become a problem before the speeding up of semiconductor devices in recent years. However, various problems have arisen as the speeding-up progresses. A typical problem is that the change in current is too great and noise is applied to the power supply, causing a malfunction or a large amount of electromagnetic radiation noise in the semiconductor device system as a whole. FIG. 8 shows a current flowing through the MOS transistor in the above-mentioned conventional example. The vertical axis is the current, and the horizontal axis is the time axis.
The peak current reaches about 65 mA and the rate of change of the current is up to about 30 mA / nS.

FIG. 9 shows a system model on a substrate on which a plurality of semiconductor devices are arranged. 7 is a conventional semiconductor device, 10 is an output terminal, 8 is another semiconductor device, 11 is an input terminal, and 10 and 11
Are connected on the substrate. This is a capacitor having a wiring capacity of 5 on the substrate. A power supply 12 is connected to power supply terminals of the semiconductor devices 7 and 8. Reference numeral 9 denotes an inductance existing on a common potential line between the semiconductor devices. Actually, the capacitors 5 and the inductances 9 exist in a distributed constant manner, and the capacitors and the inductance components also exist on other wirings. Here, the operation will be considered with a simplified model. The output current of the MOS transistor flows from the MOS transistor to the power supply line via the load capacitor 5. Here, for example, it is assumed that there is an inductance 9 of 20 nH in the power supply wiring of the substrate. Since the counter electromotive force by the time the inductance is the product of the rate of change of current and inductance, calculated to try the 20 × 10 ^- a 9 = 0.6 volts ^{- 9 × 30 × 10 - 3} ÷ 10.

If a plurality of similar output terminals change simultaneously, the back electromotive force noise increases proportionally. This back electromotive force noise causes a potential difference in a signal transmission between the semiconductor devices, where the potential should be a common potential point, thereby causing a malfunction. Actually, the capacitor and the inductance component also exist in other wirings and exist in a distributed constant manner, so that the operation becomes more complicated, and both the common potential line and the signal line have an oscillating waveform called ringing. When the amount of current and the change in current increase, it becomes impossible to remove noise even with a power supply smoothing capacitor inserted between power supplies. It is also known that electromagnetic radiation increases as the change in current increases.

In the conventional method, in order to avoid this problem, the change in the control gate voltage is slowed by lowering the current capability of the transistor that drives the control gate of the output MOS transistor, so that the output MOS transistor has the DC drive capability required for actual use. Is satisfied, and at the same time, a method of solving a problem caused by an AC drive capacity more than necessary for actual use can be considered. In particular, when driving a capacitive load such as a capacitor, reducing the peak value and the current change rate of the output current and reducing malfunction and electromagnetic radiation noise due to noise generation in a semiconductor device system including a wiring board are not considered. It is possible. FIG. 7 shows a waveform 42 when the gate of the control gate 4 is slowly driven. 62 is an output drain waveform of 6 corresponding to 42 control gates. The control gate signal 42 is shown at 52 in FIG.
Shows the output current corresponding to.

In this way, by lowering the current capability of the transistor that drives the control gate of the output MOS transistor to slow down the change in the control gate voltage, the peak current can be reduced from 65 mA.
The current rate of change has also been reduced from 31 mA / nS to 5 mA / nS to 33 mA.

However, a method of simply increasing the impedance of the current source that drives the control gate capacitance is that the control gate voltage is OF
It also increases the time required to change from the level of F to the voltage at which the MOS transistor is turned on, that is, the so-called threshold voltage. In this transient state, the MOS transistor is not turned on, so that it does not become a noise generation source, but there is a problem that the time to start changing the output is delayed more than necessary. Therefore, an object of the present invention is to reduce the output MO transistor without making the time until the output MOS transistor is turned ON unnecessarily long.
An object of the present invention is to provide a semiconductor device in which noise or the like that can be generated after the S transistor starts to be turned on is reduced.

[Means for solving the problem]

In the semiconductor device of the present invention, a first potential is applied to a MOS transistor and a gate capacitance of the MOS transistor when an input signal has a first value, and the gate potential is applied to the gate capacitance when the input signal has a second value. A driving unit for applying a second potential, wherein the driving unit is configured such that when the input signal has a first value, the gate capacitance of the MOS transistor becomes close to a threshold potential of the MOS transistor. A first drive circuit for charging the gate capacitance via a capacitor, and when the input signal reaches the first value, the first drive circuit
A second driving circuit that charges the gate capacitance of the S transistor until the gate capacitance reaches the first potential.

[Action]

According to the above configuration of the present invention, the stage where the capacitance of the control gate is charged by the current drive source and the voltage of the control gate of the output MOS transistor shifts from the OFF level to the sufficiently ON level is divided into two stages. Output MOS even if the threshold level is close to the threshold level from the OFF level of the MOS transistor, which is the transition stage of
Up to the control gate voltage level at which the current capability of the transistor is low, the control gate voltage is quickly shifted by the two current driving sources of the present invention, and the change start time of the output MOS transistor is not delayed. At the next transition stage, at the control gate voltage level at which the current capability of the MOS transistor is increased, the control gate is gradually changed only by the charging current generating source on one side of the present invention in which the impedance is set relatively high, and the output is changed. An increase in the absolute value of the output current flowing through the load capacitance and a rapid change are prevented.

[Embodiment] In the case of an output composed of a P-channel transistor and an N-channel transistor, the case of an N-channel transistor will be described. The same applies to the case of a P-channel transistor.

FIG. 1 is a block diagram of an embodiment of the present invention.
Channel MOS transistor, 4 is a control gate,
6 is a drain output terminal, 14 is a source, and 5 is an external load capacitance. Reference numeral 1 denotes an output MOS transistor controlled charging current source block for supplying two DC voltages for driving the control gates of 4, and here, an inverter composed of 151 P-channel MOS transistors and 152 N-channel MOS transistors. Although shown, other element configurations may be used. 17
Is a capacitor existing on the wiring from the control gate drive charging current source block 1 to the control gate 4 such as the gate capacitance and the wiring capacitance of the N-channel transistor 3. The input of 15 changes from high level to low level, the output of 1 changes the control gate of 4 from low level to high level, and the N-channel transistor of 3 changes from non-conductive to conductive, and is connected to the output of 6 Is discharged and changes from a high level to a low level. As the output impedance of one block is larger and the capacitor value of 17 is larger, the control gate voltage is less likely to change from a low level to a high level.

The operation of the two capacitively coupled charging current source blocks at this time will be described. 18 is a capacitor and 19 is an inverter. When 15 changes from high level to low level, the inverter output of 19 changes from low level to high level. At this time, the control gate voltage of 4 is shifted to a higher level depending on the capacitors 17 and 18 due to a change in the potential of one side of the capacitor 18. These two actions are:
The 18 capacitors act as a temporary current source.

Therefore, as shown at 43 in FIG. 4, the current is rapidly raised to a high level by the current sources 1 and 2, and when the current from the current source 2 is turned off, only the drive of 1 is performed and the level gradually changes to the high level. . Reference numeral 63 denotes a drain voltage waveform of the output MOS transistor, which starts to change from a high level to a low level earlier than the drain waveform in the conventional example of 62. FIG. 5 shows the output current waveform according to the present invention, which changes earlier in time as compared with the output current waveform 52 in the conventional example.

Further, the eighteenth capacitor in the present invention can be easily realized in the same manner as the case of manufacturing other capacitors by combining gate materials, wiring materials, and the like in a semiconductor device manufacturing process. It is also possible to use PN junction capacitance. In addition, a MOS transistor can be applied.

Although the present invention has been described using an N-channel MOS transistor as an embodiment, the present invention can be similarly realized on the P-channel side of an output MOS transistor.

2 and 3 show another embodiment of the charging current source block according to the present invention.

153 and 154 are P-channel MOS transistors, 163 and 164
Is an N-channel MOS transistor, and 156 and 166 are inverters. Reference numerals 155 and 165 denote charging capacitors, and the charge initially charged to a high level raises the control gate of the output MOS transistor to a high level via the MOS transistor. In this case, the capacitor is not directly connected to the control gate, but has the same function as the embodiment of FIG. 1 of the present invention in that the control gate is charged via the capacitor.

〔The invention's effect〕

As described above, according to the present invention, since there are two current driving sources for charging the capacity of the control gate of the output MOS transistor for driving the external load, the control gate can be driven in two stages.

If the voltage level of the control gate is close to the threshold level from the OFF level of the MOS transistor, or the control gate voltage level at which the current capability of the output MOS transistor is low even if it slightly exceeds the threshold, the two current driving sources of the present invention are used. This allows the control gate voltage to transition quickly, and does not delay the change start time of the output MOS transistor. At the next transition stage, at the control gate voltage level at which the current capability of the MOS transistor is increased, the control gate is gradually changed only by the charging current generating source on one side of the present invention in which the impedance is set relatively high, and the output is changed. It is possible to prevent the absolute value of the output current flowing through the load capacitance from increasing and abruptly changing. This satisfies the DC drive capability required for actual use in MOS transistors,
It is possible not to have an AC drive capacity more than necessary for actual use without delaying the change start time of the output MOS transistor, and it has the effect of adjusting the AC drive capacity separately from the DC drive capacity .

In addition, the method of the present invention adjusts the AC driving capacity necessary for actual use, so that the output current peak value and the current change when the output terminal changes, particularly when driving a capacitive load such as a capacitor. This has the effect of lowering the rate, and has the effect of reducing malfunctions and electromagnetic radiation noise caused by noise generation in a semiconductor device system including a wiring board.

[Brief description of the drawings]

FIG. 1 is a configuration diagram in an embodiment of the present invention. FIG. 2 is a diagram showing another embodiment of the two blocks according to the present invention. FIG. 3 is a diagram showing another embodiment of the two blocks according to the present invention. FIG. 4 is a diagram showing input / output voltage characteristics of an output MOS transistor in an embodiment of the present invention. FIG. 5 is an output current waveform diagram of the embodiment of the present invention. FIG. 6 is an output drive circuit diagram in a conventional example. FIG. 7 is an input / output voltage characteristic diagram in a conventional example. FIG. 8 is an output current waveform diagram in a conventional example. FIG. 9 is a board model diagram in which a plurality of semiconductor devices are arranged.

Claims (1)

(57) [Claims] A first potential is applied to a MOS transistor and a gate capacitance of the MOS transistor when an input signal has a first value, and a second potential is applied to the gate capacitance when the input signal has a second value. A driving unit for applying the potential of the MOS transistor, when the input signal becomes a first value, the driving unit operates until the gate capacitance of the MOS transistor becomes close to the threshold potential of the MOS transistor. A first driving circuit that charges a capacitance via a capacitor; and a second driving circuit that charges the gate capacitance until the gate capacitance of the MOS transistor reaches the first potential when the input signal has the first value. A semiconductor device, comprising: two driving circuits.