CN1609743A - Low-noise stablized voltage circuit capable of fast stopping working - Google Patents
Low-noise stablized voltage circuit capable of fast stopping working Download PDFInfo
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Abstract
The fast voltage stabilizing circuit includes one amplifier circuit to output one drive voltage based on one initiating voltage signal; one output transistor connected electrically to the amplifier circuit, one output node for outputting one voltage and the first voltage source; the first discharge transistor connected electrically to the initiating voltage signal, the output node and one feedback node; and the second discharge transistor connected electrically to the initiating voltage signal, the feedback node and one second voltage source. When the initiating voltage signal stops the amplifier circuit, the initiating voltage signal conducts the first discharge transistor and the second discharge transistor, conducts the output node and the feedback node and pulls down the output voltage fast.
Description
Technical field
The invention provides a kind of low noise mu balanced circuit and be used for this mu balanced circuit method of termination work fast, particularly a kind of starting voltage signal that utilizes, conducting one output node, a feedback node and a ground voltage supplies are with the mu balanced circuit and the correlation technique of the output voltage that drags down this low noise mu balanced circuit fast.
Background technology
In present on the market various electronic products, usually can use mu balanced circuit and carry out the work that voltage is adjusted, and provide stable voltage to being arranged at the mu balanced circuit component external.For example, in many micro controller systems, for a core circuit (Corecircuit) and the different bias voltage of another output/input circuit (I/OCircuit) that is used for carrying out data operation, data processing will be provided, usually will produce lower (voltage stabilizing) output voltage according to higher DC voltage with a mu balanced circuit, and provide bias voltage (Bias) to output/input circuit and core circuit with this DC voltage and this output voltage respectively.See also Fig. 1, Fig. 1 is the synoptic diagram of a conventional mu balanced circuit 10, and also comprises an outer external circuit elements 18 that is connected on mu balanced circuit 10 among Fig. 1, for example above-mentioned core circuit.Conventional mu balanced circuit 10 comprises an amplifier circuit 12 (Amplifier), an output transistor 14 and a load blocks 16, load blocks 16 comprises a load capacitance CL and two pull-up resistor RL1, RL2 again, and this load capacitance CL and two pull-up resistor RL1, RL2 are connected between an output node NOUT and the one second voltage source V SS (the second voltage source V SS provides a low-level DC voltage or a ground connection (Ground) voltage usually).Amplifier circuit 12 comprises one first receiving end Na1 and one second receiving end Na2 (this first and second receiving end Na1, Na2 can be considered two differential input terminals), the first receiving end Na1 is electrically connected to an external reference voltage generator 13 (ReferenceVoltageGenerator), be used for receiving respectively a reference voltage (ReferenceVoltage), the second receiving end Na2 is electrically connected to a feedback node NF1, receive a feedback voltage (FeedbackVoltage), and this reference voltage is produced by reference voltage generator 13 promptly.Like this, amplifier circuit 12 can be controlled grid (Gate) bias voltage of output transistor 14 according to reference voltage, feedback voltage and starting voltage signal (EnableVoltageSignal) ENABLE to export a driving voltage to output transistor 14 at an output terminal Np1.
In this conventional embodiment, output transistor 14 is designed to P type NMOS N-channel MOS N (PMOS) transistor, the grid of output transistor 14 is electrically connected to amplifier circuit 12 via node Np1, drain electrode is electrically connected to output node NOUT, and its source electrode is electrically connected to one first voltage source V CC.The DC voltage of the high level that provides in the system is provided the first voltage source V CC, for example, if mu balanced circuit 10 is arranged in the micro controller system, the first voltage source V CC is made as the Dc bias of 3.3V (volt), that is, the DC voltage of this 3.3V is the Dc bias that this micro controller system and 10 work of this mu balanced circuit are provided, and under these mu balanced circuit 10 work, 18 of external external circuit elements can be biased in lower 2.5V, that is to say, in this configuration, mu balanced circuit 10 utilizes the DC voltage (the first voltage source V CC) of 3.3V, produce the stable output voltage of 2.5V at output node NOUT, the electrical power requirements during 18 work of supply external circuit elements.Please continue to consult Fig. 1, output transistor 14 can be according to controlling an output voltage at output node NOUT by the driving voltage operation of grid to adjust, in addition, output node NOUT is connected to the load capacitance CL with certain capacitance, this load capacitance CL can be used to voltage stabilizing, also can fall the interference of AC ripple, and after this load capacitance CL is charged to stable state, just can set up the output voltage of stable state at output node NOUT from other filtering (Bypass).This output voltage can be provided to the voltage use of external circuit elements 18 as bias voltage on the one hand, also can set up feedback voltage at a feedback node NF1 via the dividing potential drop of two pull-up resistor RL1, RL2 on the one hand, and this feedback voltage is provided to amplifier circuit 12.
The situation that drives mu balanced circuit 10 work in the routine techniques can be described below.The first voltage source V CC can be provided to the DC voltage with high level mu balanced circuit 10, and the second voltage source V SS can be provided to mu balanced circuit 10 with having low level DC voltage or ground voltage simultaneously.The DC voltage that one high level is provided at starting voltage signal ENABLE is behind amplifier circuit 12, amplifier circuit 12 and mu balanced circuit 10 are started working, at this moment, amplifier circuit 12 is exported the grid of a low level driving voltage to output transistor 14 at output terminal Np1, conducting first voltage source V CC and output node NOUT, make the voltage between output transistor 14 source electrodes and drain electrode almost be equivalent to voltage difference between DC voltage VCC, VSS, and the electric current that conducting is big between its drain electrode and source electrode charges load capacitance CL as charging current.Along with the carrying out of charging process, the voltage of output node NOUT can rise gradually, and the voltage of node Np1 also can rise gradually, makes the output voltage of output node NOUT be tending towards the definite value of stable state gradually.When having arrived stable state, amplifier circuit 12 can be kept feedback voltage and equate with reference voltage, and this stable output voltage just can be as the Dc bias of external circuit elements 18.When the voltage swing idol of output voltage changed, amplifier circuit 12 will be adjusted controlling and driving voltage accordingly and compensate dynamically.
When desire stops (Disable) these mu balanced circuit 10 work, starting voltage signal ENABLE can change into provides a low level DC voltage to amplifier circuit 12, this low level starting voltage signal ENABLE can stop amplifier circuit 12 work, the driving voltage that makes amplifier circuit 12 transfer at output terminal Np1 to export a high level is to the grid of output transistor 14, because output transistor 14 is a P type channel metal oxide semiconductor transistor, the driving voltage of this high level can turn-off output transistor 14, make the no longer mutual conduction of voltage source V CC and output node NOUT of winning, that is to say that the first voltage source V CC no longer provides the DC voltage of high level to output node NOUT.In the process of mu balanced circuit 10 by load blocks 16 discharges, because of load capacitance CL has certain capacitance, the delay of meeting guiding discharge time, related efficient of procrastinateing mu balanced circuit 10 termination work also makes mu balanced circuit 10 that accurate and stable output voltage can't be provided.Moreover, the increase of electric power consumption amount and termination output voltage that can't be accurate and stable are also represented in the growth that mu balanced circuit 10 stops the time of work, like this, 10 of conventional mu balanced circuits can't be arranged on and stress everywhere in low energy expenditure and the portable electronic system (as mobile computer, PDA(Personal Digital Assistant)) that precisely and stably controls voltage output.
For solving the above problems, and based on the basic structure of above-mentioned mu balanced circuit 10, at USPatentNo.6,362,609, proposed in " Voltageregulator " to utilize a transistor newly is set accelerates the speed that mu balanced circuit 10 stops the output voltage work.Its interlock circuit operation sees also its patent content, is not described in detail in this.
Summary of the invention
Therefore fundamental purpose of the present invention is a kind of low noise mu balanced circuit and is used for this mu balanced circuit method of termination work fast, to address the above problem.
The technical characterictic that mu balanced circuit disclosed in this invention has possessed quick termination work (FastDisable) simultaneously and dragged down the feedback voltage of amplifier circuit, we are based on the structure of conventional mu balanced circuit, newly-increased to few two discharge transistors, make the output voltage of mu balanced circuit can pass through the discharge transistor rapid discharge; In addition, at the newly-increased at least one filter capacitor of the relevant feedback input end of amplifier circuit, at the relevant Radio Frequency Interfere (RFInterferenceSignal) of filtering with when reducing noise, also can utilize discharge transistor to drag down the feedback voltage of amplifier circuit rapidly, implement to reduce noise and reduce discharge time, like this, mu balanced circuit of the present invention can stop work fast, and low noise, accurate and stable output voltage really are provided.
Purpose of the present invention is for providing a kind of mu balanced circuit (VoltageRegulatorCircuit), be used for exporting at least one output voltage (OutputVoltage) at an output node (OutputNode), this mu balanced circuit bag includes an amplifier circuit (Amplifier), comprise one first receiving end and one second receiving end, be used for receiving respectively a reference voltage (ReferenceVoltage) and a feedback voltage (FeedbackVoltage), this amplifier circuit is according to this reference voltage, this feedback voltage, and one the starting voltage signal (EnableVoltageSignal) to export a driving voltage; One output transistor, comprise three ends (Port), this three end is electrically connected to this amplifier circuit, this output node and one first voltage source respectively, and receives this driving voltage, and this output transistor is controlled this output voltage at this output node according to this driving voltage operation to adjust; One first discharge transistor (DischargeTransistor), comprise three ends, this three end is electrically connected to an anti-phase starting voltage signal, this output node and a feedback node respectively, whether this first discharge transistor controls this output node of conducting and this feedback node according to this anti-phase starting voltage signal operation with switch, wherein this feedback node is electrically connected to this second receiving end, can provide this feedback voltage to this amplifier circuit; One second discharge transistor, comprise three ends, this three end is electrically connected to this anti-phase starting voltage signal, this feedback node and one second voltage source respectively, and this first discharge transistor is used for whether controlling this feedback node of conducting and this second voltage source according to this anti-phase starting voltage signal operation with switch; And a load blocks, be electrically connected to this output node, this feedback node and this second voltage source.In addition, comprise at least one filter capacitor (BypassCapacitor), be electrically connected to this second receiving end of this amplifier circuit, be used at least one Radio Frequency Interfere of filtering.
Another object of the present invention is for providing a kind of method that a mu balanced circuit stops (Disable) this mu balanced circuit work fast that is used for, this mu balanced circuit bag includes an amplifier circuit (Amplifier), is used for according to starting voltage signal (EnableVoltageSignal) output one driving voltage; One output transistor is electrically connected to this amplifier circuit, an output node and one first voltage source, is used for controlling an output voltage at this output node according to this driving voltage adjustment; One first discharge transistor (DischargeTransistor) is electrically connected to this starting voltage signal, this output node and a feedback node; And one second discharge transistor, be electrically connected to this starting voltage signal, this feedback node and one second voltage source; This method bag includes (a) and uses this starting voltage signal to stop this amplifier circuit work, so that this driving voltage turn-offs this output transistor, stops adjusting control one output voltage at this output node; (b) in step (a), use this first discharge transistor of this starting voltage signal conduction, this output node of conducting and this feedback node are dragged down (Pull-down) to the approaching magnitude of voltage that is positioned at this feedback node fast so that be positioned at this output voltage of this output node; And (c) in step (a), using this second discharge transistor of this starting voltage signal conduction, this feedback node of conducting and this second voltage source are pulled down to magnitude of voltage near this second voltage source fast so that be positioned at the magnitude of voltage of this feedback node.In addition, comprise (d) in step (c), when this this feedback node of second discharge transistor conducting and this second voltage source, this feedback voltage is pulled down to magnitude of voltage near this second voltage source fast; (e) in step (d), use at least one Radio Frequency Interfere of this filter capacitor filtering; And (f) in step (a), when this starting voltage signal stopped this amplifier circuit work, conducting should stop transistor with this output transistor of quick shutoff, stopped this output node of conducting and this feedback node.
Description of drawings
Fig. 1 is the synoptic diagram of a conventional mu balanced circuit.
Fig. 2 is the synoptic diagram of an embodiment of the present invention's one mu balanced circuit.
Fig. 3 is the process flow diagram of the present invention one method embodiment.
Fig. 4 is the synoptic diagram of another embodiment of Fig. 2 mu balanced circuit of the present invention.
Fig. 5 is the process flow diagram of Fig. 3 other method embodiment.
The reference numeral explanation
10,30 mu balanced circuits, 12,32 amplifier circuits
13 reference voltage generators, 14,34 output transistors
16,36 load blocks, 18,38 external circuit elements
20,40 phase inverters, 22 discharge transistors
41 first discharge transistors, 42 second discharge transistors
44 stop transistor
Embodiment
Technical characterictic of the present invention is for emphasizing the operational scenario of a low noise mu balanced circuit when termination work (Disable).See also Fig. 2, Fig. 2 is the synoptic diagram of an embodiment of the present invention one (low noise) mu balanced circuit 30.Please note, mu balanced circuit 30 shown in Figure 2 is finished with a plurality of metal-oxide semiconductor (MOS) transistor and associated circuit components, and when reality was implemented, these a plurality of metal-oxide semiconductor transistors can be with other kind of transistor, and (BJT) finished as bipolar junction transistor.Ask for an interview Fig. 2, mu balanced circuit 30 include an amplifier circuit 32 (Amplifier), an output transistor 34, a phase inverter 40 (Inverter), one first discharge transistor 41 (DischargeTransistor), one second discharge transistor 42, with a load blocks 36.During actual enforcement, amplifier circuit 32 can be an operational amplifier (OperationalAmplifier) or a differential amplifier (DifferentialAmplifier); Amplifier circuit 32 comprises an output terminal NP1, one first receiving end NA1 and one second receiving end NA2, the first receiving end NA1 can receive a reference voltage, and the second receiving end NA2 can receive a feedback voltage (FeedbackVoltage), amplifier circuit 32 receives a starting voltage signal ENABLE (EnableVoltageSignal) in addition, whether be used for controlling its work, when amplifier circuit 32 carried out work, amplifier circuit 32 can be exported a driving voltage at output terminal Np1 according to reference voltage, feedback voltage and starting voltage signal ENABLE.As previously mentioned, the transistor in the present embodiment is all finished with the metal-oxide semiconductor transistor, and therefore, each transistor has three ends and external circuit joins, and is respectively a grid (Gate), drain electrode (Drain) and an one source pole (Source).The output terminal NP1 of amplifier circuit 32 is connected to the grid of output transistor 34, and the drain electrode of this output transistor 34 is electrically connected to an output node NOUT, and source electrode is electrically connected to one first voltage source V CC.The first voltage source V CC is used to provide the magnitude of voltage of a high level, and output node NOUT can be connected to an external circuits element 38.When mu balanced circuit 30 is in running order, amplifier circuit 32 can be exported the driving voltage of suitable level, therefore conducting output transistor 34 also adjusts control one output voltage (OutputVoltage) at output node NOUT, the electrical power requirements during 38 work of supply external circuits element.
When desire stops these mu balanced circuit 30 work, starting voltage signal ENABLE can provide a low level DC voltage to amplifier circuit 32, amplifier circuit 32 can be exported the grid of the driving voltage of a high level to output transistor 34 at output terminal Np1 subsequently, to turn-off output transistor 34, no longer conducting first voltage source V CC and output node NOUT are to stop to provide forward voltage to arrive this output node NOUT.At the same time, 40 of phase inverters are the anti-phase starting voltage signal IN_ENABLE of low level starting voltage signal ENABLE conversion high level, and the anti-phase starting voltage signal IN_ENABLE of this high level are sent to the grid of first discharge transistor 41 and second discharge transistor 42.Because first and second discharge transistor 41,42 is N type channel metal oxide semiconductor transistor, anti-phase starting voltage signal IN_ENABLE meeting conducting first discharge transistor 41 of high level, conducting output node NOUT and feedback node NF1, simultaneously, second discharge transistor 42 also can be switched on, this feedback node NF1 and the second voltage source V SS mutual conduction, make the feedback voltage on the feedback node NF1 be dragged down (Pull-down) fast to the low level voltage value that provides near the second voltage source V SS, and because first and second discharge transistor 41,42 all have very little resistance value, the output voltage that is positioned at output node NOUT can be selected by first and second discharge transistor 41,42 rapid discharges, avoid RC circuit in the load blocks 36 to the delay of discharge time, significantly reduced the required time of discharge.
Please note, in present embodiment of the present invention, utilize two discharge transistors (first and second discharge transistor 41,42) setting, and utilize this two discharge transistor 22 (source electrode and drain electrode) in the interconnective design of feedback node NF1, feedback voltage on the feedback node NF1 and the output voltage on the output node NOUT are dragged down in the lump fast, rapid termination work (FastDisable) and two technical characterictics that drag down the feedback voltage of amplifier circuit 32 have fast been implemented simultaneously, based on this, when mu balanced circuit 30 stops work, output node NOUT should be considered as the mutual conduction with feedback node NF1, but not with directly conducting of the second voltage source V SS (ground voltage or default low level voltage).Please continue to consult Fig. 2, for making mu balanced circuit 30 of the present invention have the low noise technical characterictic of feedback, mu balanced circuit 30 also comprises a filter capacitor Cp (BypassCapacitor), this filter capacitor Cp is electrically connected to the second receiving end NA2 of amplifier circuit 32, but the relevant radiofrequency signal of filtering and reduce noise.Please later consult Fig. 1, if desire in conventional structure, to be provided with this filter capacitor Cp, then this filter capacitor Cp can make the speed reduction that the voltage on the second receiving end NA2 is adjusted, speed when having dragged slowly whole mu balanced circuit 30 to stop work simultaneously, yet, in the present invention's mu balanced circuit 30 shown in Figure 3, because feedback voltage can drag down its magnitude of voltage rapidly by second discharge transistor 42, when reducing noise, can not sacrifice the speed of discharge and the efficient of the work of termination, make mu balanced circuit 30 output low noises of the present invention, accurate and stable output voltage.
Based on the mu balanced circuit 30 among above-mentioned Fig. 2 embodiment, and be conceived to the operational scenario of this mu balanced circuit 30 when stopping work, the method embodiment that the present invention is used for stopping fast these mu balanced circuit 30 work can be summarized in the following step, and ask for an interview Fig. 3, Fig. 3 is the process flow diagram of the present invention one method embodiment:
Step 100: beginning, prepare to stop mu balanced circuit 30 work;
Step 102: before with amplifier circuit 32 termination work, mu balanced circuit 30 is at the output voltage of output node NOUT output stable state.When desire stops these mu balanced circuit 30 work, use starting voltage signal ENABLE to stop amplifier circuit 32 work (at this moment, starting voltage signal ENABLE is a low level d. c. voltage signal), make the driving voltage of this amplifier circuit 32 outputs one high level, and then shutoff (finishing) output transistor 34 with a P type channel metal oxide semiconductor transistor, stop conducting first voltage source V CC and output node NOUT proceed to step 104 and step 106 simultaneously;
Step 104: use phase inverter 40 that starting voltage signal ENABLE is converted to anti-phase starting voltage signal IN_ENABLE (high level), make the anti-phase starting voltage signal of this high level IN_ENABLE conducting first discharge transistor 41, conducting output node NOUT and feedback node NF1, this moment output voltage value very near the feedback voltage on this feedback node NF1, and proceed to step 108;
Step 106: the anti-phase starting voltage signal of high level IN_ENABLE conducting second discharge transistor 42 that utilizes phase inverter 40 conversions, the conducting feedback node NF1 and the second voltage source V SS, be pulled down to magnitude of voltage fast so that be positioned at the feedback voltage of this feedback node NF1, carry out step 108 near this second voltage source V SS;
Step 108: after finishing while step 104 and step 106, the output voltage that is positioned at this output node NOUT also can be pulled down to fast near the second voltage source V SS (ground connection or default low) magnitude of voltage, finishes the technical characterictic that the present invention stops mu balanced circuit 30 work rapidly.
In fact, in step 102, when low level starting voltage signal ENABLE is input into amplifier circuit 32, when working to stop amplifier circuit 32, amplifier circuit 32 still need expend the regular hour with output driving voltage transfer high level to by low level, for the quicker amplifier circuit 32 that stops is accurately worked, preferably can be after starting voltage signal ENABLE becomes low level by the high level one in when work, driving voltage can reflect the change of starting voltage signal ENABLE at once, turn-offs output transistor 34 in the shortest time.See also Fig. 4, Fig. 4 is the synoptic diagram of another embodiment of Fig. 3 mu balanced circuit 30 of the present invention.Follow basic structure and the technical characterictic of Fig. 2 embodiment, the mu balanced circuit of Fig. 4 has increased a P type channel metal oxide semiconductor transistor newly more 30, as " stopping transistor 44 ".Grid, drain electrode and the source electrode that stops transistor 44 be electrically connected to respectively the grid of starting voltage signal ENABLE, output transistor 34, with a high level voltage source, when reality was implemented, the available first voltage source V CC provided the voltage of this high level.Under structure disclosed by the invention, stopping transistor 44 can be according to starting voltage signal ENABLE to adjust the value of driving voltage.ENABLE transfers low level to by high level when the starting voltage signal, when desiring to stop amplifier circuit 32 work, conducting simultaneously should stop transistor 44, conducting high level voltage source and drain electrode, make this high level voltage promote the magnitude of voltage of the grid that is positioned at output transistor 34 rapidly, that is, move driving voltage to high level rapidly by low level, with this output transistor 34 of quick shutoff.
Like this,, can in the step 102 of Fig. 3 method embodiment, add a correlation step, ask for an interview Fig. 5 based on the mu balanced circuit 30 of above-mentioned Fig. 4 embodiment.Fig. 5 is the process flow diagram of Fig. 3 other method embodiment, and newly-increased step is:
Step 103: after starting voltage signal ENABLE transfers a low level d. c. voltage signal to by the d. c. voltage signal of a high level, this low level starting voltage signal ENABLE can conducting stop transistor 44, value with the fast lifting driving voltage, turn-off output transistor 34 rapidly, stop conducting this output node NOUT and this first voltage source V CC.
In addition, when reality was implemented, the number of discharge transistor can need not be defined as two according to deviser's increase in demand.By above-mentioned various embodiment as can be known, low noise mu balanced circuit of the present invention is based on the structure of conventional mu balanced circuit, utilize newly-increased arriving to lack two discharge transistors and a filter capacitor, drag down the feedback voltage of amplifier circuit rapidly, and make the output voltage of mu balanced circuit pass through the discharge transistor rapid discharge simultaneously, the technical characterictic that has possessed low noise feedback step-down mechanism (Low-noiseFeedbackPull-low) and quick termination work (FastDisable) simultaneously, further reduce noise and reduce discharge time, reduce unnecessary power loss, make mu balanced circuit of the present invention that low noise can really be provided, accurately, and stable output voltage.
The above only is the preferred embodiments of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (24)
1. a mu balanced circuit is used for exporting at least one output voltage at an output node, and this mu balanced circuit bag includes:
One amplifier circuit comprises one first receiving end and one second receiving end, is used for receiving respectively a reference voltage and a feedback voltage, and this amplifier circuit starts voltage signal to export a driving voltage according to this reference voltage, this feedback voltage and;
One output transistor, comprise three ends, this three end is electrically connected to this amplifier circuit, this output node and one first voltage source respectively, and receives this driving voltage, makes this output transistor control this output voltage at this output node according to this driving voltage operation to adjust;
One first discharge transistor, comprise three ends, this three end is electrically connected to an anti-phase starting voltage signal, this output node and a feedback node respectively, whether this first discharge transistor controls this output node of conducting and this feedback node according to this anti-phase starting voltage signal operation with switch, wherein this feedback node is electrically connected to this second receiving end, can provide this feedback voltage to this amplifier circuit;
One second discharge transistor, comprise three ends, this three end is electrically connected to this anti-phase starting voltage signal, this feedback node and one second voltage source respectively, and this first discharge transistor is used for whether controlling this feedback node of conducting and this second voltage source according to this anti-phase starting voltage signal operation with switch; And
One load blocks is electrically connected to this output node, this feedback node and this second voltage source.
2. mu balanced circuit as claimed in claim 1, it also comprises at least one filter capacitor, is electrically connected to this second receiving end of this amplifier circuit, is used at least one Radio Frequency Interfere of filtering.
3. mu balanced circuit as claimed in claim 1, wherein each transistorized three end is respectively a grid, a drain electrode and an one source pole; In this output transistor, this grid is electrically connected to this amplifier circuit, and this drain electrode is electrically connected to this output node, and this source electrode is electrically connected to this first voltage source; In this first discharge transistor, this grid is electrically connected to this anti-phase starting voltage signal, and this drain electrode is electrically connected to this output node, and this source electrode is electrically connected to this feedback node; In this second discharge transistor, this grid is electrically connected to this anti-phase starting voltage signal, and this drain electrode is electrically connected to this feedback node, and this source electrode is electrically connected to this second voltage source.
4. mu balanced circuit as claimed in claim 3, it comprises that also one stops transistor, this stops transistorized grid, drain electrode and source electrode, be electrically connected to grid and this first voltage source of this starting voltage signal, this output transistor respectively, wherein whether this termination transistor controls this driving voltage of conducting and this first voltage source according to this starting voltage signal operation with switch.
5. mu balanced circuit as claimed in claim 4, wherein when this starting voltage signal stops this amplifier circuit work and this termination transistor of conducting, this this driving voltage of termination transistor controls to be turn-offing this output transistor, with the output voltage that stops this adjustment level at this output node.
6. mu balanced circuit as claimed in claim 4, wherein this first discharge transistor and this second discharge transistor are respectively N type NMOS N-channel MOS N (NMOS) transistor, and this output transistor and this termination transistor are respectively P type NMOS N-channel MOS N (PMOS) transistor.
7. mu balanced circuit as claimed in claim 3, wherein the load blocks bag includes:
One load capacitance is connected between this output node and this second voltage source;
One first pull-up resistor is connected between this output node and this feedback node; And
One second pull-up resistor is connected between this feedback node and this second voltage source, and wherein this first pull-up resistor interconnects in the mode of connecting with this second pull-up resistor.
8. mu balanced circuit as claimed in claim 1, it also includes a phase inverter, be electrically connected to the grid of this first discharge transistor and this second discharge transistor, be used for this starting voltage conversion of signals is this anti-phase starting voltage signal, to provide this anti-phase starting voltage signal to this first discharge transistor and this second discharge transistor.
9. mu balanced circuit as claimed in claim 1, wherein this first voltage source provides the voltage of a high level, and second voltage source provides a ground voltage or a low level voltage.
10. mu balanced circuit as claimed in claim 9, wherein when this starting voltage signal stopped this amplifier circuit work, this driving voltage turn-offed this output transistor, to stop the to provide output voltage of this adjustment level to this output node.
11. mu balanced circuit as claimed in claim 9, wherein when this starting voltage signal stops the work of this amplifier circuit, this this first discharge transistor of anti-phase starting voltage signal conduction, this output node of conducting and this feedback node.
12. mu balanced circuit as claimed in claim 11, wherein when this starting voltage signal stops this amplifier circuit work, this this second discharge transistor of anti-phase starting voltage signal conduction, this feedback node of conducting and this second voltage source are so that the magnitude of voltage that provides near this second voltage source to be provided this feedback voltage fast.
13. mu balanced circuit as claimed in claim 1, wherein this amplifier circuit is an operational amplifier or a differential amplifier.
14. one kind is used for the method that a mu balanced circuit stops this mu balanced circuit work fast, this mu balanced circuit bag includes:
One amplifier circuit is used for exporting a driving voltage according to a starting voltage signal;
One output transistor is electrically connected to this amplifier circuit, an output node and one first voltage source, is used for controlling an output voltage at this output node according to this driving voltage adjustment;
One first discharge transistor is electrically connected to this starting voltage signal, this output node and a feedback node; And
One second discharge transistor is electrically connected to this starting voltage signal, this feedback node and one second voltage source;
This method bag includes:
(a) use this starting voltage signal to stop this amplifier circuit work,, stop adjusting control one output voltage at this output node so that this driving voltage turn-offs this output transistor;
(b) in step (a), use this first discharge transistor of this starting voltage signal conduction, this output node of conducting and this feedback node are pulled down near the magnitude of voltage that is positioned at this feedback node fast so that be positioned at this output voltage of this output node; And
(c) in step (a), use this second discharge transistor of this starting voltage signal conduction, this feedback node of conducting and this second voltage source are pulled down to magnitude of voltage near this second voltage source fast so that be positioned at the magnitude of voltage of this feedback node.
15. method as claimed in claim 14, wherein this amplifier circuit bag comprises one first receiving end and one second receiving end, be used for receiving respectively a reference voltage and a feedback voltage, this second receiving end is electrically connected to this feedback node, make that the magnitude of voltage that is positioned at this feedback node is this feedback voltage, this method also includes:
(d) in step (c), when this this feedback node of second discharge transistor conducting and this second voltage source, this feedback voltage is pulled down to magnitude of voltage near this second voltage source fast.
16. method as claimed in claim 15, wherein this mu balanced circuit also comprises at least one filter capacitor, is electrically connected to this second receiving end of this amplifier circuit, and this method also includes:
(e) in step (d), use at least one Radio Frequency Interfere of this filter capacitor filtering.
17. method as claimed in claim 14, wherein this mu balanced circuit comprises that also one stops transistor, and this termination transistor is electrically connected to this starting voltage signal, this output transistor and this first voltage source, and this method also includes:
(f) in step (a), when this starting voltage signal stopped this amplifier circuit work, conducting should stop transistor with this output transistor of quick shutoff, stopped this output node of conducting and this first voltage source.
18. method as claimed in claim 14, wherein this first voltage source provides the magnitude of voltage of a high level, and second voltage source provides a ground voltage or a low level magnitude of voltage.
19. method as claimed in claim 14, wherein this mu balanced circuit also comprises a load blocks, and this load blocks bag includes:
One load capacitance is connected between this output node and this second voltage source;
One first pull-up resistor is connected between this output node and this feedback node; And
One second pull-up resistor is connected between this feedback node and this second voltage source, and wherein this first pull-up resistor interconnects in the mode of connecting with this second pull-up resistor.
20. method as claimed in claim 14, wherein this mu balanced circuit also includes a phase inverter, is electrically connected to this first discharge transistor and this second discharge transistor, is used for this starting voltage conversion of signals is this anti-phase starting voltage signal, and this method also includes:
(g) in step (b), use this this first discharge transistor of anti-phase starting voltage signal conduction, with this output node of conducting and this feedback node; And
(h) in step (c), use this this second discharge transistor of anti-phase starting voltage signal conduction, with this feedback node of conducting and this second voltage source.
21. method as claimed in claim 14, wherein this output transistor, this first discharge transistor and this second discharge transistor are respectively an oxide-semiconductor transistors or a bipolar junction transistor.
22. method as claimed in claim 21, wherein this first discharge transistor and this second discharge transistor are respectively a N type channel metal oxide semiconductor transistor, and this output transistor is a P type channel metal oxide semiconductor transistor.
23. method as claimed in claim 22, wherein the grid of this output transistor is electrically connected to this amplifier circuit, and the drain electrode of this output transistor is electrically connected to this output node, and the source electrode of this output transistor is electrically connected to this first voltage source; The grid of this first discharge transistor is electrically connected to this starting voltage signal, and the drain electrode of this first discharge transistor is electrically connected to this output node, and the source electrode of this first discharge transistor is electrically connected to this feedback node; The grid of this second discharge transistor is electrically connected to this starting voltage signal, and the drain electrode of this second discharge transistor is electrically connected to this feedback node, and the source electrode of this second discharge transistor is electrically connected to this second voltage source.
24. method as claimed in claim 14, wherein this amplifier circuit is an operational amplifier or a differential amplifier.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101024560A CN100367142C (en) | 2003-10-21 | 2003-10-21 | Low-noise stablized voltage circuit capable of fast stopping working |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101024560A CN100367142C (en) | 2003-10-21 | 2003-10-21 | Low-noise stablized voltage circuit capable of fast stopping working |
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| CN1609743A true CN1609743A (en) | 2005-04-27 |
| CN100367142C CN100367142C (en) | 2008-02-06 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102004514A (en) * | 2006-05-09 | 2011-04-06 | 株式会社理光 | Constant voltage circuit |
| US7973521B2 (en) | 2008-08-08 | 2011-07-05 | Mediatek Inc. | Voltage regulators |
| CN101919148B (en) * | 2008-01-15 | 2013-05-22 | 全视科技有限公司 | Hybrid on-chip regulator for limited output high voltage |
| CN108459644A (en) * | 2017-02-20 | 2018-08-28 | 旺宏电子股份有限公司 | Low voltage difference stable-pressure device and its operating method |
| US10768646B2 (en) | 2017-03-09 | 2020-09-08 | Macronix International Co., Ltd. | Low dropout regulating device and operating method thereof |
| CN113344162A (en) * | 2021-05-19 | 2021-09-03 | 深圳天德钰科技股份有限公司 | Voltage control circuit, display control circuit and electronic tag |
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| US10444780B1 (en) * | 2018-09-20 | 2019-10-15 | Qualcomm Incorporated | Regulation/bypass automation for LDO with multiple supply voltages |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5677642A (en) * | 1994-11-01 | 1997-10-14 | At&T Global Information Solutions Company | Signal generator with supply voltage tolerance |
| KR100289846B1 (en) * | 1998-09-29 | 2001-05-15 | 윤종용 | Low power consumption voltage controller |
| FR2798480B1 (en) * | 1999-09-10 | 2001-10-26 | St Microelectronics Sa | VOLTAGE REGULATOR |
| JP4471451B2 (en) * | 2000-05-22 | 2010-06-02 | 日本テキサス・インスツルメンツ株式会社 | Drive signal supply circuit |
| US6414537B1 (en) * | 2000-09-12 | 2002-07-02 | National Semiconductor Corporation | Voltage reference circuit with fast disable |
| CN1175331C (en) * | 2002-03-28 | 2004-11-10 | 华邦电子股份有限公司 | Voltage regulator having bidirectional current |
| CN1208702C (en) * | 2003-03-06 | 2005-06-29 | 威盛电子股份有限公司 | Voltage stabilizing circuit with current mirror to compensate current and prevent initial overcurrent and its contol method |
| CN1209691C (en) * | 2003-03-06 | 2005-07-06 | 威盛电子股份有限公司 | Prechargeable voltage stabilizing circuit and relevant method |
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2003
- 2003-10-21 CN CNB2003101024560A patent/CN100367142C/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102004514A (en) * | 2006-05-09 | 2011-04-06 | 株式会社理光 | Constant voltage circuit |
| CN101341452B (en) * | 2006-05-09 | 2011-06-01 | 株式会社理光 | Constant voltage circuit |
| CN101919148B (en) * | 2008-01-15 | 2013-05-22 | 全视科技有限公司 | Hybrid on-chip regulator for limited output high voltage |
| US7973521B2 (en) | 2008-08-08 | 2011-07-05 | Mediatek Inc. | Voltage regulators |
| CN108459644A (en) * | 2017-02-20 | 2018-08-28 | 旺宏电子股份有限公司 | Low voltage difference stable-pressure device and its operating method |
| US10768646B2 (en) | 2017-03-09 | 2020-09-08 | Macronix International Co., Ltd. | Low dropout regulating device and operating method thereof |
| CN113344162A (en) * | 2021-05-19 | 2021-09-03 | 深圳天德钰科技股份有限公司 | Voltage control circuit, display control circuit and electronic tag |
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