CN1209691C

CN1209691C - Prechargeable voltage stabilizing circuit and relevant method

Info

Publication number: CN1209691C
Application number: CN 03106872
Authority: CN
Inventors: 林有为
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2003-03-06
Filing date: 2003-03-06
Publication date: 2005-07-06
Anticipated expiration: 2023-03-06
Also published as: CN1432884A

Abstract

The present invention provides a voltage stabilizing circuit and a relative control method to provide DC stabilized voltage. The voltage stabilizing circuit comprises a bipolar junction transistor for providing charge current, a capacitive circuit, an operational amplifier, a reference voltage circuit and a precharge circuit, wherein the capacitive circuit can stabilize output voltage; the operational amplifier can control the base bias of the bipolar junction transistor according to the stabilized voltage to obtain exact stabilized voltage output. When the voltage stabilizing circuit begins to run, the operational amplifier is firstly prohibited to not conduct the bipolar junction transistor, the precharge circuit firstly provides precharge current for the capacitive circuit to establish voltage before the capacitive circuit, and then the operational amplifier is used for controlling the bipolar junction transistor to begin to provide charged current for the capacitive circuit and establish stabilized voltage in a steady state.

Description

Prechargeable voltage stabilizing circuit and relevant method

Technical field

The invention provides a kind of mu balanced circuit (regulator) and corresponding control methods that is used for the chip biasing, refer in particular to a kind of can the charging to electric capacity of voltage regulation earlier, prevent excessive mu balanced circuit and the corresponding control methods of conduction of current transistor initial current in the mu balanced circuit with pre-charge circuit.

Background technology

In modern information society, electronic message unit of all kinds (little as mobile phone, greatly to computing machine, the webserver) all is based on various micro controller systems: micro controller system can normally be moved, also just become one of most important research emphasis of modern information industry.

In general, various micro controller systems all are being that one or more chip to be installed on the circuit board (similarly being printed circuit board (PCB)) comes specific implementation on the hardware.In order to improve the integrated level of semiconductor circuit in the chip, reduce power consumption, increase arithmetic speed, the core circuit (core circuit) that is used for carrying out data operation, data processing in the chip all can be setovered with lower voltage, and the voltage level of electronic signal is also lower.But the data in the core circuit to be exported to the outer circuit board of chip, or data are inputed to chip when handling by circuit board, signal higher with voltage level usually, that power is bigger just has enough signal driving forces, so an output/input circuit (i/o buffer) can be set in the chip in addition, go into the usefulness of buffering as output.Because the handled electronic data of core circuit, signal have lower voltage level; In the time of these data, signal will being transferred to external world's (similarly being circuit board), output again after will these data, voltage of signals level, power being improved by output/input circuit.In like manner, also can its signal level be reduced,, make things convenient for core circuit to carry out data processing to meet the lower bias voltage of core circuit by the pending data, signal that the external world transfers to core circuit 14 by output/input circuit.Provide core circuit and output/input circuit different bias voltages, will produce a lower voltage of voltage regulation according to higher DC voltage with a mu balanced circuit usually, and respectively with this DC voltage and this voltage of voltage regulation setover output/input circuit and core circuit.In known technology, mu balanced circuit is to be realized by a Zener diode (Zener Diode), and this diode one end reverse bias is in DC voltage, and the other end just can be exported the voltage of voltage regulation that size is the difference of voltage between this DC voltage and this diode two ends.

Yet so known mu balanced circuit can not stably be kept voltage of voltage regulation accurately, and the voltage of voltage regulation of its output is also unstable.

Summary of the invention

Therefore, fundamental purpose of the present invention is to provide a kind of mu balanced circuit that accurate, stable voltage of voltage regulation can be provided with feedback controling mode, to overcome the shortcoming of known technology.

In prototype mu balanced circuit of the present invention, be to come the capacitance module charging with the bipolar junction transistor in FEEDBACK CONTROL one charging circuit, to set up, to keep voltage of voltage regulation with the size that an operational amplifier detects the voltage of voltage regulation that capacitance module sets up.But at the beginning of bringing into operation, because voltage of voltage regulation is extremely low, the possibility of result of operational amplifier FEEDBACK CONTROL can excessively drive charging circuit, makes a large amount of electric current of charging circuit conducting, causes bipolar junction transistor to burn easily.

Therefore, the present invention easily proposes the mu balanced circuit after the improvement, be before charging circuit begins the capacitance module charging, earlier capacitance module to be charged with a pre-charge circuit earlier, so that in capacitance module, set up the voltage a little less than the stable state voltage of voltage regulation, not yet temporary transient the startup earlier of this moment operational amplifier and charging module.By the time voltage of voltage regulation rises to a certain preset value, enable (enable) operational amplifier and charging circuit (also make simultaneously pre-charge circuit out of service) again, in subsequent process, set up, keep the voltage of voltage regulation of stable state by the FEEDBACK CONTROL of operational amplifier with the control charging circuit.Because when operational amplifier brought into operation, voltage of voltage regulation had risen to preset value, operational amplifier just can be maintained at the electric current of bipolar junction transistor conducting in the scope of safe operation, can excessively not drive the bipolar junction transistor in the charging circuit.Thus, just can avoid the shortcoming in the prototype mu balanced circuit, and provide chip correct, stable bias voltage.

Description of drawings

Fig. 1 is the function block schematic diagram of a prototype mu balanced circuit structure between a chip and a circuit board.

Fig. 2 is the function block schematic diagram of mu balanced circuit structure of the present invention between a chip and a circuit board.

Fig. 3 is the circuit diagram of operational amplifier one embodiment among Fig. 2.

Fig. 4 is the circuit diagram of control circuit one embodiment among Fig. 2.

Fig. 5 is the time dependent sequential synoptic diagram of associated voltage when mu balanced circuit moves among Fig. 2.

The reference numeral explanation

10,30 chips, 12,32 circuit boards

14,34 core circuits, 16,36 output/input circuits

18,38 mu balanced circuits, 20,40 operational amplifiers

22,42 reference voltage generators, 24,46 capacitance modules

48 control circuits, 50 support circuits

52 phase inverters, 54 rejection gates

56 inner pre-charge circuit t0-t1, tp time point

Ic0-Ic1, Ic, Ipc, Ir electric current

Vreg0, Vreg, Vop, Vopb, Vs0, Vs voltage

Vbg0, Vbg reference voltage Op0, Op output terminal

Vp25, V25 voltage of voltage regulation Vcc, Vss Dc bias

Vd0, Vd driving voltage Cp1, C1 electric capacity

Np1-Np2, N0-N10 node R p0-Rp1, R0-R1 resistance

Inn, Inp input end dashed curve Vc2p

V25m, V25s, V25mp voltage level

Qp1-Qp2, Q1-Q3, T1-T14, S1-S7, M1-M11 transistor

Embodiment

Please refer to Fig. 1.Being in the micro controller system of Fig. 1 signal, a chip 10 cooperates the functional block diagram of a circuit board 12 operations.For instance, circuit board 12 can be a motherboard, and 10 of chips can be the chips of being located on the motherboard (similarly being the north and south bridge chip); Perhaps circuit board 12 also can be the printed circuit board (PCB) on the auxiliary insert card (add-on card similarly is a network card), and chip 10 is exactly the function that is used for controlling this auxiliary insert card.As previously mentioned, promptly be provided with a core circuit 14 and an output/input circuit 16 in the chip 10.Core circuit 14 is mainly used to carry out data operation and data processing.To export the data of circuit board 12 after core circuit 14 is handled to, or will import pending data into, then all will carry out the buffering of data and the conversion of signal via output/input circuit 16 to core circuit 14 via circuit board 12.Just as above-mentioned, core circuit 14 can be offset to lower voltage, and handled electronic data, signal also have lower voltage level; To will these data, voltage of signals level, power be improved by output/input circuit 16, so that transfer on the circuit board 12 with these data, when signal transfers to circuit board 12.In like manner, also can its signal level be reduced,, make things convenient for core circuit 14 to carry out data processing to meet the lower bias voltage of core circuit 14 by the pending data, signal that circuit board 12 transfers to core circuit 14 by output/input circuit 16.

Because the direct swap data of output/input circuit 16 and circuit board 12 energy on circuit design, output/input circuit 16 is offset to identical voltage usually with circuit board 12; DC voltage Vcc among Fig. 1, Vss (voltage that DC voltage Vss can hold with regarding as) promptly are used for the output/input circuit 16 in biasing circuit plate 12 and the chip 10.But, as previously mentioned, core circuit 14 can the lower DC voltage of biasing, and therefore, chip 10 will cooperate circuit board 12 to be combined into a mu balanced circuit 18, to produce the voltage of voltage regulation Vp25 core circuit 14 of setovering.With typical example, circuit board 12 can provide the Dc bias (just DC voltage Vcc is 3.3 volts) of 3.3 volts (volt) to chip 10, and core circuit 14 then can be offset to lower 2.5 volts; In this configuration, mu balanced circuit 18 will utilize 3.3 volts DC voltage Vcc, produce 2.5 volts voltage of voltage regulation V25, the electricity needs when core circuit 14 operations are provided.

As shown in Figure 1, in mu balanced circuit 18, can use on the circuit board 12 one in order to bipolar junction transistor Qp1 that electric current and pressure drop are provided as a charging circuit, and have a high capacity capacitor C p1 as a capacitance module 24.Cooperate transistor Qp1, capacitance module 24 on the circuit board 12, then be provided with an operational amplifier 20, a reference voltage generator (bandgap circuit) 22 in the chip 10 and be used for two resistance R p0, Rp1 of dividing potential drop.Mu balanced circuit 18 is offset between DC voltage Vcc, the Vss; Wherein reference voltage generator 22 is used for producing a reference voltage Vbg0; 20 of operational amplifiers have two differential input terminals (being denoted as "+", "-" among Fig. 1 respectively), are electrically connected to the reference voltage output of node Np1 and reference voltage generator 22 respectively; Output terminal Op0 then is electrically connected to the base stage (base) of transistor Qp1, and with a driving voltage Vd0 as a drive signal, the base bias of oxide-semiconductor control transistors Qp1.When reality is implemented, for example, can be provided with a pin (pin) on the chip 10, so that output terminal Op0 can connect the transistor Qp1 to the circuit board 12.The emitter-base bandgap grading of transistor Qp1 (emitter) is offset to DC voltage Vcc, and collector (collector) then is electrically connected to capacitance module 24 in node Np0.Be provided with the capacitor C p1 of a high capacity in the capacitance module 24, be used for voltage stabilizing, but and the interference of bypass (bypass) AC ripple; After capacitor C p1 is charged to stable state, just can set up the voltage of voltage regulation Vp25 of stable state at node Np0.And capacitance module 24 can be back in the chip 10 via another corresponding pin of chip 10 at the voltage of voltage regulation Vp25 of node Np0.This voltage of voltage regulation Vp25 can provide on the one hand to the voltage of core circuit 14 as biasing, also can set up a voltage Vs0 at node Np1 via the dividing potential drop of resistance R p0, Rp1 on the one hand.Behind operational amplifier 20 comparison reference voltage Vbg0, the voltage Vs0, just the energy FEEDBACK CONTROL is to the driving voltage Vd0 of transistor Qp1.

The situation of mu balanced circuit 18 operations can be described below: when circuit board 12 will make chip 10 bring into operation, the DC voltage Vcc that can begin high level is provided brought into operation mu balanced circuit 18 to mu balanced circuit 18.This moment, reference voltage generator 22 and operational amplifier 20 also can bring into operation, by the voltage Vs0 of operational amplifier 20 beginning comparison node Np1 and the reference voltage Vbg0 of reference voltage generator 20 generations.Because before mu balanced circuit 18 brought into operation, node Np0 was maintained low level (level of DC voltage Vss), voltage Vs0 also is maintained at low level jointly; Therefore when operational amplifier 20 had just brought into operation, operational amplifier 20 can also can be low level voltage because voltage Vs0 makes the driving voltage Vd0 of its output terminal Op0 much smaller than reference voltage Vbg0.At this moment, voltage between transistor Qp1 emitter-base bandgap grading, base stage also just almost is equivalent to the voltage difference between DC voltage Vcc, Vss, and make a large amount of electric current I c0 of transistor Qp1 conducting as charging current, high capacity capacitor C p1, the Cp2 charging in capacitance module 24.Along with the carrying out of charging process, the voltage of node Np0 can rise gradually, and the voltage Vs0 of node Np1 also can rise gradually; And operational amplifier 20 also will increase the driving voltage Vd0 of its output terminal Op0.The rising of driving voltage Vd0 can reduce the voltage between transistor Qp1 emitter-base bandgap grading, base stage, reduces its conducting degree, and the size of current of electric current I c0 is also reduced gradually.Via the detection feedback to voltage Vs0, the size of operational amplifier 20 meeting controlling and driving voltage Vd0 makes the voltage Vp25 of node Np0 be tending towards the definite value of stable state gradually.When having arrived stable state, operational amplifier 20 can be kept voltage Vs0 and equate with reference voltage Vbg0; In other words, voltage Vp25 also just equals voltage (1+Rp0+Rp1) Vbg0.The voltage Vp25 of this stable state just can be as the Dc bias of core circuit 14, and required electric current I c1 during core circuit 14 operations is also just provided by transistor Qc1 adjusting.When the voltage swing idol of voltage Vp25 changed, operational amplifier 20 controlling and driving voltage Vd0 accordingly compensated dynamically.For instance, if core circuit 14 strengthens the electric current demand because of operand, this moment, capacitor C p2 can prevent that the voltage Vp25 of node Np0 from descending suddenly apace, and the voltage Vp25 that slightly falls can make voltage Vs0 descend jointly, driving voltage Vd0 is descended, and make voltage microlitre between transistor Qp1 emitter-base bandgap grading, base stage, increase the electric current I c0 of transistor Qp1 conducting, the electricity needs that increases with response core circuit 14.

But, though the prototype mu balanced circuit 18 among Fig. 1 can produce the voltage of voltage regulation Vp25 of the stable state core circuit 14 of setovering, but this technology might have a latent defect, be exactly that mu balanced circuit 18 can be first aspire to the bigger electric current of transistor Qp1 conducting what move at the beginning, cause transistor Qp1 to be burnt easily.As previously mentioned, when mu balanced circuit 18 has just brought into operation because the voltage of node Np0 is low level, jointly operational amplifier 20 in the driving voltage Vd0 of output terminal Op0 also near low level; So voltage difference between DC voltage Vcc, Vss no better than just of the voltage between transistor Qp1 emitter-base bandgap grading, base stage.With aforesaid exemplary, the voltage difference between DC voltage Vcc, Vss has 3.3 volts; And under general situation, as long as the voltage between transistor Qp1 emitter-base bandgap grading, base stage has 0.7 to 0.8 volt, just can the suitable electric current of conducting.In comparison, the electric current of steady-state circuit 18 conducting at the beginning of operation significantly surmounts the electric current of transistor Qp1 required conducting under the operate as normal situation in fact as can be known.And so big electric current may easily just burn transistor Qp1 at the beginning of mu balanced circuit 18 operations.

Therefore, the present invention also proposes the mu balanced circuit of an improvement.Please refer to Fig. 2.Fig. 2 is established in the function block schematic diagram of 32 of a chip 30 and circuit boards for mu balanced circuit 38 of the present invention.Based on the configuration of modern microcontroller, also be provided with core circuit 34 and output/input circuit 36 in the chip 30; Core circuit 34 runs on lower voltage of voltage regulation V25, and output/input circuit 36 and circuit board 32 are the same to use higher DC voltage Vcc to setover; Dc bias Vss then holds the zero voltage reference of (ground) with can be considered.In order to produce core circuit 34 employed voltage of voltage regulation V25, the present invention also is provided with a mu balanced circuit 38 between chip 30 and circuit board 32, set up voltage of voltage regulation V25 with the Dc bias Vcc that provides according to circuit board 32.Mu balanced circuit 38 of the present invention is offset between DC voltage Vcc, the Vss (for instance, DC voltage Vcd can be 3.3 volts a voltage, corresponding DC voltage Vss then is 0 volt a voltage reference), it has comprised the reference voltage generator 42 that is arranged in the chip 30, operational amplifier 40, control circuit 48, as the n-type metal oxide semiconductor transistor Q3 of pre-charge circuit and be used for resistance R 0, the R1 of dividing potential drop; Cooperate foregoing circuit, also comprise a bipolar junction transistor Q1 and a capacitance module 46 on the circuit board 32 in order to electric current and suitable pressure drop to be provided.Reference voltage generator 42 is used for producing a reference voltage Vbg.40 of operational amplifiers are provided with two differential positive-negative input end Inp, Inn and output terminal Op; Wherein input end Inn promptly is used for accepting reference voltage Vbg, and input end Inp then is electrically connected to node N1.When operational amplifier 40 operations, can be worse than output terminal Op according to the voltage of two input end Inp, Inn and export a corresponding driving voltage Vd as a drive signal.

The base stage of transistor Q1 is controlled by the driving voltage Vd of operational amplifier 40 output terminal Op output; When reality is implemented, for instance, on the chip 30 pin can be set so that output terminal Op can outwards be electrically connected to the base stage of transistor Q1.The emitter-base bandgap grading of transistor Q1 then is offset to DC voltage Vcc, and collector then is electrically connected to node N0; According to the control of driving voltage Vd, transistor Q1 can provide a charging current Ic to inject node N0.Be provided with the capacitor C 1 of high capacity in the capacitance module 46, be used for voltage stabilizing, but and the unnecessary interchange of bypass disturb, make the voltage of node N0 be maintained at a stationary value easily; Utilize capacitance module 46 to be used as load, mu balanced circuit 38 can be set up voltage of voltage regulation V25 at node N0.Node N0 can be electrically connected to the node N3 in the chip 30 by another pin on the chip 38, and the voltage of voltage regulation V25 of node N0 is back to core circuit 34, with biasing core circuit 34; Resistance R 0, R1 also can divide an extrusion voltage Vs (making voltage Vs equal R1/ (R0+R1) V25) at node N1 according to voltage of voltage regulation V25 simultaneously, and voltage Vs are transferred to the input end Inp of operational amplifier 40.

In the present invention, control circuit 48 generation voltage signal Vpc, Vop and Vopb are as control signal; Transistor Q2 then is used for as a pre-charge circuit, and its drain bias is in DC voltage Vcc, and body (body) is offset to DC voltage Vss, and grid is controlled by the voltage Vpc that control circuit 48 produces, and source electrode then is electrically connected to node N3; The foregoing circuit structure can make the control of the controlled circuit 48 of transistor Q3 and provide a pre-charge current Ipc to inject node N3.And operational amplifier 40 is accepted the control of voltage Vop and Vopb in addition, operational amplifier 40 is under an embargo (disable) and out of service, or enables and bring into operation.In preferred embodiment of the present invention, operational amplifier 40 is under an embargo and when not moving, can exports the voltage (voltage level of DC voltage Vcc just) of a high level regularly at its output terminal Op, to turn-off transistor Q1.When operational amplifier 40 is enabled and after bringing into operation, can be worse than output terminal Op according to the voltage of two input end Inp, Inn and export corresponding driving voltage Vd.

Cooperate above-mentioned configuration among the present invention, the principle of mu balanced circuit 38 operations of the present invention can be described below.When circuit board 32 will make chip 30 bring into operation, can begin provided DC voltage Vcc to chip 30 and mu balanced circuit 38.Control circuit 48 meetings this moment are under an embargo with voltage Vop, Vopb control operational amplifier 40 earlier and do not move; As previously mentioned, operational amplifier 40 can be exported the driving voltage Vd of a high level at output terminal Op when being under an embargo, and making transistor Q1 jointly is zero not conducting electric current because of voltage essence between emitter-base bandgap grading, base stage.In the 40 controlled forbidden whiles of operational amplifier, control circuit 48 also can be with the voltage Vpc oxide-semiconductor control transistors Q3 conducting of high level.So that pre-charge current Ipc to be provided, charge to capacitance module 46 via node N3, N0.In other words, not conducting of transistor Q1 at this moment, but by transistor Q conducting pre-charge current Ipc, come to capacitance module 46 chargings.Along with transistor Q3 continues to capacitance module 46 chargings, the voltage of voltage regulation V25 of node N0 also can the low level (level of DC voltage Vss) when initial begin to rise.Control circuit 48 also can continue to estimate the amplitude of voltage of voltage regulation V25 rising simultaneously, estimates that up to control circuit 48 voltage of voltage regulation V25 have been increased to a certain preset value; In preferred embodiment, it can be a magnitude of voltage a little less than stable state voltage of voltage regulation V25.By the time control circuit 48 estimates that voltage of voltage regulation V25 has been increased to this preset value, control circuit 48 will change the voltage swing of each signal Vop, Vopb and Vpc, operational amplifier 40 is enabled and brought into operation, transistor Q3 then turn-offs not conducting and stops to provide pre-charge current Ipc.After operational amplifier 40 brings into operation, will produce corresponding driving voltage Vd with the voltage difference of reference voltage Vbg according to voltage Vs, begin conducting charging current Ic to capacitance module 46 chargings with oxide-semiconductor control transistors Q1, final operational amplifier 40 can dynamically be kept the voltage of voltage regulation V25 of a voltage stabilizing, makes the steady state voltage size of voltage of voltage regulation V25 be maintained at voltage (1+R0/R1) Vbg.

By foregoing description as can be known, mu balanced circuit 38 of the present invention is at the beginning of bringing into operation and voltage of voltage regulation V25 (and voltage Vs) when being zero, can not start the FEEDBACK CONTROL between operational amplifier 40, transistor Q1, make operational amplifier 40 can be because of bigger voltage difference between voltage Vs and reference voltage Vbg yet excessive driving transistors Q1.Make the 40 forbidden whiles of operational amplifier, the present invention then be with transistor Q3 as a pre-charge circuit, provide pre-charge current Ipc to capacitance module 46 with to capacitor C 1, C2 charging, the voltage of voltage regulation V25 that makes node N0 is gradually by low accurate the rising.By the time after voltage of voltage regulation V25 rises to preset value, control circuit 48 will stop to provide pre-charge current Ipc with signal Vpc oxide-semiconductor control transistors not conducting of Q3, simultaneously also utilize signal Vop, Vopb that operational amplifier 40 is enabled, allow the FEEDBACK CONTROL between operational amplifier 40, transistor Q1 bring into operation, the foundation of catcher voltage of voltage regulation V25 and stable state voltage of voltage regulation V25 keep.That is to say, when operational amplifier 40 brings into operation, voltage of voltage regulation V25 no longer is low level voltage, and the voltage difference between voltage Vs and reference voltage Vbg furthers, and this also makes the driving voltage Vd of operational amplifier 40 outputs can be higher than low level voltage.So, when driving voltage Vd oxide-semiconductor control transistors Q1 began conducting, the too small shortcoming of the initial voltage between emitter-base bandgap grading, base stage just was improved, and transistor Q1 is the conducting excessive electric current with regard to can excessively not driven also.

Fig. 3 is the circuit diagram of operational amplifier 40 1 specific embodiments among the present invention, and Fig. 4 then is the circuit diagram of control circuit 48 1 specific embodiments among the present invention.As shown in Figure 3, operational amplifier 40 of the present invention is offset between DC voltage Vcc, the Vss, is the main fundamental structure that forms operational amplifier with n-type metal oxide semiconductor transistor T1, T2, T5 to T8, T12, T14 and p type metal oxide semiconductor transistor T 3, T4, T9 to T11 and T13; N-type metal oxide semiconductor transistor S1 to S3, S7 and p type metal oxide semiconductor transistor S4 to S5 are then as switching transistor, and operational amplifier 40 can the controlled needs that are under an embargo, enable among the present invention to cooperate.The body of each n-type metal oxide semiconductor transistor is with DC voltage Vss biasing, and the transistorized body of each p type metal oxide semiconductor is then setovered with DC voltage Vcc.It is one differential right that transistor T 1, T2 form, respectively with the grid of transistor T 1, T2 input end Inp, the Inn as operational amplifier 40.With differential to the transistor T 5 that is electrically connected to node N5 as a current source biasing, its grid also is electrically connected to node N6 jointly with the grid of transistor T 6, T7, T14, forms a current mirror.Support circuits 50 can produce an electric current I r as the reference electric current, by the above-mentioned differential size for node N5 bias current of current mirror control.Transistor T 3, T4 be as differential right active load, and its grid also is electrically connected jointly with the grid of transistor T 9, T11, forms another current mirror.In gross, transistor T 1 to T5 forms the differential input level of operational amplifier 40, its preliminary amplifying signal can be done secondary amplification by transistor T 6 to T11, and transistor T 13, T12 be as AB class (class AB) output stage of operational amplifier 40, and with node N8 as output terminal Op.

With the transistor T 1 to T14 that forms the amplifier body structure relatively, transistor S1 to S7 is then as switch, the bias voltage of oxide-semiconductor control transistors T1 to T14 grid is respectively enabled or is under an embargo with further control operational amplifier 40.The wherein signal Vop of the controlled circuit 48 of the grid of transistor S1, S2, S7 control (please also refer to Fig. 2), the signal Vopb control of the then controlled circuit 48 of the grid of transistor S3 to S5.Operational amplifier 40 is subjected to signal Vop, Vopb control and the operation situation that is under an embargo, enables can be described as follows.When control circuit 48 will make operational amplifier 40 be under an embargo, can make signal Vop was high level, and signal Vopb is a low level; The whole conductings of transistor S1 to S7 this moment.Transistor S1, the S3 of conducting can be pulled low to the voltage of node N6 low level DC voltage Vss, makes transistor T 5 to T7, the neither conducting of T14, and the electric current I r that support circuits 50 produces also can flow to the transistor S3 of conducting, can inflow transistor T14.In like manner, the transistor S2 of conducting and S7 can be respectively be pulled low to low level with the grid voltage of transistor T 8 and T12, and these two transistors are turn-offed; 10 conductings of transistor T.Transistor S4, the S5 of conducting then draws high the grid of transistor T 3, T4, T9, T11 the DC voltage Vcc to high level, and these four transistors are turn-offed and not conducting.The transistor T 10 of conducting cooperates the transistor T 11 of not conducting, can make the grid voltage of transistor T 13 be pulled to low level, make transistor T 13 conductings, and the voltage (just driving voltage Vd sees Fig. 2) of output terminal Op is drawn high the DC voltage Vcc to high level.At the beginning of mu balanced circuit 38 of the present invention brought into operation, operational amplifier 40 can be under an embargo earlier, and the high level driving voltage Vd voltage of its output terminal Op just can make between transistor Q1 emitter-base bandgap grading, base stage voltage minimum, allowed also not conducting of transistor Q1.

Relatively, when control circuit 48 will be controlled operational amplifier 40 and enables, voltage Vop can be upgraded to high level, voltage Vopb is a low level, this moment, each transistor S1 to S7 can turn-off and not conducting, no longer influence the grid bias of transistor T 1 to T14, and transistor T 1 to T14 just can join together to carry out the normal function of operational amplifier 40, according to the voltage difference between two differential input terminal Inp, Inn with in the corresponding driving voltage Vd of output terminal Op output.

As shown in Figure 4, control circuit 48 among the present invention is provided with n-type metal oxide semiconductor transistor M1 to M3, M5, M6, M9 to M11, p type metal oxide semiconductor transistor M4, M7 and M8, and be offset to phase inverter 52, rejection gate 54 between DC voltage Vcc, Vss.The transistorized body bias of each p type metal oxide semiconductor is in DC voltage Vcc, and the body of each n-type metal oxide semiconductor transistor then is offset to DC voltage Vss.The grid of transistor M1, M2 and M3 all is electrically connected to DC voltage Vcc, forms an inner pre-charge circuit 56, is electrically connected to node N9 with the grid of transistor M6; The drain electrode of transistor M6, the equal common bias of source electrode form an electric capacity in DC voltage Vss, with as one second capacitance module.Inner pre-charge circuit 56 can charge to the electric capacity that transistor M6 forms, to set up a voltage Vc2 at node N9.Transistor M7, M9, M10 are connected to the circuit of a phase inverter kenel, receive the voltage of voltage Vc2 as input with grid, and will be used for the voltage Vpc (please also refer to Fig. 2) of oxide-semiconductor control transistors Q3 at node N10 output control circuit 48.Via rejection gate 54, two phase inverters 52, control circuit 48 just can utilize voltage Vpc to produce two other control signal Vop and Vopb, enables or is under an embargo with control operational amplifier 40.

The waveform sequential chart of each interdependent node change in voltage when Fig. 5 moves for mu balanced circuit 38 of the present invention; The transverse axis of each waveform is the time, and the longitudinal axis is the size of voltage; From top to bottom block curve is used for representing voltage of voltage regulation V25, voltage Vreg, control circuit 48 builtin voltage Vc2 (being shown in Fig. 4) and control circuit 48 to be used for signal Vpc, Vop and the Vopb of oxide-semiconductor control transistors Q3, operational amplifier 40 respectively among Fig. 5.Below will utilize Fig. 5 that the situation of control circuit 48 (as Fig. 4) and even whole mu balanced circuit 38 (as Fig. 2) operation further is discussed.As shown in Figure 5, suppose chip 30 is brought into operation at time point t0 circuit board 32; Just as discussed earlier, this moment, circuit board 32 began to provide DC voltage Vcc to mu balanced circuit 38.When time point t0, low level voltage Vreg make transistor M4, M8 conducting (please refer to Fig. 4) in the control circuit 48, transistor M5, M11 then turn-off and between drain electrode, source electrode just as open circuit (open); Inner pre-charge circuit 56 also can begin conducting one electric current I pc2 because of the biasing of DC voltage Vcc as one second pre-charge current simultaneously, be injected into the grid of transistor M6 by node N9, the electric capacity that forms with respect to transistor M6 charges, and makes the voltage Vc2 of node N9 be begun to rise by low level.But, when time point t0, the voltage of node N9 is low level voltage still, this low level voltage can make transistor M7 conducting, and transistor M9, M10 turn-off, and make the voltage Vpc of node N10 be pulled to high level, voltage Vop also is the high level (voltage level of DC voltage Vcc just jointly, as indicating among Fig. 5), the phase inverter 52 in the control circuit 48 then make signal Vopb be low level (voltage level of DC voltage Vss, such as among Fig. 5 sign).As previously mentioned, the voltage Vpc of high level meeting turn-on transistor Q3 (please refer to Fig. 2) makes transistor Q3 begin conducting pre-charge current Ipc, and capacitance module 46 is begun charging, and makes voltage V25 begin to rise.Simultaneously, signal Vop is that high level, signal Vopb are that low level then can make operational amplifier 40 be under an embargo and out of service, and, transistor Q1 is also turn-offed and not conducting (please refer to Fig. 2, Fig. 3 and related description) in the driving voltage Vd of output terminal Op output high level.

Just as shown in Figure 5, after time point t0, along with the charging of 56 couples of transistor M6 of inner pre-charge circuit, the voltage Vc2 of node N9 also can be raise gradually by low level, is elevated at time point t1 at last to make transistor M7 change shutoff into by conducting.Also make transistor M9, M10 change conducting into by original shutoff, the voltage Vpc of the node N10 high level since by time point t0 is pulled low to low level, voltage Vop also changes low level into by high level jointly, and voltage Vopb also simultaneously changes high level at time point t1 into by low level.In addition, between time point t0 to t1, inside pre-charge circuit 56 (see figure 4)s in control circuit 48 are the electric capacity charging that transistor M6 is formed, transistor Q3 as pre-charge circuit in mu balanced circuit 38 (see figure 2)s is also charging to the capacitor C in the capacitance module 46 1, C2 simultaneously, makes the voltage of voltage regulation V25 of node N0 also be begun to rise by the low level voltage of time point t0; Arrived time point t1, voltage of voltage regulation V25 also rises to a voltage level V25m.Because the change of voltage Vpc, Vop and Vopb when time point t1, transistor Q3 turn-offs and conducting pre-charge current Ipc no longer, and operational amplifier 40 begins to enable after time point t1, and beginning FEEDBACK CONTROL, to adjust of the charging of driving voltage Vd driving transistors Q1 catcher to capacitance module 46, make voltage of voltage regulation V25 behind time point t1, continue to rise to the voltage level V25s (see figure 5) of stable state, and dynamically steady state voltage V25 is maintained at the voltage level V25s of this stable state by the FEEDBACK CONTROL of operational amplifier 40; This steady state voltage level V25s also just equals voltage (1+R0/R1) Vbg; For instance, the steady state voltage level is 2.5 volts, after the voltage of voltage regulation V25 of stable state sets up by the time, just can be used for having operated core circuit 34.

As seen from the above description, between time point t0 and t1, steady state voltage V25 is that the transistor Q3 by pre-charge circuit sets up; By the time operational amplifier 40 after the time point t1, when transistor Q1 brings into operation, steady state voltage V25 has risen to voltage level V25m, low level voltage when no longer being time point t0.When operational amplifier 40 when time point t1 begins according to the big or small FEEDBACK CONTROL of steady state voltage V25 the driving of transistor Q1, just do not use low level driving voltage Vd and come excessive driving transistors Q1, and transistor Q1 can not burn because of the electric current of conducting is excessive yet.In addition, as shown in Figure 5, change the speed that voltage Vc2 sets up in the control circuit 48, just can control the opportunity that operational amplifier 40, transistor Q1 bring into operation.For instance, if the voltage upcurve of voltage Vc2 is shown in dashed curve Vc2p, just be increased at time point tp and make voltage Vpc, Vop be reduced to low level by high level, and make voltage Vopb be increased to high level by low level, so steady state voltage V25 can just be taken over by operational amplifier 40, transistor Q1 when rising to voltage level V25mp and continue to set up, keep voltage of voltage regulation V25.In other words, want oxide-semiconductor control transistors Q3, Q1 when voltage of voltage regulation V25 rises to a certain preset value, to join operation, can adjust the speed of 56 pairs of transistor M6 chargings of inner pre-charge circuit in the control circuit 48, make voltage Vc2 rise to be enough to that the transistor Q3 of pre-charge circuit just also charged to capacitance module 46 voltage of this preset value when trigger voltage Vpc, Vop and Vopb changed.So also just can suitably arrange operational amplifier 40 in the size of back that bring into operation to the driving voltage Vd of transistor Q1.And to adjust the speed that 56 couples of transistor M6 of inner pre-charge circuit charge, can suitably adjust the size of inner pre-charge circuit 56 conducting electric currents and the capacitance of transistor M6.For instance, if the electric current I pc2 of pre-charge circuit 56 conductings be transistor Q3 pre-charge current Ipc 1/10th, and the equivalent capacitance value of transistor M6 also is 1/10th of capacitance module 46 equivalent capacitance value, and then the ascending velocity of voltage Vpc2 (ratio that magnitude of voltage increased in the unit interval) will be identical with the ascending velocity of voltage of voltage regulation V25 when transistor Q3 moves; So just can utilize the ascending velocity of voltage Vpc2 to estimate the ascending velocity of voltage of voltage regulation V25, and control the opportunity of transistor Q3, Q1 handing-over operation.

With known technology relatively, the present invention is that the mode with FEEDBACK CONTROL provides more accurate, stable voltage of voltage regulation.Though in prototyping technique, because mu balanced circuit its operational amplifier when moving at the beginning of prototype will come the driving of FEEDBACK CONTROL to its bipolar junction transistor Qp1 according to low level steady state voltage, tend to excessive driving transistors Qp1 at the beginning of bringing into operation, transistor Qp1 is burnt, make mu balanced circuit can't set up voltage of voltage regulation smoothly, core circuit in the chip also just can not obtain bias voltage, also can't trouble-free operation.And the present invention be with transistor Q3 as pre-charge circuit, before operational amplifier, bipolar junction transistor Q1 bring into operation, promptly earlier voltage of voltage regulation is promoted to a certain degree; By the time after operational amplifier brought into operation, just excessive driving transistors Q1 not prevented that transistor Q1 from burning, and keeps the follow-up normal operation of mu balanced circuit of the present invention, guarantees that the core circuit in the chip can obtain correct, stable bias voltage.

The above only is preferred embodiment of the present invention, and all equivalences of making according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.

Claims

One kind can precharge mu balanced circuit, be used to provide a voltage of voltage regulation, this mu balanced circuit includes:

One capacitance module has a high capacity capacitor, and utilization receives the electric charge that a charging current provided and sets up this voltage of voltage regulation;

One charging circuit comprises a transistor, is electrically connected to this capacitance module, and after the second predetermined baseline behind first a predetermined baseline when beginning to switch on, this charging circuit can produce this charging current by this transistor; And

It is characterized in that, also include a pre-charge circuit, have another transistor, be electrically connected to this capacitance module, the first predetermined baseline that is used to rise when switching at the beginning provides a pre-charge current to this capacitor one input end by this another transistor.
2. mu balanced circuit as claimed in claim 1, wherein the pre-charge current that provides of this pre-charge circuit can make this voltage of voltage regulation rise; When this voltage of voltage regulation rose to a predeterminated voltage, this pre-charge circuit can stop this pre-charge current is provided, and this charging circuit can begin to provide this charging current to this input end.
3. mu balanced circuit as claimed in claim 1, wherein this charging circuit can change the size of this charging current according to a drive signal; And this mu balanced circuit includes an operational amplifier in addition, is used for producing this drive signal accordingly according to this voltage of voltage regulation.
4. mu balanced circuit as claimed in claim 3, wherein this operational amplifier is to produce this drive signal accordingly according to the voltage difference between this voltage of voltage regulation and a reference voltage.
5. mu balanced circuit as claimed in claim 3, wherein when this voltage of voltage regulation rose, the corresponding drive signal that this operational amplifier produces can make this charging circuit reduce this charging current; And the pre-charge current that this pre-charge circuit provides can just make this voltage of voltage regulation rise before this charging circuit begins to provide this charging current.
6. mu balanced circuit as claimed in claim 3, it includes a control circuit in addition, is used for controlling this pre-charge circuit and this operational amplifier; When this mu balanced circuit brought into operation, this control circuit can make this pre-charge circuit begin to provide this pre-charge current earlier, and the while also makes this operational amplifier be under an embargo and do not produce this drive signal, so that this charging circuit does not provide this charging current.
7. mu balanced circuit as claimed in claim 6, wherein the pre-charge current that provides of this pre-charge circuit can make this voltage of voltage regulation rise; And this control circuit can be estimated the amplitude that this voltage of voltage regulation rises; After this control circuit makes this pre-charge circuit begin to provide this pre-charge current and estimates that this voltage of voltage regulation has risen to a predeterminated voltage, this control circuit can make this pre-charge circuit stop to provide this pre-charge current, also enable simultaneously this operational amplifier, make this operational amplifier begin to produce this drive signal, and make this charging circuit begin to provide this charging current according to this voltage of voltage regulation.
8. a method that is used for a mu balanced circuit is used for controlling this mu balanced circuit one voltage of voltage regulation is provided, and wherein this mu balanced circuit includes:

One capacitance module, it is provided with an input end, is used for receiving an electric current; The electric charge that is provided by this electric current can be provided this capacitance module, and sets up this voltage of voltage regulation accordingly;

One charging circuit is electrically connected to this input end, is used for providing a charging current to this input end; And

One pre-charge circuit is electrically connected to this input end, is used to provide a pre-charge current to this input end;

And this method includes: before making this charging circuit begin to provide this charging current, make this pre-charge circuit begin to provide this pre-charge current earlier.
9. method as claimed in claim 8, wherein the pre-charge current that provides of this pre-charge circuit can make this voltage of voltage regulation rise; And this method includes in addition: when this voltage of voltage regulation rises to a predeterminated voltage, make this pre-charge circuit stop to provide this pre-charge current, and make this charging circuit begin to provide this charging current to this input end.
10. method as claimed in claim 8, wherein this charging circuit can change the size of this charging current according to a drive signal; And this mu balanced circuit includes an operational amplifier in addition, is used for producing this drive signal accordingly according to this voltage of voltage regulation.