JPS5996865A - Power source - Google Patents
Power sourceInfo
- Publication number
- JPS5996865A JPS5996865A JP20668582A JP20668582A JPS5996865A JP S5996865 A JPS5996865 A JP S5996865A JP 20668582 A JP20668582 A JP 20668582A JP 20668582 A JP20668582 A JP 20668582A JP S5996865 A JPS5996865 A JP S5996865A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistor
- power source
- sub
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、安定化電源のための閉ループを構成するスイ
ッチング電源回路を備えた電源装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a power supply device including a switching power supply circuit forming a closed loop for a stabilized power supply.
従来例の構成とその問題点
一般的に使用される、閉ループをもったスイッチング安
定化電源回路を第1図に示す。(VCC)ははバッテリ
ー等の安定化されていない入力電源端子、(V、 )は
安定化された出力電源端子である。(1)は発振器、(
2)は発振器(1)にニジトリガーされるにぎ9波発生
回路、(3)は電圧比較器で、差動アンプ(4)の出力
電圧値により設定される電位vcとのこぎり波発生回路
(2)の電圧とを比較して矩形波出力を出力し、反転ア
ンプ(5)、抵抗(rl)を介してスイッチング素子で
あるトランジスタ(Q2)のベース入力とし、トランジ
スタ(Q2)を導通させる。トランジスタ(Q2)が導
通することにより抵抗(R2) k介して出力トランジ
スタ(Ql)のベース電流が流れ、トランジスタ(Ql
)が導通する。このように出力トランジスタ(Ql)に
矩形波出力が得られ、ダイオード(D+)、インダクタ
(Ll)、コンデンf(Ct)で構成されるフィルタに
て平滑されてDC!圧にされ、出力電源端子(vo)に
直流電圧■。が出力される。この出力電源端子(VO)
に出力される出力■。は可変抵抗(VRI)を介して差
動アンプ(4)に入力され、基準電圧発生器(6)の出
力vRと比較されることにより閉ループ金構成している
。この回路の負荷特性を第2図に示す。Conventional configuration and its problems A commonly used closed-loop switching stabilization power supply circuit is shown in FIG. (VCC) is an unregulated input power terminal such as a battery, and (V, ) is a regulated output power terminal. (1) is an oscillator, (
2) is a sawtooth wave generation circuit that is triggered by the oscillator (1), and (3) is a voltage comparator that compares the potential vc set by the output voltage value of the differential amplifier (4) with the sawtooth wave generation circuit (2). ) and outputs a rectangular wave output, which is input to the base of a transistor (Q2) which is a switching element via an inverting amplifier (5) and a resistor (rl), thereby making the transistor (Q2) conductive. When the transistor (Q2) becomes conductive, the base current of the output transistor (Ql) flows through the resistor (R2), and the transistor (Ql)
) conducts. In this way, a rectangular wave output is obtained at the output transistor (Ql), and it is smoothed by a filter consisting of a diode (D+), an inductor (Ll), and a capacitor f (Ct), and the DC! DC voltage is applied to the output power terminal (vo). is output. This output power terminal (VO)
■ Output output to. is input to the differential amplifier (4) via a variable resistor (VRI) and compared with the output vR of the reference voltage generator (6) to form a closed loop circuit. The load characteristics of this circuit are shown in FIG.
上記スイッチング方式の安定電源は効率がよいため、発
熱も少なく、コン/(クトに構成できる75玉、回路的
に複雑になり易い。また出力電圧の異なった負荷(回路
)や、起動時に大電流力;流れる負荷(モーター、プラ
ンジャー等)をつなく゛場合には、第1図に示す回路と
同じ構成のものを2系統必要と1電源回路が非常に複雑
になるという問題カニあった0
発明の目的
本発明は上記従来の欠点を解消するもので、主回路に簡
単な構成の副回路を付加するだけで、品11回路の負荷
としてのモーター等の負荷変動の影響発明の構成
上記目的を達するため、本発明の電源装置は、閉ループ
を構成するスイッチング電源回路力)ら成る主回路の出
力段をドライブ゛するスイッチンク゛素子と並列に、別
の出力段から成る副回路をドライブするスイッチング素
子を接続し、前記副回路により前記主回路とは異った電
圧の準安定化電源を構成したものである。The above switching type stable power supply is highly efficient, generates little heat, and can be easily configured with 75 circuits, making it easy to complicate the circuit.Also, it is difficult to handle loads (circuits) with different output voltages and large currents at startup. When connecting a flowing load (motor, plunger, etc.), there was a problem in that two systems with the same configuration as the circuit shown in Figure 1 were required, making one power supply circuit extremely complicated. Purpose The present invention solves the above-mentioned conventional drawbacks, and achieves the above-mentioned object by simply adding a sub-circuit with a simple configuration to the main circuit. Therefore, in the power supply device of the present invention, a switching element that drives a sub-circuit consisting of another output stage is connected in parallel with a switching element that drives an output stage of a main circuit consisting of a switching power supply circuit forming a closed loop. However, the sub-circuit constitutes a quasi-stable power supply with a voltage different from that of the main circuit.
実施例の説明
以下、本発明の一実施例について、図面に基づいて説明
する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第3図は電源装置の回路図で、(Vo )は出力電源端
子、(Qi)はトランジスタ、(Rr)(Rj)は抵抗
、(D2)はダイオード、(R2)はインタ“フタ、(
C2)はコンデンサであり、これらにより構成された砧
IJ回路力玉第1図に示す主回路に付加されたものであ
る。Figure 3 is a circuit diagram of the power supply device, in which (Vo) is the output power terminal, (Qi) is the transistor, (Rr) (Rj) is the resistor, (D2) is the diode, (R2) is the interface lid, (
C2) is a capacitor, which is added to the main circuit shown in FIG. 1 of the Kinuta IJ circuit shown in FIG.
ここで、主回路と副回路との定数力(同じであれば、副
回路の負荷特性は144図に示すような準安定化の特性
をもつ。しかしこのままでは、負仙電流It、 = I
t、であれば出力電圧V□=Voである力;、IL>I
XであればvO<■dとなり、逆に’lL<IL’であ
ればvO>Voとなってし1う。これは、出力段のトラ
ンジスタ(Ql)、(Q7)の重連時の電圧ドロップや
Δト滑フィルタ(LIXCI) 、(R28C2)の直
流抵抗分の電圧ドロップが負荷電流により変わるために
主回路と畠IJu路との電圧ドロップに差力;でるので
、それ第五出力電圧に現われるのである。このような場
合、11回路の出力電圧に自由度がないため最大効率を
得るだめの定格電圧を得ることができない。Here, if the constant power of the main circuit and the sub-circuit is the same, the load characteristic of the sub-circuit will have a quasi-stabilizing characteristic as shown in Fig. 144. However, if this continues, the negative current It, = I
t, then the output voltage V□=Vo; IL>I
If X, then vO<■d, and conversely, if 'IL<IL', then vO>Vo. This is because the voltage drop when the output stage transistors (Ql) and (Q7) are connected in parallel, and the voltage drop due to the DC resistance of the delta tosliding filter (LIXCI) and (R28C2) vary depending on the load current. Since there is a voltage drop with the Hatake IJu path, it appears in the fifth output voltage. In such a case, since there is no degree of freedom in the output voltage of the 11 circuits, it is not possible to obtain the rated voltage required to obtain the maximum efficiency.
そこで、主回路の抵抗(R1)を例えば68011と大
きくしておき、トランジスタ(Ql)のコレクタ波形の
デユーティを第9図のように(t+tx)として、可変
抵抗(VRt )にて出力電圧■0を設定する。そして
副回路の抵抗(R()を主回路の抵抗(R1)より小さ
く(例えば220Ω)にすると、トランジスタ(Ql)
のコレクタのデユーティ−は第10図のように(1+1
2)と短くなシ、出力電圧■6を出力電圧■0よりも低
くするこきができる。また逆に高くすることもできる。Therefore, the resistance (R1) of the main circuit is made large, for example, 68011, and the duty of the collector waveform of the transistor (Ql) is set (t+tx) as shown in Figure 9, and the output voltage is Set. Then, if the resistance (R()) of the sub circuit is made smaller (for example, 220Ω) than the resistance (R1) of the main circuit, the transistor (Ql)
The duty of the collector is (1+1
2) In short, it is possible to make the output voltage (6) lower than the output voltage (2) 0. Conversely, it can also be made higher.
これは出力段のトランジスタ(Ql)(Qlの再結合時
間を利用したもので、理想的には第6図の波形になるが
、実際にはトランジスタ(Ql)のエミッタ・ベース間
の抵抗(R1)を変えると第7図のように可変すること
ができる。しかしその幅は数μs 程になので、スイッ
チング周波数は100 KHz(T=10μs)程度高
くないと効果は少ない。なお第7図において、tlはR
1= 330Ω、t2はR1=680Ω、t3はR1=
1200Ωの場合をそれぞれ示している。また第5図
及び第8図はトランジスタ(Q2)のコレクタ波形図で
ある。This utilizes the recombination time of the output stage transistor (Ql) (Ql), and ideally the waveform is as shown in Figure 6, but in reality the resistance (R1) between the emitter and base of the transistor (Ql) is ) can be varied as shown in Fig. 7. However, since the width is about several μs, the effect is small unless the switching frequency is about 100 KHz (T = 10 μs). In Fig. 7, tl is R
1=330Ω, t2 is R1=680Ω, t3 is R1=
The case of 1200Ω is shown in each case. Further, FIGS. 5 and 8 are collector waveform diagrams of the transistor (Q2).
発明の詳細
な説明したように本発明によれば、閉ループを構成する
スイッチング電源から成る主回路に簡単な構成の副回路
を付加するだけで、副回路により、主回路に影響を及ぼ
さずに出力電圧を可変することができる準安定化電源を
構成し得、したがって蘭回路の負荷としてのモーター等
の負荷変動の影響が主回路側へ及ぶことがないと共に、
定格負荷に対して最大効率を得ることができる。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by simply adding a sub-circuit with a simple configuration to the main circuit consisting of a switching power supply forming a closed loop, the sub-circuit can generate output without affecting the main circuit. It is possible to configure a semi-stabilized power supply that can vary the voltage, so that the influence of load fluctuations such as the motor as a load of the circuit does not affect the main circuit side,
Maximum efficiency can be obtained for the rated load.
第1図は従来装置の回路図、第2図は第1図に示す回路
の負荷電流特性の説明図、第3図は本発明の一実施例に
おける電源装置の回路図、第4図は第3図に示す回路の
負荷電流特性の説明図、第5図はトランジスタ(Q2)
のコレクタ波形図、第6図はトランジスタ(Ql)の理
想的なコレクタ波形図、第7図はトランジスタ(Ql)
の実際のコレクタ波形図、第8図はトランジスタ(Q2
)のコレクタ波形図、第9図はトランジスタ(Ql)の
実際のコレクタ波形図、第10図はトランジスタ(Ql
)のコレクタ波形図である。
(Ql)(01′XQ2)・・・トランジスタ、(DI
)(D2)・・・ダイオード、(LIXL2)・・・イ
ンダクタ、(CIXC2)・・・コンデyf、(VRI
) =−6f 変抵抗、(RxXRi)(R2)(R
j)−抵抗
代理人 森 本 義 弘
第を図
第2図
第3図
第を図
第7図FIG. 1 is a circuit diagram of a conventional device, FIG. 2 is an explanatory diagram of load current characteristics of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a power supply device according to an embodiment of the present invention, and FIG. An explanatory diagram of the load current characteristics of the circuit shown in Figure 3, Figure 5 is the transistor (Q2)
Figure 6 is the ideal collector waveform diagram of the transistor (Ql), Figure 7 is the ideal collector waveform diagram of the transistor (Ql).
Figure 8 shows the actual collector waveform diagram of the transistor (Q2
), Figure 9 is the actual collector waveform diagram of the transistor (Ql), and Figure 10 is the collector waveform diagram of the transistor (Ql).
) is a collector waveform diagram. (Ql) (01'XQ2)...transistor, (DI
) (D2)...Diode, (LIXL2)...Inductor, (CIXC2)...Conductor yf, (VRI
) = -6f Variable resistance, (RxXRi) (R2) (R
j) - Resistance agent Yoshihiro Morimoto Figure 2 Figure 3 Figure 7
Claims (1)
主回路の出力段をドライブするスイッチング素子と並列
に、別の出力段から成る副回路をドライブするスイッチ
ング素子を接続し、前記副回路によシ前記主回路とは異
なった電圧の準安定化電源を構成した電源装置。1. Connect a switching element that drives a sub-circuit consisting of another output stage in parallel with a switching element that drives an output stage of a main circuit consisting of a switching power supply circuit constituting a closed loop, and connect the switching element that drives a sub-circuit consisting of another output stage, and A power supply device configured as a quasi-stable power supply with a voltage different from that of the circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20668582A JPS5996865A (en) | 1982-11-24 | 1982-11-24 | Power source |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20668582A JPS5996865A (en) | 1982-11-24 | 1982-11-24 | Power source |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5996865A true JPS5996865A (en) | 1984-06-04 |
JPH0124028B2 JPH0124028B2 (en) | 1989-05-09 |
Family
ID=16527412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20668582A Granted JPS5996865A (en) | 1982-11-24 | 1982-11-24 | Power source |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5996865A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005245158A (en) * | 2004-02-27 | 2005-09-08 | Ricoh Co Ltd | Motor driver, digital camera, and motor control method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5465324A (en) * | 1977-11-02 | 1979-05-25 | Hirobumi Matsuo | Multiple output direct current power converter |
JPS5892017A (en) * | 1981-11-27 | 1983-06-01 | Matsushita Electric Ind Co Ltd | Power supply device |
-
1982
- 1982-11-24 JP JP20668582A patent/JPS5996865A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5465324A (en) * | 1977-11-02 | 1979-05-25 | Hirobumi Matsuo | Multiple output direct current power converter |
JPS5892017A (en) * | 1981-11-27 | 1983-06-01 | Matsushita Electric Ind Co Ltd | Power supply device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005245158A (en) * | 2004-02-27 | 2005-09-08 | Ricoh Co Ltd | Motor driver, digital camera, and motor control method |
JP4541723B2 (en) * | 2004-02-27 | 2010-09-08 | 株式会社リコー | Motor drive device, digital camera, and motor control method |
Also Published As
Publication number | Publication date |
---|---|
JPH0124028B2 (en) | 1989-05-09 |
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