JP2003088105A - Switching regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching regulator capable of reducing circuit area by making unneeded a soft-start circuit that occupies a large area. SOLUTION: This switching regulator is provided with a first circuit to which an inductor 4 and a switching element 7 are connected in series; a second circuit structured in such a way that a rectifying device 5 is connected in series to a capacitor 6, the one end of the rectifying device side is connected to the one end of the switching element, and the other end of the capacitor side is connected to the other end of the switching element; and a third circuit that controls the switching element by the output of an AND circuit, by using a logic level signal corresponding to the mutual connection point of the rectifying device and the capacitor as one input to the AND circuit 16, and by using as the other input to the AND circuit a rectangular wave signal whose logic level changes based on a specified duty ratio, by counting the output signal of an oscillating circuit 12 that oscillates by a specified frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a switch circuit for switching a power inputted from the outside to form a pulse current, converting the pulse current into a direct current and outputting the direct current, and a constant output voltage. The present invention relates to a switching regulator that controls switching operation.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing the structure of a conventional switching regulator of this type. In the figure,
The switching regulator 1a includes a power supply voltage input terminal 2 for supplying electric power from the outside and a boosted voltage output terminal 3 for outputting a voltage boosted with respect to a reference voltage to the outside. Of these, one end of an inductor 4 is connected to the power supply voltage input terminal 2, one end of a switching transistor 7 composed of an N-channel MOS transistor is connected to the other end, and the other end of the switching transistor 7 is grounded. In addition, the diode 5 is connected to the other end of the inductor 4.
Of the diode 5 is connected to the boosted voltage output terminal 3 and the other end is connected to one end of the capacitor 6 which is grounded. And
A switching pulse control circuit 8a for controlling ON / OFF of the switching transistor 7 according to the voltage of the boosted voltage output terminal 3 is provided.

This switching pulse control circuit 8a has two
The resistors 9a and 9b are connected in series, one end of which is connected to the boosted voltage output terminal 3, that is, the interconnection point of the diode 5 and the capacitor 6, and the other end of which is grounded. Then, the resistors 9a and 9b of the voltage dividing circuit 9
The interconnection point of is connected to the negative side input terminal (−) of the error amplification circuit 11 configured by using an operational amplifier. The positive input terminal (+) of the error amplification circuit 11 is connected to the positive electrode of the DC power supply 10 that generates a reference voltage, and the negative electrode thereof is grounded. Further, at the output end of the error amplifier circuit 11, P
The positive side input terminal of the PWM comparator 13a having a WM (pulse width modulation) function is connected, and the negative side input terminal of the PWM comparator 13a is connected to the output terminal of the oscillation circuit 12 that generates a triangular wave signal. The output terminal of the PWM comparator 13a is the control input terminal of the switching transistor 7, that is, the N channel M
It is connected to the gate of the OS transistor.

The operation of the switching regulator 1a configured as described above will be described below with reference to the time chart shown in FIG. First, the external power supply voltage Vdd
Is supplied to the power supply voltage input terminal 2. At this time, a current flows into the capacitor 6 via the inductor 4 and the diode 5, which causes the voltage RG of the boosted voltage output terminal 3 to flow.
Vout gradually increases, but its absolute value is small. Therefore, the voltage Va divided by the voltage dividing circuit 9 applied to the error amplifying circuit 11 also becomes low. Error amplifier circuit 11
Outputs a voltage according to the difference between the reference voltage Vref of the DC power supply 10 added to this and the divided voltage Va,
The output voltage Vfb decreases as the difference (Vref-Va) increases, and the output voltage Vfb increases as the difference (Vref-Va) decreases.

Therefore, immediately after the voltage is supplied to the power supply voltage input terminal 2, the value of the output voltage Vfb of the error amplifier circuit 11 is relatively large, and this voltage Vfb is added as one input of the PWM comparator 13a. At this time, the triangular wave signal Vosc of the oscillation circuit 12 is added as the other input of the PWM comparator 13a. The PWM comparator 13a outputs a signal of logic level "H" when there is a relationship of Vfb> Vosc between the voltage Vfb applied to it and the triangular wave signal Vosc, and when it has a relationship of Vfb <Vosc, on the contrary. A signal of level "L" is output. As a result, as shown in FIG. 4, while the triangular wave signal Vosc is lower than the voltage Vfb, the switching transistor 7 is turned on (described as ON in the drawing), and the triangular wave signal Vos is turned on.
A switching pulse Vsw for turning off the switching transistor 7 (described as OFF in the drawing) is output while c is higher than the voltage Vfb.

When the switching transistor 7 is turned on, the inductor 4 and the switching transistor 7 are turned on.
Current flows through the switching transistor 7, and when the switching transistor 7 is turned off in this state, the energy stored in the inductor 4 causes the capacitor 6 to pass through the diode 5 through the diode 5.
Since a current flows through the battery to charge it, the voltage RGVout of the boosted voltage output terminal 3 also gradually increases as the voltage across the battery rises. Note that the longer the ON time of the switching transistor 7, the larger the energy stored in the capacitor 6 by one switching operation, that is, the current flowing through the inductor 4, and the larger the boosted amount of the voltage RGVout at the boosted voltage output terminal 3. .

FIG. 4 is a time chart showing the voltage waveform of each part of the switching regulator 1a. The divided voltage Va of the voltage dividing circuit 9 also rises in proportion to the rise of the voltage RGVout of the boosted voltage output terminal 3. When the difference from the reference voltage Vref decreases as the voltage Va increases, the output voltage Vfb of the error amplifier circuit 11 gradually decreases. As a result, the switching pulse V output from the PWM comparator 13a
The duty ratio of sw becomes small, and the boosted amount by one switching operation of the switching transistor 7 also becomes small. On the contrary, if the voltage RGVout of the boosted voltage output terminal 3 decreases, the duty ratio of the switching pulse Vsw output from the PWM comparator 13a increases, and the boosted amount by one switching operation of the switching transistor 7 also increases.

Finally, the voltage RGV shown in the following equation
controlled by out. RGVout = Vref (r1 + r2) / r2 (1) where r1: the resistance value of the resistor 9a forming the voltage dividing circuit 9 and r2: the resistance value of the resistor 9b forming the voltage dividing circuit 9.

By the way, in the above-mentioned conventional switching regulator 1a, the voltage RGVout becomes the minimum at the start of the step-up operation for supplying power to the power supply voltage input terminal 2 to generate the voltage at the step-up voltage output terminal 3. Therefore, there is a problem that the duty ratio of the switching pulse Vsw becomes the maximum and a large inrush current flows through the inductor 4 to lower the power supply voltage Vdd or destroy the inductor 4 and the capacitor 6.

FIG. 5 is a circuit diagram showing the configuration of another conventional switching regulator proposed to solve this problem. In the figure, the same elements as those shown in FIG. 3 are the same. And the description thereof will be omitted. This switching regulator 1b is provided with a soft start circuit 20 in the switching pulse control circuit 8b, and instead of the PWM comparator 13a in FIG. 3, the output of the error amplification circuit 11 is the first input and the output of the soft start circuit 20 is the first input. A PWM comparator 13b having two inputs and an output of the oscillation circuit 12 as a third input is used. Of these, the soft start circuit 20 is the current source 2
One end of a capacitor 22 whose other end is grounded is connected to the output terminal of 1, and the voltage generated at one end of the capacitor 22 is applied as a second input of the PWM comparator 13b.

When the output voltage of the soft start circuit 20 is Vsof, the PWM comparator 13b outputs Vf
When b> Vosc and Vsof> Vosc, an “H” level switching pulse Vsw is output, and Vfb <Vosc
Alternatively, when Vsof <Vosc, the "L" level switching pulse Vsw is output.

FIG. 6 is a time chart showing the output voltage of the soft start circuit 20 in consideration of Vsof and corresponding to FIG. In this case, the voltage RGVout of the boosted voltage output terminal 3, the reference voltage Vref, the divided voltage Va, and the output voltage Vfb of the error amplification circuit 11 are the same as those described with reference to FIG. On the other hand, the capacitor 22 is the current source 2
1 is charged, and the output voltage Vsof gradually rises. Therefore, the pulse width of the switching pulse Vsw is extremely narrow at the beginning and then gradually widens, whereby gentle boosting is performed, so that the rush current to the inductor 4 is suppressed. Such an operation is performed when Vsof <Vfb, and thereafter, when Vsof> Vfb, the operation switches to the operation described with reference to FIG.

When a switching regulator is actually used, a load is connected to the boosted voltage output terminal 3 which outputs the voltage RGVout, and the energy stored in the capacitor 6 is reduced by the amount consumed by the load. The detailed value of the internal voltage and the circuit constant in the switching pulse control circuit 8b are designed to generate the switching pulse Vsw having the optimum duty ratio or the optimum frequency according to the value of the voltage RGVout or the fluctuation of the load current.

[0014]

The switching regulator 1b shown in FIG. 5 is provided with a soft start circuit 20, and the duty ratio of the switching pulse Vsw is gradually increased until the output voltage thereof exceeds the output voltage Vfb of the error amplification circuit 11. With such a configuration, it is possible to suppress the inrush current immediately after the supply of the power supply voltage Vdd to the power supply voltage input terminal 2 is started. However, since most of the switching pulse control circuit 8b is composed of analog circuits, the problem that the circuit area occupied by the soft start circuit 20 and the like increases when the switching regulator 1b is formed on the semiconductor substrate is a problem to be solved. Had.

The present invention has been made to solve the above problems, and when the load current is constant or changes little, the soft start circuit occupying a large area becomes unnecessary, thereby making the circuit unnecessary. It is an object of the present invention to provide a switching regulator whose area can be reduced.

[0016]

In order to achieve the above object, a switching regulator according to a first aspect of the present invention is a switching regulator in which an inductor and a switching element are connected in series, a rectifying element and a capacitor are connected in series, The voltage at the interconnection point of the rectifying element and the capacitor is divided from the second circuit configured by connecting one end on the rectifying element side to one end of the switching element and connecting the other end on the capacitor side to the other end of the switching element. The logic level signal corresponding to the difference between the value obtained by pressing and the reference voltage is used as one input of the AND circuit, and the output signal of the oscillation circuit that oscillates at a predetermined frequency is counted and the logic level is determined at the predetermined duty ratio. And a third circuit for controlling the switching element by the output of the AND circuit, which receives the changing rectangular wave signal as the other input of the AND circuit. As a result, the circuit elements that occupy a large area, such as the soft start circuit and the PWM comparator, can be replaced with digital circuits that occupy a small area, and optimal switching pulses can be logically synthesized, thus reducing the circuit area. can do.

Next, in the switching regulator according to the second aspect, as the digital circuit used in the third circuit, the duty ratio corresponding to the ON period is set as time elapses at the start of ON / OFF control of the switching element. The configuration is such that the soft start circuit occupies a large area when the load current is constant or changes little.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below in detail based on the preferred embodiments shown in the drawings. FIG. 1 is a circuit diagram showing the overall configuration of a switching regulator according to the present invention. In the figure, the same elements as those of FIG. 3 or FIG. 5 showing the conventional apparatus are designated by the same reference numerals, and the description thereof will be omitted. Figure 1
The switching regulator 1 shown in (1) includes a switching pulse control circuit 8 having a different configuration from the switching pulse control circuit 8a or 8b constituting the conventional device, and the other parts are configured the same as the conventional device.

In the switching pulse control circuit 8, two resistors 9a and 9b are connected in series, one end of which is connected to the boosted voltage output terminal 3, that is, an interconnection point of the diode 5 and the capacitor 6, and the other end. Is provided with a voltage dividing circuit 9 which is grounded. The resistors 9a and 9 of the voltage dividing circuit 9 are
The interconnection point of b is connected to the negative side input terminal (−) of the comparator 14. The positive input terminal (+) of the comparator 14 is connected to the positive electrode of the DC power supply 10 that generates a reference voltage, and the negative electrode thereof is grounded. further,
The output terminal of the comparator 14 is connected to one input terminal of the AND circuit 16.

The output signal of the oscillator circuit 12 is applied to the digital circuit 15 as a clock signal. Digital circuit 15
Outputs a rectangular wave signal of a pattern predetermined by simulation or the like, that is, a rectangular wave signal whose duty ratio gradually increases as time passes, and its output terminal is connected to the other input terminal of the AND circuit 16. ing. The output terminal of the AND circuit 16 is connected to the control input terminal of the switching transistor 7, that is, the gate of the N-channel MOS transistor.

The series connection circuit of the inductor 4 and the switching transistor 7 described above corresponds to the first circuit of the present invention, and the series connection circuit of the diode 5 and the capacitor 6 corresponds to the second circuit of the present invention. The switching pulse control circuit 8 corresponds to the third circuit of the present invention. The operation of the embodiment configured as described above will be described especially for the switching pulse control circuit 8 having a different configuration from the conventional device. This switching regulator 8
Is also configured to be stable according to the relationship of the following formula (2). RGVout = Vref (r1 + r2) / r2 (2) where r1: the resistance value of the resistor 9a forming the voltage dividing circuit 9 and r2: the resistance value of the resistor 9b forming the voltage dividing circuit 9.

Here, the relation of the equation (2) is not satisfied, and for example, the voltage of the boosted voltage output terminal 3 increases and the following (3)
Suppose that the relationship shown in the formula is established. RGVout> Vref. (R1 + r2) / r2 (3) In this case, the output voltage Vcpo of the comparator 14 becomes "L" level. In this state, even if the output Vpls of the digital circuit 15 is at "H" level, the switching pulse Vsw output from the AND circuit 16 becomes "L" level and the switching transistor 7 is turned off.

On the contrary, it is assumed that the voltage at the boosted voltage output terminal 3 is lowered and the relationship shown in the following equation (4) is established. RGVout <Vref. (R1 + r2) / r2 (4) In this case, the output voltage Vcpo of the comparator 14 becomes the "H" level. Therefore, the switching transistor 7 is also controlled to be turned on / off in accordance with the on / off operation of the output Vpls of the digital circuit 15.

On the other hand, in this embodiment, as shown in FIG. 2, the digital circuit 15 outputs a rectangular wave signal having a small duty ratio in a constant period t1 after the switching operation is started, and It is set to output a rectangular wave signal having a larger duty ratio in the constant period t2, and to output a rectangular wave signal having a larger duty ratio in the subsequent constant period t3. Therefore, while the output voltage PGVout of the boosted voltage output terminal 3 is in the relationship satisfying the above expression (4), the switching pulse Vsw synchronized with the output Vpls of the digital circuit 15 is applied to the control terminal of the switching transistor 7 to perform this switching. The transistor 7 is turned on and off.

With such a configuration, an increase in inrush current to the inductor 4 is prevented, and at the same time, a circuit element having a large occupied area such as the soft start circuit 20 and the PWM comparator 13b shown in FIG. Optimal switching pulse Vsw by replacing with circuit
Can be logically synthesized.

As described above, according to the embodiments described with reference to FIGS. 1 and 2, the soft start circuit occupying a large area becomes unnecessary when the load current is constant or the fluctuation is small. By doing so, the circuit area can be reduced.

Although the above embodiment has described the case where the positive voltage is boosted and output, the present invention is not limited to this application, and a P-channel MOS transistor is used as the switching transistor 7. ,
It can also be applied to a device that boosts and outputs a negative voltage by connecting the diode 5 with an inverse characteristic. Further, the switching transistor 7 is not limited to the MOS transistor, and a bipolar transistor may be used.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a switching regulator according to the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a conventional switching regulator.

FIG. 4 is a time chart for explaining the operation of the switching regulator shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of another conventional switching regulator.

6 is a time chart for explaining the operation of the switching regulator shown in FIG.

[Explanation of symbols]

1 Switching regulator 2 Power supply voltage input terminal 3 Boosted voltage output terminal 4 inductor 5 Diode (rectifier element) 6 capacitors 7 Switching transistor (switching element) 8 Switching pulse control circuit 9 voltage divider 10 DC power supply 12 Oscillation circuit 14 Comparator 15 Digital circuit 16 AND circuit

Claims (2)

[Claims] 1. A first circuit in which an inductor and a switching element are connected in series, a DC voltage is applied to both ends thereof, a rectifying element and a capacitor are connected in series, and one end of the rectifying element side is connected to the inductor. A second circuit connected to one end of the switching element, the other end of the capacitor side being connected to the other end of the switching element, and the rectifying element connected with a polarity that suppresses a decrease in the current of the inductor; A voltage dividing terminal that divides the voltage of the voltage output terminal by using an interconnection point of the rectifying element and the capacitor as a voltage output terminal,
A comparator that outputs a logic level signal by comparing the voltage divided by the voltage dividing resistor with a reference voltage, an oscillation circuit that oscillates at a predetermined frequency, and an output signal of the oscillation circuit that counts and outputs a logic signal at a predetermined duty ratio. A digital circuit that outputs a rectangular wave signal whose level changes, and an output of the comparator as one input and an output of the digital circuit as the other input, and outputs a logical product signal of these two inputs,
Turning on the switching element according to the AND signal,
And a third circuit including a logical product circuit that performs off control. 2. The switching regulator according to claim 1, wherein the digital circuit gradually increases the duty ratio corresponding to the ON period with the passage of time at the start of ON / OFF control of the switching element.