JP2001086740A - Dc-dc converter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a control signal to a high frequency for miniaturizing parts, without reducing the voltage conversion efficiency, and to minimize a circuit. SOLUTION: As a switching element for stepping-down/stepping-up, an NMOS transistor is used. When an input voltage is higher than a prescribed output voltage by the error signal of an error amplifier, a control signal is outputted from a PWM comparator 5, a drive signal is generated from a gate drive circuit 8, and an NMOS 10 for step-down is switched. At this time by the error signal whose level is shifted by a level shift circuit, the drive signal of a gate drive circuit 9 is set to a low level, and an NMOS 11 is turned off, thus lowering an output voltage Vout to a prescribed voltage. When an input voltage is lower than the prescribed output voltage by the error signal whose level is shifted by the level shift circuit, the control signal is outputted from a PWM comparator 6, and the NMOS 11 for step-up is switched. At this time, the NMOS 11 is turned on, thus raising the output voltage Vout until it reaches a prescribed voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a step-up / step-down DC-DC converter that steps up or steps down an input DC voltage and outputs the resulting voltage.

[0002]

2. Description of the Related Art Conventionally, step-up / step-down DC-DC converters (devices) are roughly classified into (1) a SEPIC system in which a step-up switching regulator and a step-down switching regulator are connected in series; ) A system in which a linear regulator is connected to a step-up switching regulator, (3) a switched capacitor (charge pump) system, (4) a step-up / down converter in which a step-down DC-DC converter and a step-up DC-DC converter are connected as one circuit. There are four circuit types of a pressure type DC-DC converter type.

However, in the (3) switched capacitor (charge pump) system, although the size (area) of the circuit is small, the output current is only about 200 mA, which is not suitable for a large output. (2) In a system in which a linear regulator is connected to a step-up switching regulator, the efficiency of the step-down operation by the linear regulator is low, and the voltage conversion efficiency is low. (1) The SEPIC method has higher voltage conversion efficiency than the method (2), but since the step-up switching regulator and the step-down switching regulator are operated simultaneously, the step-up switching regulator and the step-down switching regulator are operated. The efficiency is lower than that of the step-up / step-down DC-DC converter system (4) in which only one of the regulators is operated.

[0004] Therefore, the method (4) is more popular than the other three methods because it has a higher voltage conversion efficiency and has a relatively small circuit size for a large output current.

FIG. 5 is a circuit diagram showing a configuration example of a conventional step-up / step-down DC-DC converter (for example, Japanese Utility Model Publication No. 7-2783).
1). In this example, a PNP transistor is used as a step-down switching element, and an NPN transistor is used as a step-up switching element.

The output voltage Vout of this circuit is equal to the resistances 26 and 2
7, and is input to the error amplifier 24. The error amplifier 24 compares the divided voltage Vd with the control input voltage Vo, outputs an error signal of the control input voltage Vo directly to the comparator 21, and shifts the error signal by a predetermined voltage with the level shift 29, It is output to the comparator 22. On the other hand, a triangular wave signal oscillated by the oscillator 23 is input to other input terminals of the comparators 21 and 22.

Here, when the output voltage Vout is higher than a predetermined voltage, the comparator 21 outputs to the PNP transistor 12 a control signal generated by PWM-modulating the triangular wave signal by the error signal.

At this time, the output of the comparator 22 is at a low level due to the error signal having undergone the level shift, and the NPN transistor 28 is turned off. With this, PNP
The type transistor 25 is switched by the control signal to reduce and maintain the output voltage Vout to a predetermined voltage.

On the other hand, when the output voltage Vout is lower than the predetermined voltage, the comparator 22 outputs to the NPN transistor 28 a control signal generated by PWM-modulating the triangular wave signal based on the level-shifted error signal. At this time, the level of the error signal is shifted by the comparator 2.
The output of 1 is at a low level, turning on the PNP transistor 25. Thereby, the NPN transistor 2
8 is switched by the control signal to output voltage V
out is raised to a predetermined voltage and maintained.

[0010]

In the above-described conventional step-up / step-down DC-DC converter, the frequency of the control signal for driving the switching element is reduced in order to further reduce the circuit size (area). Higher frequencies have been achieved. The reason is that when the control signal is increased in frequency, the amplitude of the current flowing through the inductor 14 can be reduced, and components such as a switching element, an inductor, and a smoothing capacitor can be reduced in size.

However, if the control signal is simply made higher in frequency, the switching loss generated in the switching element increases in proportion to the frequency of the control signal. Causes the switching element to be destroyed.

When the frequency of the conventional circuit shown in FIG. 5 in which a bipolar transistor is used as a switching element is increased, for example, when a control signal is set to 1 MHz, heat generation is increased and power conversion efficiency is reduced to about 50%. , The operation becomes unstable.

Thus, the conventional buck-boost D shown in FIG.
The C-DC converter has a problem that the circuit size cannot be reduced as desired by increasing the frequency of the control signal.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to reduce the size of parts by increasing the frequency of a control signal without lowering the voltage conversion efficiency. Another object of the present invention is to provide a DC-DC converter for step-up / step-down which can reduce the circuit size.

[0015]

To achieve the above object, a feature of the present invention is to provide a boosting switching element and a step-down switching element, wherein the step-up switching element and the step-down switching element are provided. A DC-DC converter device that performs control to increase or decrease an output voltage by switching any one of an oscillation circuit that generates an oscillation signal, and an error signal corresponding to a difference between the output voltage and a reference voltage. And a first control signal generated by modulating the pulse width of the oscillation signal based on the value of the error signal, and maintaining the first control signal constant depending on the value of the error signal. A first pulse width modulation comparison circuit for setting a level, a level shift circuit for shifting the level of the error signal, and the level-shifted oscillation Together to generate a second control signal generated by modulating the pulse width by item, the value of the error signal and the second to a constant level of the second control signal
A pulse width modulation comparison circuit, a step-down first MOS transistor switched by the first control signal, a step-up second MOS transistor switched by the second control signal, It is provided with an inductor through which a switching current flows when the first or second MOS transistor is switched, and a rectifying and smoothing circuit for rectifying and smoothing the switching current flowing through the inductor.

The feature of the invention of claim 2 is that the first and second features are as follows.
Are both N-type MOS transistors.

A feature of the invention according to claim 3 is that a high voltage power supply circuit for increasing a peak voltage of the second control signal for switching the second N-type MOS transistor is provided. .

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the DC-DC converter device of the present invention. DC
The DC converter device outputs the output voltage Vout (actually V
The error amplifier 1 that generates the error signal 100 by comparing the divided voltage value Vd of the out signal with the reference voltage Vref, the reference voltage Vr
a reference voltage circuit 2 for generating ef, a level shift circuit 3 for shifting the level of the error signal 100 by a predetermined voltage ΔE, an oscillator 4 for oscillating a triangular wave signal 200 for control, and generating the triangular wave signal 200 by PWM modulation with the error signal 100. A PWM comparator 5 for generating a control signal 300, a PWM comparator 6 for generating a control signal 301 generated by PWM-modulating the triangular wave signal 200 with an error signal 101, a power supply circuit 7 for generating a high voltage, and a power supply circuit 7. A gate drive circuit 8 that generates a drive signal 400 from the control signal 300 using the high voltage thus obtained, a gate drive circuit 9 that generates a drive signal 401 from the control signal 301, and a drive signal 400
NMOS transistor 10 which is driven and switched by a booster, NMOS transistor 11 which is boosted and driven by a drive signal 401, an inductor 12 through which a switching current flows, an input terminal 13 for inputting an input voltage Vin, and outputs an output voltage Vout. It has an output terminal 14, a smoothing capacitor C, diodes D1 and D2 for rectifying the switching current, and resistors R1 and R2 for dividing the output voltage Vout.

FIG. 2 is a circuit diagram showing a configuration example when a charge pump is used as the power supply circuit 7 shown in FIG. The charge pump includes an oscillator (OSC) 71 that generates a square wave of the voltage E, diodes D3, D4, and D5 that boost (2E) the square wave voltage E, and capacitors C1, C2,
Consists of C3.

FIG. 3 is a circuit diagram showing a configuration example of the gate drive circuit 8 shown in FIG. The gate drive circuit 8 is a circuit in which inverters 81 and 82 are connected in series, and a high voltage (2E) from the power supply circuit 7 is supplied to the inverters 81 and 82.

FIG. 4 is a circuit diagram showing a configuration example of the level shift circuit 3 shown in FIG.

The level shift circuit 3 comprises a resistor R3, a constant current source 31, and a current mirror for supplying a current equal to the current flowing through the constant current source to the resistor R3. In the meantime,
A shift voltage ΔE equal to the product of R3 and the constant current i occurs.
This shift voltage ΔE is provided in order to avoid simultaneous switching operation of the step-up NMOS transistor and the step-down NMOS transistor, and its value is set to be equal to or larger than the voltage amplitude of the triangular wave signal 200.

Next, the operation of this embodiment will be described. Input voltage Vin is input from input terminal 13, and output voltage Vout of a predetermined voltage is output from output terminal 14.

The output voltage Vout is divided by the resistors R1 and R2 and input to the error amplifier 1. The error amplifier 1 compares the divided voltage Vd with the reference voltage Vref, generates an error signal 100 with the reference voltage Vref, inputs the error signal directly to the PWM comparator 5, and converts the error signal 100 into a level shift circuit. The error signal 101 shifted by the predetermined voltage ΔE in step 3 is input to the PWM comparator 6. On the other hand, the triangular wave signal 200 oscillated from the oscillator 4 is input to other input terminals of the PWM comparators 5 and 6.

Here, when the input voltage Vin is higher than the set output voltage, the PWM comparator 5 outputs the error signal 10
A control signal 300 pulse-width-modulated with 0 is generated, and the NMOS transistor 10 for step-down is output via the gate drive circuit 8 so that the output voltage Vout becomes equal to the set output voltage.
For switching control. At this time, since the level of the level-shifted error signal 101 is lower than the level of the triangular wave signal 200, the drive signal 401 of the gate drive circuit 9
Becomes a constant value at the low level, and the boosting NMOS transistor 11 is always off. Since the gate of the MOS transistor is a capacitive load, current flows only at the moment when the control signal switches from low level to high level or from high level to low level. Therefore, even if the gate charging current is increased to shorten the switching time and reduce the switching loss, the current consumption of the control circuit is only slightly increased.

The on-duty of the control signal 300 changes in conjunction with the deviation of the output voltage Vout from the set output voltage. That is, when the output voltage Vout becomes higher than the set output voltage, the level of the error signal 100 decreases, and the intersection with the triangular wave signal 200 moves to the lower voltage side. As a result, the on-duty decreases, and the output voltage Vout also changes in a decreasing direction. Conversely, when the output voltage becomes lower than the set output voltage, the intersection of the error signal and the triangular wave signal moves to the high voltage side, and as a result, the on-duty increases and the output voltage also changes in the increasing direction.

The gate drive circuit 8 generates a drive signal (voltage amplitude 7 to 8 V) 400 higher in voltage than the control signal 300,
By outputting this to the gate of the NMOS transistor 10, the NMOS transistor 10 is switched. By the switching of the NMOS transistor 10, a switching current flows through the inductor 12, and the switching current is rectified by the diodes D1 and D2, further smoothed by the capacitor C, and output voltage Vou.
t.

On the other hand, when the input voltage Vin is lower than the set output voltage, the PWM comparator 6 outputs the error signal 101
Generates a control signal 301 subjected to pulse width modulation, and controls the switching of the boosting NMOS transistor 11 via the gate drive circuit 9 so that the output voltage Vout becomes equal to the set output voltage. At this time, since the level of the error signal 100 is higher than the level of the triangular wave signal 200, the drive signal 400 of the gate drive circuit 8 has a high level and a constant value, and the step-down NMOS transistor 10 is always on.

The on-duty of the control signal 301 changes in conjunction with the deviation of the output voltage Vout from the set output voltage. That is, when the output voltage Vout becomes higher than the set output voltage, the level of the error signal 101 decreases, and the intersection with the triangular wave signal 200 moves to the lower voltage side. As a result, the on-duty decreases, and the output voltage Vout changes in a decreasing direction. Conversely, when the output voltage becomes lower than the set output voltage, the intersection of the error signal and the triangular wave signal moves to the high voltage side, and as a result, the on-duty increases and the output voltage also changes in the increasing direction.

By the switching of the NMOS transistor 11, a switching current flows through the inductor 12, and the switching current is rectified by the diode D2, further smoothed by the capacitor C, and output voltage Vo.
ut.

Here, the high voltage driving of the NMOS transistor 10 will be described. In this example, since the NMOS transistor 10 is used as the step-down switching element, the driving signal 4 for driving the NMOS transistor 10 is used.
00: DC input voltage + FET threshold voltage V
A high voltage exceeding th is required, and a high voltage of about 7 to 8 V is required. Therefore, a high voltage is generated by using the power supply circuit 7 as a charge pump as shown in FIG. 2 and supplied to the gate drive circuit 8 to generate a high voltage drive signal 400 from the control signal 300. Note that a boost switching regulator can be used as the power supply circuit 7.

According to the present embodiment, the DC-
NMO as a switching element of a DC converter device
Since the S transistors 10 and 11 are used, the frequency of the control signal 300 can be increased (3 MHz to 5 MHz) without lowering the switching efficiency of the switching element, for example, 3 MHz and the input voltage is 2.5 to 6.0 V. ,
With an output voltage of 3.3 V and an output current of 400 mA, a voltage conversion efficiency of 85% can be obtained.

Therefore, without lowering the voltage conversion efficiency,
It is possible to reduce the size of the components of the buck-boost DC-DC converter such as the NMOS transistors 10 and 11, the inductor 12, and the smoothing capacitor C, thereby reducing the size (area) of the circuit to about half of the conventional size. it can.

According to the above embodiment, the step-down MO
Although an N-type MOS transistor is used as the S transistor 10, it may be a P-type MOS transistor. In this case, since the drive signal for switching the P-type MOS transistor does not need to be a high voltage, the power supply circuit 7 for generating the high voltage is not required. The size of the MOS transistor is about three times as large as that in the case of using an N-type MOS transistor, and the gate capacitance is also about three times. Accordingly, when the frequency of the control signal is increased, the conversion efficiency decreases. Will be.

Nevertheless, higher conversion efficiency can be maintained than in the case of using a conventional bipolar transistor, so that the circuit size can be reduced accordingly.

When a P-type MOS transistor is used, all of the control circuit and the switching element can be monolithically integrated.

The polarity of the input terminals of the PWM comparators 5 and 6 to which the error signal 100, the level-shifted error signal 101 and the triangular wave signal 200 are input can be changed according to the configuration of the gate drive circuit. It is.
That is, in the case of the present embodiment, the gate drive circuit is configured to output the logic level of the input signal as it is, but when the input / output is inverted, the error signal and the level-shifted error signal are converted into PWM signals. By inputting the signal to the minus terminal of the comparator and inputting the triangular wave signal 200 to the positive terminal, it is possible to obtain the same effect as in the present embodiment.

[0038]

As described in detail above, the D of the present invention
According to the C-DC converter device, the frequency of the control signal can be increased without lowering the voltage conversion efficiency, the components can be reduced in size, and the circuit size can be easily reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a DC-DC converter device of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a power supply circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration example of a gate drive circuit shown in FIG. 1;

FIG. 4 is a circuit diagram illustrating a configuration example of a level shift circuit illustrated in FIG. 1;

FIG. 5 is a circuit diagram showing a configuration example of a conventional buck-boost DC-DC converter.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 error amplifier 2 reference voltage circuit 3 level shift circuit 4 oscillator 5, 6 PWM comparator 7 power supply circuit 8, 9 gate drive circuit 10 step-down NMOS transistor 11 step-up NMOS transistor 12 inductor 13 input terminal 14 output terminal C capacitor D1, D2 Diode R1, R2 Resistance

Claims (3)

[Claims] 1. A DC comprising a boosting switching element and a step-down switching element, and performing a control of switching one of the step-up switching element and the step-down switching element to raise or lower an output voltage. An oscillator circuit for generating an oscillation signal, a difference circuit for generating an error signal corresponding to a difference between the output voltage and a reference voltage, and a pulse width of the oscillation signal modulated by the value of the error signal. A first pulse width modulation comparison circuit for generating a first control signal to generate the first control signal and for setting the first control signal to a constant level depending on the value of the error signal; and shifting the level of the error signal. A level shift circuit for generating a second control signal for modulating a pulse width with the oscillation signal subjected to the level shift. In both cases, a second pulse width modulation comparison circuit for setting the second control signal to a constant level depending on the value of the error signal; a first step-down MOS transistor switched by the first control signal; A second MOS transistor for boosting which is switched by the second control signal, an inductor through which a switching current flows when the first or second MOS transistor is switched, and a switching current flowing through the inductor. And a rectifying / smoothing circuit for rectifying and smoothing. 2. The DC-DC converter according to claim 1, wherein both the first and second MOS transistors are N-type MOS transistors. 3. A high-voltage power supply circuit for increasing a peak voltage of the second control signal for switching the second N-type MOS transistor. DC-DC converter device.