JPS5996763A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit which has a low consumed current and is strong to noises by making a constituent of a complementary type MIS field effect transistor consisting of an MIS field effect transistor wherein the sum of absolute values of threshold voltage of each is larger than a power source voltage. CONSTITUTION:In the input-output voltage characteristic of a CMOS-FET inverter which satisfies the condition of ¦VTHP¦+VTHN>VDD between the threshold values VTHP, VTHN of a P-channel type FET and an N-channel type FET and the power source voltage VDD, a region I represents the P-channel type FET at ON, the N-channel type FET at OFF, a region II the P-channel one at OFF, and a region III the P-channel one at OFF, the N-channel one at ON. When an input voltage is at the region II, an output voltage is kept at the load capacitance at the next stage. Since this constitution do not bring the P-channel type FET and the N-channel type FET into a conduction state at the same time, a drain current does not flow regardless of the rise-fall times of the input voltage, which is also strong to the noise at the time of transience because of the presence of a logical threshold hysteresis.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit in which a plurality of complementary MIS field effect transistors are integrated on the same semiconductor substrate.

Conventionally, for example, in an integrated circuit using a complementary MO8 field effect transistor (hereinafter referred to as CMOS-FET), a P-channel FE that constitutes an 0MO8-FET has been used.
T and N-channel FET threshold voltage VTHPIVT
HN (!: t OjA t Pressure VDD (7) The valley constant was determined so that the relationship VTHPl+VTHN<VDD was established.

Example Eva, VDD = 10 V integrated circuit technology, vTH
P.

VTHN is approximately -2V and +2V, respectively. FIG. 1 shows the input/output voltage characteristics and drain current of a conventional 0MO8-F'ET inverter. When the rise time and fall time of the input signal are short, the train current can be ignored, and the charge current is considered to be the charging/discharging current of the MOS-FET gate capacitor in the next stage. In this case, in order to achieve high-speed operation, it is necessary to make l VTI (P l + VTHN as small as possible and increase the charging/discharging current. However, in the delay circuit as shown in Fig. 2, the input of inverter 2 The rise and fall times of the direct voltage become longer, and the train current shown in Figure 1 cannot be ignored.The smaller %1VTHP1.VTHN is made to obtain high-speed operation, the more the drain current becomes a dog, and the integrated circuit The oscillation circuit shown in Fig. 3 has a similar drawback.Furthermore, the conventional C
As is clear from the figure, since there is no hysteresis characteristic in the -Lislenskjöld, if noise is mixed in during hyperconvulsions, there is a risk that the circuit will malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor integrated circuit with low current and strong resistance to noise.

FIG. 4 shows the input/output voltage characteristics of a CMO5-FET inverter that satisfies the 1vTHP1+vTHN'>VDD null condition. In Figure 4, the area engineering is 'P channel type FE'
l'on, N channel type FET off, area ■ is P
Channel type FET off, region I is P channel type F
HT off, N-channel type F'ET on.

Input ゛: When the pressure is in the region ゛, the output voltage is held by the load capacity of the next stage. In this configuration, P-channel type F
Since E'1' and the N-channel channel type F'ET do not enter the mA state at the same time, no drain current flows regardless of the rise and fall times of the input voltage.

Furthermore, since the cooking threshold has hysteresis characteristics, it is resistant to noise during transient periods.

IVTHPI + VTHN > VDD Woti foot f Ruta? h VTHP *The methods of changing VTHN are well known, such as changing the gate exclusive body, ion implantation, etc. This suggests methods such as controlling the impurity concentration in the channel region and changing the thickness and type of the gate insulating film. This allows the width of the glume area 4 in FIG. 4 to be changed arbitrarily.

This inverter can be used as a delay circuit inverter 2 consisting of two inverters 1.2 and a capacitor 3 shown in FIG. 2, or a delay circuit inverter 2 shown in FIG. Inverter 6, resistor 7. By applying this to the inverter 3 of the oscillation circuit consisting of the crystal oscillator 8, a circuit with low current consumption and low noise resistance can be obtained.

As described above, specific embodiments of the present invention have been described with reference to CMO:1-FET.
Although the inverter has been described, various other combinations are possible. The integrated circuit is IVTHI)l+VTHN
>Even if it is composed only of complementary FETs that satisfy VDD, there will be complementary FETs that satisfy the above conditions and complementary FEs that do not.
It may be configured by combining T.

According to the present invention, a semiconductor integrated circuit with low current consumption and low noise can be obtained without complicating the circuit configuration or manufacturing process.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the relationship between the output voltage and drain 1lEfi of a conventional C408-FET inverter and the input voltage, Fig. 2 is a wiring diagram of a delay circuit, Fig. 5 is a wiring diagram of an oscillation circuit, and FIG. 4 is a diagram showing the input/output voltage characteristics of the innocoator according to the present invention. 1.2.6...Inverter, 3-5...Capacity, 7.
・Resistance, 8. Crystal oscillator. Ya1 (2) Te2 Flash

Claims (1)

[Claims] A semiconductor integrated circuit characterized in that the sum of the absolute values of respective threshold voltages is greater than the power supply voltage, and the semiconductor integrated circuit includes a complementary M I S field effect transistor made of five field effect transistors as a component.