JPS5994876A - Manufacture of metal insulator semiconductor device - Google Patents

Abstract

PURPOSE:To make it easy to control the effective channel length and improve the evenness of a surface by forming a recess groove by etching a substrate at a channel region scheduled part after forming a source and a drain region. CONSTITUTION:A field oxide film 2 and an oxide film pattern 3' are formed on a p type Si substrate 1, which is nitrided after ion implantation, and thus an Si nitride film 5, the n<+> type source and drain regions 6 and 7 are formed. The recess groove 8 is formed by etching, a thermal oxide film 9 is formed, and a gate electrode 11 is formed by depositing a doped polycrystalline Si film and patterning it. A thermal oxide film 12 is formed, and the Si nitride film 5 is removed by etching, resulting in the formation of an Al-Si wiring 14. The depth of the recess groove 8 can be made shallower than the junction depth between the source and drain regions 6 and 7, there is less possibility of the generation of side etching, the controllability for the effective channel length is excellent, and the surface becomes even.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing an MIS semiconductor device.

[Technical background of the invention and its problems]

Progress in the miniaturization of MOS transistors is accelerating as LSIs become larger in capacity and more highly integrated, and the effective channel length of the MOS (lannostar) currently at the center of development is already in the submicron range. . Furthermore, the effective channel length of MOS transistors currently applied to VLSI devices is less than 2 μm9.1.5~1.
The thickness is 7 μm. Along with these trends, many problems have arisen that need to be solved, such as the problem of the optical channel effect, the problem of reduced reliability due to hot electrons, and the problem of processing irregularities due to microfabrication.

However, as the capacity of memory devices increases, from 256 kbit DRAM to IM bitDRA
M, also 6 4 kbitsRM to 256 kb
Technological development of IT SRAM is progressing on a four-fold basis every two to three years, and solutions to the various problems mentioned above are being proposed.

By the way, the short channel effect is the source.

This is a phenomenon in which as the interval between the drains becomes shorter, the depletion layer due to the drain voltage approaches the source region, the surface potential of the channel region decreases, and the threshold voltage (Vth) decreases. As a result, the controllability of the drain current by the gate voltage deteriorates, and the fluctuation of Vth becomes large υ, which significantly deteriorates the device performance. Furthermore,
As the drain depletion layer approaches the source region, the electric field strength in the channel region near the drain increases significantly.
The drain current makes the generation of hot electrons and the generation of electron-hole pairs due to impact-ionization more noticeable, and the gate current and substrate current increase. Also,
Hot electrons trapped in the gate oxide film cause Vth to change over time, making reliability unstable.

In order to prevent such short channel effects, a method is generally used to suppress the elongation of the depletion layer by optimizing the impurity (φ degree) in the channel region.
A thickness of about 2.0 μm is considered to be an effective preventive measure against a drain voltage of 5 V, and is applied to devices. However, when the effective channel length becomes 1.5 μm or less, it becomes necessary to reduce the drain voltage.

On the other hand, there are also attempts to lengthen the effective channel length structurally, as seen in transistors with a concave MO8 structure or a VMO8 structure. These Yang Tian transistors are manufactured, for example, by the following method.

First, a second conductivity type impurity is diffused throughout the element region separated by a field oxide film of a first conductivity type semiconductor substrate to form a second conductivity type impurity region. Next, a desired position of the element region is etched deeper than the junction depth of the impurity region to separate the impurity region into source and drain regions, and a channel formed of a concave groove or V-groove between the source and drain regions. Form a region. Next, the concave groove or V? A gate electrode made of polycrystalline silicon or metal silicide is formed on +S via a gate oxide film. Subsequently, after depositing a CVD-3iCh film on the entire surface, a contact hole is opened, and a wiring metal is further deposited on the entire surface, followed by turning to form a wiring. Still, as another wiring formation process, after forming the r-) electrode,
A thick oxide film is formed around the dirt electrode by thermal oxidation treatment, and a thin oxide film is formed on the surfaces of the source and drain regions, respectively, and only the thin oxide film on the surfaces of the source and drain regions is removed by etching to form a contact hole as a dirt electrode. On the other hand, a method has also been adopted in which the wiring is formed using self-line, and then a wiring metal is deposited and patterned.

The transistors manufactured by the above-mentioned method with a concave to 10 stf structure or a VMO8 structure have a long effective channel length, so the short channel effect can be prevented, and the horizontal PR of the groove can be short, so it can be used for dirt. The electrode portion can be miniaturized in a two-dimensional manner.

However, in the above-mentioned method, the controllability of the effective channel length is poor due to side etching and the like, since the groove (TF) must be etched deeper than the junction depth of the impurity region. , also a concave groove or V
Since the grooves are deep, the surface near the dart electrode has large irregularities and poor flatness. In addition, when a CvD-8in film is used as an interlayer insulating film when forming wiring, a contact hole is created by photolithography, so a margin for mask alignment is required, making it difficult to miniaturize the source and drain regions. This is difficult, and the junction capacitance is also large, which is disadvantageous for increasing speed. On the other hand, if a method is adopted in which the wiring is thermally oxidized, only the thin oxide film on the surface of the source and drain regions is etched to form a contact hole, and then the wiring is formed, the end of the dirt electrode Since the oxide film becomes thinner, dirt electrodes are connected to the wiring.

There is a risk of short-circuiting with the drain region.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing fine, flat, and high-speed TI/IIS semiconductor devices with good controllability without causing defects such as short circuits. That is.

[Summary of the invention]

In the method for manufacturing an MI8 semiconductor device of the present invention, first, a mask material is applied to a planned channel region portion of an island-shaped element region formed by electrically separating a first conductivity type semiconductor substrate via an oxide film. After forming the zetan, impurity ions of the 24th electric type are ion-implanted into the intended source and drain regions using this mask material/zetaan as a mask. Next, after removing the mask material/mother turn, the surfaces of the planned source and drain regions are directly nitrided to form a nitride film, and the ion-implanted impurities are activated to form the source and drain regions of the second conductivity type. Form a region. Subsequently, the oxide film is removed,
Further, the exposed portion of the substrate where the channel region is to be formed is etched to form a groove. Next, a gate insulating film is formed on the concave bamboo surface, and a gate electrode material is deposited on the entire surface.
・A dirt electrode t''X'f shadow is formed by turning.Finally, after forming an oxide film on the surface of the dirt electrode, a source is produced using the oxide film as a mask.

The nitride film on the drain region is removed to form a contact hole, and further wiring is formed.

According to the method of the present invention, the depth of the groove is equal to the source.

Since it may be shallower than the junction depth of the drain region, the effective channel length can be easily controlled and the surface flatness can be improved. By removing the nitride film on the surface of the source and drain regions using the oxide film on the surface of the gate electrode as a mask during wiring formation, contact holes can be made using self-aligned lines, and there is no need for a photolithographic process. Source and drain regions can be miniaturized. There is still a sufficiently thick curved film at the end of the meter electrode, so 1.
) - No defects such as short circuits between the i-pole and the source and drain regions occur.

[Embodiments of the invention]

Examples of the present invention will be described below in Figures 1 (a) to (g) and 2.
This will be explained with reference to the figures.

First, a field oxide film 2 was formed on a P-type silicon substrate 1 by a selective oxidation method, and then an oxide film 3 with a thickness of about 5 mm was formed on the surface of an island-shaped element region surrounded by this field oxide film 2. FIG. 1(a) (Illustrated).

Next, a photoresist pattern 4 is formed on the intended channel region, and the oxide film 3 is removed by etching using the photoresist pattern 4 as a mask.
' was formed. Next, the photoresist pattern 4
As a mask, As is applied to the planned source and drain regions.
Acceleration energy 40keV, dose t2X
Ion implantation was performed under the condition of 1015 crn (see figure (b)
).

Next, the photoresist gloss turn 4 was removed and cleaned, and then heated at 1000°C for 20 minutes in NH3, f gas.
A nitriding process was carried out for a minute to form a silicon nitride film 5 with a thickness of 30 to 50 mm on the exposed surface of the source and drain regions. At this time, the silicon nitride film hardly grows on the oxide film pattern 3'. The As ion-implanted layer is still electrically activated to form the n-type source and drain regions.
was formed (as shown in FIG. 3(c)).

Next, after removing the oxide film pattern 3' by etching, the exposed channel region portion was etched to a depth of 0.3 μm using a KOI (based on KOI) solution.
The etching speed of the KOH-based solution for the (100) plane is about 10 times faster than that for the (111) plane, so the (l1
1) A groove 8 having the surface as a side wall was formed. Further, the depth of the groove 8 can be freely selected according to the transistor characteristics, taking into consideration the xj of the n+ type source and drain regions 6 and 7 (as shown in FIG. 3(d)). In the same figure (d), Xj of the revised source and drain regions 6 and 7 is finally about 0.3 μm.
The case where the depth of the groove 8 is set to approximately the same depth of 03 μm is shown, assuming that

Next, a thermal oxidation process is performed using the silicon nitride film 5 as an oxidation-resistant mask to form a thermal oxide film 9 with a thickness of about 100× that will become a gate insulating film on the surface of the recess n8, and then a thermal oxide film 9 with a thickness of about 100× is formed on the entire surface. 3000mm Lindog polycrystalline silicon film 10
was deposited (as shown in Fig. 1(e)).

Next, the polycrystalline silicon film 10 was turned to form an r-to-electrode 1. Continued -' (1,900
A thick thermal oxide film 12 was formed only on the surface of the dart electrode 11 by thermal oxidation treatment at a relatively low temperature. At this time, since the silicon nitride film 5 is formed on the surface of the n-type source and drain regions 6.7, a thermal oxide film does not grow (as shown in FIG. 6(f)).

Next, using the thick thermal oxide film 12 on the surface of the r-) electrode 11 as a mask, the silicon nitride film 5 on the n-type source and drain regions 6 and 7 was removed by etching to form contact holes 13 and 13. Next, At-8 on the entire surface
After depositing ilq, patterning is performed to form wiring x4. z4
was formed to produce a MOS) lannosta (see figure (g)
(Illustrated).

The manufactured MOS l-lanzoster shown in FIG. 1(g) does not form the concave Ff8 as shown in FIG. 2. Δyj at 11jl (for example, on the source region 6 side)
The channel length recedes laterally. When Δyj is specifically calculated in the above embodiment, it is as follows. Normally, yj=0.8xj, but the surface of the groove 8 is formed at an angle of about 54° by anisotropic etching. Here, the junction surface of the source region 6 and the groove 8 are connected from the top end of the groove 8.
If the distance at the intersection with the side surface of is approximately equal to yCj, then Δyj = yj-xj
This means that the lateral diffusion length of the source region 6 is suppressed by a little more than 20% of υ, Xj.

The same applies to the drain side, and if these and the bent portion of the groove 8 are taken into account, the effective channel length is increased by approximately 60% of xj as a whole. In other words,
When the channel length is shortened, it is necessary to make xj shallower in order to maintain the effective channel length, but by adopting the method of the present invention, the same effect as when Xj is reduced to 3 is obtained.

As mentioned above, since the effective channel length can be increased in the method of the present invention, it is possible to prevent the negative channel effect in the same manner as in the conventional VMO transistor.

According to the method of the present invention, however, unlike the conventional VMOS transistor manufacturing method, after the source and drain regions 6 and 7 are formed in advance in the step shown in FIG. 1(d), the substrate 1 between them is etched. Since the groove 8 is formed in this manner, the depth of the groove 8 can be made shallower than the junction depth of the source and drain regions 6.7. Therefore, there is little possibility that side etching will occur, and the effective channel length can be easily controlled. In addition, the surface of the manufactured M'OS transistor will be very flat, and the effective channel length will be approximately equal to the oxide film 1 in the process shown in FIG. 1(b). It is determined by the machining accuracy of turn 3'. Since this oxide film E-turn 3' is very thin, side etching can be ignored not only when processed by dry etching but also when processed by wet etching. The grooves 8 can be formed without variation. Therefore, from this point as well, the uniformity of the channel length can be improved.

Also, in the process shown in FIG. 1(g), the contact holes 13,1,? of the wiring 14.14 are formed. The source and drain regions 6 are formed by using the thermal oxide film 12 on the surface of the dart city as a mask.
, 7 can be formed in a self-lined manner by etching the silicon nitride film 5 on the surface of the silicon nitride film 5. . Therefore, unlike when using a photo-etching process, mask alignment margins are not required, so the source and drain regions 6 and 7 can be miniaturized, and the junction capacitance can be reduced, which is effective for speeding up. be. Furthermore, since a sufficiently thick silicon oxide film can be left at the end of the dirt electrode 1,
No defects such as a short circuit between the horizontal electrode 11 and the source and drain regions 6.7 occur in the wirings 14, 14.

Note that although the thermal oxide film 9 was used as the dirt insulating film in the above embodiment, the present invention is not limited to this, and other insulating films may be used. Figure 3(a), (
This will be explained with reference to b) and FIGS. 4(a) to (c).

FIG. 3(a) shows the state after the process in FIG. 1(d) t, similar to the above embodiment. Subsequently, the surface of the groove 8 is directly nitrided in NT gas again to form a silicon nitride film 21 with a thickness of about 50× that will become a dirt insulating film, and then, for example, a phosphorus-doped polycrystalline silicon film 10 is deposited ( The same figure (b
). Next, through the steps shown in FIG. 1(f) and below, an MIS (MIS) using the silicon nitride film 21 as the dirt insulating film is formed.
A transistor is manufactured.

Therefore, if the silicon nitride film 21 is used as the dirt insulating film as described above, the capacitance can be improved although the dielectric breakdown voltage is lowered.

FIG. 4(,) also shows the state after the process in FIG. 1(a) i, similar to the above embodiment. Subsequently, after removing the silicon nitride film 5 on the n-type source and drain regions 6 and 7, thermal oxidation treatment is performed to form a thermal oxide film with a thickness of about 100X.
Further, the thermal oxide film is nitrided in plasma-excited NH3 gas at about 1000 DEG C. to convert it into oxynitride 22 with a thickness of 150 to 200 mm. At this time, the isolation oxide film 2
The surface also becomes oxynitride (as shown in the same figure (b)).

Next, for example, a phosphorus-doped polycrystalline silicon film 10 is formed on the entire surface.
After depositing oxynitride 2 as a dirt insulating film (as shown in Figure 1(c)), the steps shown in Figure 1(f) and below are performed.
MIS) using 2) orchid zosta is produced.

If the oxynitride 22 is used as the dirt insulating film as described above, both the dielectric strength and the capacitance will have values between those of the oxide film and the silicon nitride film.

However, if the As ion implantation dose is kept low in order to suppress the lateral diffusion of the source and drain regions and prevent the short channel effect in the process shown in FIG. 1(b), (g) In the illustrated process, the silicon nitride film 5 is etched and removed using the thermal oxide film 12 on the surface of the dirt electrode 11 as a mask to form contact holes 13, 13, and then As ions are implanted at a high dose and annealed. As shown in FIG. 5, the n-type high concentration impurity region 31,
32 can also be formed to reduce contact resistance.

Furthermore, although polycrystalline silicon was used as the dirt electrode material in the above embodiment, metal silicide may also be used.

Furthermore, in the above embodiment, when forming the groove 8, rcott
Although a chemical dry etching solution was used, chemical dry etching may also be used.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to provide a method for manufacturing a MIS semiconductor device that is fine, has good flatness, and has increased speed with good controllability without causing defects such as short circuits.

[Brief explanation of drawings]

Figures 1(a) to (g) show 1Vq in the embodiment of the present invention.
A cross-sectional view showing the manufacturing process of an os transistor, and the second half is an explanatory view showing the effective channel length of a MOS transnoster manufactured in an embodiment of the present invention.
4(b), FIGS. 4(a) to 5(c), and FIG. 5d are sectional views showing the manufacturing process of an M-type S transistor in other embodiments of the present invention, respectively. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Oxide film, 4... Photorenost pattern, 5
... Silicon nitride film, 6, 7 ... Source, drain region, 8 ... Groove, 9 ... r-1 C2 film, 10
...Polycrystalline silicon! Kan, 11...Dart electrode, 1
2... Thermal oxide film, 13... Contact ball, 14
...Wiring, 21...Silicon nitride film, 22...Oquine nitride, 31.32...N+ type high concentration impurity region. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 1 2 Figure Ayl (b) Ward 3 Figure 5

Claims (6)

[Claims] (1) A step of forming an e-turn of a mask material via an oxide film on a planned channel region of an island-shaped element region formed by electrically separating a first conductivity type semiconductor substrate, and the mask. A step of ion-implanting impurity of the second conductivity type into the intended source and drain regions using the material/mother turn as a mask, and after removing the mask material pattern, the source. A step of directly nitriding the surface of the planned drain region to form a nitride film and activating the ion-implanted impurities to form a second conductivity type source and drain region, and removing the oxide film and further exposing it. A step of etching the substrate in the area where the channel region is to be formed to form a groove, a step of forming a date insulating film on the surface of the groove, and a step of depositing an r-) electrode material on the entire surface, and then turning... After forming a gate electrode and performing thermal oxidation treatment to form an oxide film on the surface of the dirt electrode, the nitride film on the source and drain regions is removed using the oxide film as a mask to form a contact hole. 1. A method for manufacturing an MIS semiconductor device, comprising the steps of: forming a wiring; and forming a wiring. (2) The method for manufacturing an MIS semiconductor device according to claim 1, wherein the ketone insulating film is a thermal oxide film. (3) r-) The method for manufacturing an MI8 semiconductor device according to claim 1, wherein the insulating film is a silicon nitride film formed by directly nitriding the surface of the groove. (4) The ketone insulating film is made of oxynitride, which is formed by removing the silicon nitride film on the surface of the source and drain regions, then thermally oxidizing the entire surface, and further nitriding the thermal oxide film. A method for manufacturing an MI8 semiconductor device according to claim 1, characterized in that: (5) The method for manufacturing an MIS semiconductor device according to claim 1, wherein the r-) electrode material is polycrystalline silicon or metal silicide. (6) After etching the insulating film on the surface of the source and drain regions and before forming wiring. The M I S according to claim 1, characterized in that impurities of the second conductivity type are ion-implanted into the drain region at a higher dose than the initial ion implantation dose, and further annealed. A method for manufacturing a semiconductor device.