JPS5994156A - Memory access control system - Google Patents

Abstract

PURPOSE:To enhance the access efficiency of a memory device and make the data processing speed high, by encoding the access direction for every block to give it to the memory device and performing the access control in the memory device side. CONSTITUTION:Operation designating information, access direction designating information, and an access block length are inputted from a CPU through terminals D, E, and G, registers 10 and 29, etc. to a memory access/sequence control part 11. The control part 11 inputs an address and an operation designating signal to a memory array address register/decoder part 18 and a memory access timing generating part 19 and supplies control information to a memory array 24. The timing outputted from the timing generating part 19 is sent to a read data control part 27 to control a data register 25 and a gate 26 of a bus, and data read out from the memory 24 is sent from a terminal J to an input/output device or the like through the register 25 and etc. The access direction and etc. are given to the memory device in this manner to make the memory access and the data processing high-speed.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a memory device of a data processing system whose main purpose is to process and/or store two-dimensional data (image data, etc.). In particular, the present invention relates to a memory access control method that can improve flexibility and speed up access to the memory device.

(b) Prior Art and Problems Conventionally, two-dimensional image data and other data have been processed and stored in a data storage memory.
Since one-dimensional addressing memory has very poor processing efficiency, two-dimensional or three-dimensional addressing memory has been devised and applied.

However, in general, when accessing in block units, regular access in a fixed direction is possible;
In order to access in the reverse direction or in another direction, it is necessary to calculate the seat address using a program or the like, generate a new address, and then access the memory, resulting in poor memory access efficiency.

FIG. 1 shows an example of the configuration of a data processing system that processes/stores image data and the like. When the central processing unit 1 accesses a data block in the memory device 2, for example, in direct memory access transfer, the central processing unit 1 inputs the start address, block length,
Control signals such as operation designation are given to the memory device 2, and read data and metropes are sent to the magnetic disk 7 via the magnetic disk control device 4, and the data is stored therein. Further, data is read from the magnetic disk 7 and written into the memory device 2. Alternatively, the read data and strobe may be displayed on the display 5 via the control device 3 and printed on the printer 6. When a series of data processing or storage is completed, the memory device 2
A completion report is then sent to the central processing unit 1. When performing the above operation, a command from a keyboard or the like requests that the figure shown in FIG. 2A be rotated by 90 degrees clockwise as shown in B and displayed or printed. . Conventionally, the second
The central processing unit 1 calculates the address of the figure A in the figure using a program, etc., changes the reading direction, creates a new figure B on the memory device 2, reads out the figure B, and transfers the 5 image data. For processing, the rotation direction of the figure is 180 degrees.
There are various ways to flip a rotated figure, such as making it symmetrical about the X axis or symmetrical about the Y axis. Therefore, a new address calculation by the central processing unit 1 is required, and the memory capacity is also required to be more than twice that of the image data, resulting in a disadvantage that the efficiency of memory access is reduced.

(c) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks. When accessing a block of memory, the access direction is coded for each block and given to the memory device, and the coded information is transmitted to the memory device. An object of the present invention is to provide a memory access control method that speeds up memory access and data processing speed by decoding and controlling an address generation unit to create a predetermined address.

(d) Structure of the Invention The structure of the present invention is a central processing unit of a data processing system whose main purpose is to process and/or accumulate two-dimensional data, an external storage device, and a receiving device for artificial satellite data. When accessing memory from an input/output device including an image-only input/output device, by giving the memory device the direction to access each block of data, three constant addresses can be generated within the memory device. This is what I did.

(e) Embodiments of the Invention In block access of a memory device, the present invention provides the memory device with the start address, block length, access direction, operation designation, etc., and performs access control on the memory device side. This is an attempt to speed up memory access by generating addresses and the like without involving the program in the central processing unit.

FIG. 3 is a block diagram of a circuit showing one embodiment of the present invention. Operation designation information such as read/write, etc., including an activation signal, enters the memory access/sequence control unit 11 from the central processing unit via the terminal.

Access direction designation information is input from the central processing unit through terminal E. After being temporarily stored in the register 10, the information is input to the memory access/sequence control unit 11. The starting address is input from the central processing unit through the terminal F, is temporarily stored in the register 15, and is sent to the arithmetic unit 16 for calculating the memory access address and x, y.
The access block length is entered from the central processing unit 4-1 from the 1,000G input to the arithmetic unit 30 for calculating the end address, and is once stored in the register 29 having an up/down count function. If the horizontal axis is X and the vertical axis is Y, then the Xp'I end address is calculated and stored in the register 31. Also, the access block length output from the register 29 is input to the 7-lip flop 28 for the memory access end detection interrupt signal, and when the block length becomes "0'", the interrupt signal is sent to the memory access/sequence control unit via the logic circuits 32 and 35. Send to 11. Memory access/
The sequence control section 11 provides addresses and operation designation signals to the memory array address register/decoder section 18 and the memory access timing generation section 19, and
Control information is supplied to 4. The timing output from the timing generator 19 is sent to the memory access/sequence controller 11 via the logic circuit 35. Also, read data control section 2
7, controls the read data register 25 and the bus gate 26, and is read out from the memory array 24 to the logic circuit '16'16'16'16'16'16' The data is sent to input/output devices, external storage devices, etc. Furthermore, the data is sent to the write data control unit 22, enters the memory array write information register 23, and writes the data input from the terminal H via the logic circuit 34 to the memory array 24, thereby controlling the data update. The read/write address at this time is given by the memory array address register/decoder section 18.

The memory access/sequence control section 11 controls the register control circuit 12, drives the initial setting section 13 for setting the memory access address color/initial value, and sets the register 14 indicating the address within the access block. Register 14 has an up/down count function. Arithmetic unit 16 calculates an address for accessing data in memory array 24 from the values of register 14 and register 15, and stores it in register 17. Comparator 20 for memory access completion detection compares the addresses of register 17 and register 31, and if they match, sets flip-flop 21 for memory access completion detection interrupt signal via logic circuit 33. The signal of flip-flop, P21 is logic circuit 32.35
The data is sent to the memory access/sequence control unit 11 via the. The memory access/sequence control unit 11 checks whether access has been completed each time one access is completed.

and sends a termination report to the central processing unit, input/output device, or external storage device control device via terminal C using the termination signal;
End the access operation.

FIG. 4 is a diagram illustrating address designation of access blocks on the memory array 24. If the first address in the X-axis direction is Xi and the block length is Lx, the last address xe
it, xs+Lx. Set the starting address in the Y-axis direction to 7
m, and if the block length is Ly, the final address ye is ys
It will be 10Ly. Since the start addresses za and ym of a block can be regarded as relatively 0 addresses, the access is completed by repeating the access for the length of the block in the X-axis and Y-axis directions.

Furthermore, by changing the access direction when reading or writing a block, it is possible to rotate and flip the image data. For example, to rotate 7-90 degrees clockwise during reading, use Xll from za, ye.
, yl, and repeat this process from x8 to xe.

FIG. 5 is a block diagram of a circuit showing another embodiment of the present invention. This embodiment uses a processing device such as a microprocessor, a rewritable control memory, and is microprogram controlled (firmware controlled) to be economical and flexible in changing the configuration. A processing device 40 for controlling the memory device reads out a program from a control memory 41 that functions as a microprogram for control, controls an ink 7 process control unit 46, and inputs the start address and operation designation information to the terminal. , access direction designation information, and access block length. An address for accessing the memory array 50 is stored in the address register 42 and sent to an address decoder 47 to decode the address and access the memory array 50. The timing at this time is given by a timing generator 48 controlled by access information stored in an access register 43. Access information of memory 8-array 50 is sent to address decoder 47 and memory status register 44, which controls access register 43. Transfer control register 45 stores data input from terminal H in write register 49 and causes it to be written to the memory array. Also, during reading, the register 51 and gate 52 are controlled to send the read data from the memory array 50 from the terminal J.

(f) As described in detail, the present invention provides a data processing system that processes and/or stores two-dimensional data by providing an access direction without requiring address calculation by a central processing unit. Since the data block can be processed by controlling the reading direction or writing direction of the data block, the access efficiency of the memory device can be improved and the data processing speed can be increased, which has a great effect.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of a data processing system, FIG. 2 is a diagram explaining a figure reading method, FIG. 3 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 4 is a memory array. FIG. 5, which is a diagram explaining addressing of the above access block, is a block diagram of a circuit showing another embodiment of the present invention. 1 is a central processing unit, 2 is a memory device, 3 is a control device, 4
is a magnetic disk control device, 5 is a display, 6 is a printer, 7 is a magnetic disk, 10゜14.15.17.2
3.25.29.31 is a register, 11 is a memory access/sequence control unit, 12 is a register control circuit, 13
16.30 is an arithmetic unit, 18 is a memory array address register/decoder unit, 19 is a timing generation unit, 24 is a memory array, 40 is a processing unit, 41 is a control memory, 42, 43, 44, 45 , 49. 51 is a register, 47 is an address decoder, 48 is a timing generator, and 50 is a meso array. Part 1 (2) 11-

Claims (1)

[Claims] A central processing unit of a data processing system whose main purpose is to process and/or store two-dimensional data;
A memory access control system that generates a predetermined address within a memory device by giving the memory device a direction for accessing each block of data during memory access from an external storage device and an input/output device. method.