JPS5992624A - Ｃｍｏｓ論理回路 - Google Patents

Ｃｍｏｓ論理回路

Info

Publication number
JPS5992624A
JPS5992624A JP57202929A JP20292982A JPS5992624A JP S5992624 A JPS5992624 A JP S5992624A JP 57202929 A JP57202929 A JP 57202929A JP 20292982 A JP20292982 A JP 20292982A JP S5992624 A JPS5992624 A JP S5992624A
Authority
JP
Japan
Prior art keywords
logic
circuit
type
setting circuit
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57202929A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0446015B2 (enExample
Inventor
Hideji Koike
秀治 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57202929A priority Critical patent/JPS5992624A/ja
Publication of JPS5992624A publication Critical patent/JPS5992624A/ja
Publication of JPH0446015B2 publication Critical patent/JPH0446015B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H03K19/09482—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors using a combination of enhancement and depletion transistors
    • H03K19/09485—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
JP57202929A 1982-11-19 1982-11-19 Ｃｍｏｓ論理回路 Granted JPS5992624A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57202929A JPS5992624A (ja) 1982-11-19 1982-11-19 Ｃｍｏｓ論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57202929A JPS5992624A (ja) 1982-11-19 1982-11-19 Ｃｍｏｓ論理回路

Publications (2)

Publication Number Publication Date
JPS5992624A true JPS5992624A (ja) 1984-05-28
JPH0446015B2 JPH0446015B2 (enExample) 1992-07-28

Family

ID=16465492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57202929A Granted JPS5992624A (ja) 1982-11-19 1982-11-19 Ｃｍｏｓ論理回路

Country Status (1)

Country Link
JP (1) JPS5992624A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614841A (en) * 1993-12-24 1997-03-25 Bull S.A. Frequency multiplier using XOR/NXOR gates which have equal propagation delays

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342456U (enExample) * 1976-09-16 1978-04-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5342456U (enExample) * 1976-09-16 1978-04-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614841A (en) * 1993-12-24 1997-03-25 Bull S.A. Frequency multiplier using XOR/NXOR gates which have equal propagation delays

Also Published As

Publication number Publication date
JPH0446015B2 (enExample) 1992-07-28

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