JPS5988838A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5988838A
JPS5988838A JP57197532A JP19753282A JPS5988838A JP S5988838 A JPS5988838 A JP S5988838A JP 57197532 A JP57197532 A JP 57197532A JP 19753282 A JP19753282 A JP 19753282A JP S5988838 A JPS5988838 A JP S5988838A
Authority
JP
Japan
Prior art keywords
chip
silver
gold foil
gold
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57197532A
Other languages
Japanese (ja)
Inventor
Mamoru Ito
護 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57197532A priority Critical patent/JPS5988838A/en
Publication of JPS5988838A publication Critical patent/JPS5988838A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract

PURPOSE:To prevent silver migration by protruding a fringe of a bonding medium outward of a chip when fixing the chip to a substrate having silver coating through the bonding medium. CONSTITUTION:A tab 5 of a lead frame is covered with silver coating 13 and gold foil 11 (bonding medium) which is larger than a chip 6 is fixed to a center of said tab by welding. After that, the chip 6 is attached to a center of the gold foil 11 by rubbing in a predetermined temperature and is fixed by producing Au- Si eutectic layer. As gold foil protrudes outward from the fringe of the chip 6, in a revere-bias test of the chip 6 of n-p-n type in which a collector lead 4 is used as an anode under the condition of high temperature and high humidity, leak current from silver coat 13 is extremely small and deterioration of resistance to the pressure of te chip caused by silver migration hardly occurs resulting in the improvement of reliability.

Description

【発明の詳細な説明】 本発明は半導体装置、特に表面を銀被膜で被った基板に
接合材を介してチップを固定した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a chip is fixed to a substrate whose surface is covered with a silver film via a bonding material.

半導体装置の一つであるトランジスタとして、第１図に
示すような構造のものが一般に知られている。このトラ
ンジスタ１は、一端（内端）をレジンパッケージ２内に
それぞれ突入させる３本のリード３を有している。中央
のり一ド３はコレクタリード４となり、内端の幅広のタ
ブ部５にはトランジスタ用チップ６が固定されている。2. Description of the Related Art As a transistor, which is one type of semiconductor device, one having a structure as shown in FIG. 1 is generally known. This transistor 1 has three leads 3 whose one end (inner end) extends into the resin package 2, respectively. The central glue 3 serves as a collector lead 4, and a transistor chip 6 is fixed to a wide tab portion 5 at the inner end.

また、他のり−ド３はエミッタリード７、ベースリード
８となり、これらのリード３の内端の幅広のワイヤボン
ディング部９と前記チップ６の電極（特に図示せず）と
は導線（ワイヤ）１０で接続されている。さらに、各リ
ード３の内端部、チップ６およびワイヤ１０はレジンモ
ールドによって形成されるレジンパッケージ２で被覆さ
れている。したがって、レジンパッケージ２からは３本
のリード３の他端（外端）のみが平行に突出する構造と
なっている。Further, the other leads 3 become an emitter lead 7 and a base lead 8, and a wide wire bonding part 9 at the inner end of these leads 3 and an electrode (not particularly shown) of the chip 6 are connected to a conductor (wire) 10. connected with. Further, the inner end of each lead 3, chip 6 and wire 10 are covered with a resin package 2 formed by resin molding. Therefore, the structure is such that only the other ends (outer ends) of the three leads 3 protrude from the resin package 2 in parallel.

ところで、前記チップ６は第２図の断面図でその詳細を
示すように、タブ部５には金箔１１を介して固定される
。また、タブ部５は４２７０イ等の鉄−ニッケル系合金
の母材１２の表面に銀被膜（銀めっき膜）１３を形成し
た構造となっている。By the way, the chip 6 is fixed to the tab portion 5 via a gold foil 11, as shown in detail in the sectional view of FIG. Further, the tab portion 5 has a structure in which a silver coating (silver plating film) 13 is formed on the surface of a base material 12 of an iron-nickel alloy such as 4270I.

そして、チップ取付時には、タブ部５に金箔１１を抵抗
溶接によって固定した稜に、チップ６を所定温度下で金
箔１１にこすり付けることにより、金とシリコンの共晶
合金化によって固定する。When mounting the chip, the chip 6 is rubbed against the gold foil 11 at a predetermined temperature on the edge of the tab portion 5 where the gold foil 11 is fixed by resistance welding, thereby fixing the chip 6 by forming a eutectic alloy of gold and silicon.

しかし、このような従来のトランジスタ１は、次のよう
な欠点があることが本発明者によって明らかとなった。However, the inventor of the present invention has found that such a conventional transistor 1 has the following drawbacks.

すなわち、従来のトランジスタ１は、金が高価であるこ
とから金箔の使用量を抑える努力が払われていて、接合
性を充分維持できる程度を限度とする大きさの金箔を用
いることから、チップ幅に対して金箔幅が小さくなる。In other words, in the conventional transistor 1, since gold is expensive, efforts are made to reduce the amount of gold foil used, and the chip width is The width of the gold leaf is smaller than that of the gold leaf.

たとえば、チップ６の最大部幅が０．６４ｍに対して、
金箔幅は０．５　ｔｒｒｍ　（金箔厚さ５μｍ）となっ
ている。この結果、チップ端部が金−シリコン共晶層１
４（図中金箔の表層部）とは異なる金、シリコン、銀か
らなる金−シリコンー銀共晶層１５（クロスハツチング
領域）を介して銀被膜１３に電気的に接触する。そして
、コレクタリード４が陽極となるＮＰＮ形のチップ６の
場合には、高温高湿逆バイアス試験下では、銀のイオン
化、それに続く陽極部における銀の析出（いわゆるマイ
グレーション）が生じてしまい、電極間等でショートを
生じ易くなり、トランジスタ１の耐圧劣化を引き起こし
てしまう。For example, when the maximum width of chip 6 is 0.64 m,
The gold foil width is 0.5 trrm (gold foil thickness 5 μm). As a result, the edge of the chip has a gold-silicon eutectic layer 1.
It electrically contacts the silver film 13 through a gold-silicon-silver eutectic layer 15 (cross-hatched area) made of gold, silicon, and silver different from that shown in FIG. In the case of an NPN type chip 6 in which the collector lead 4 serves as an anode, under a high temperature, high humidity reverse bias test, silver ionization and subsequent silver precipitation (so-called migration) at the anode part occur, resulting in electrode Short-circuits are likely to occur between the transistors 1 and 2, resulting in deterioration of the withstand voltage of the transistor 1.

すなわち、金箔１１および金−シリコン共晶層１４以外
の銀被膜１３および金−シリコンー銀共晶層１５間でも
リーク電流が発生し、電気化学反応によって銀の析出成
長が生じる。That is, leakage current is generated between the silver film 13 and the gold-silicon-silver eutectic layer 15 other than the gold foil 11 and the gold-silicon eutectic layer 14, and the electrochemical reaction causes silver precipitation and growth.

したがって、本発明の目的は銀被膜上に接合材を介して
チップを固定する構造の半導体装置において、銀マイグ
レーションの生じない信頼度の高い半導体装置を提供す
ることにある。Therefore, an object of the present invention is to provide a highly reliable semiconductor device in which silver migration does not occur in a semiconductor device having a structure in which a chip is fixed on a silver film via a bonding material.

このような目的を達成するために本発明は、表面に銀被
膜を有する基板上に接合材を介してチップを固定した半
導体装置において、前記接合材の周縁はチップの周縁よ
りも外方に突出しているものであって、銀マイグレーシ
ョンが生じないようになっている。In order to achieve such an object, the present invention provides a semiconductor device in which a chip is fixed on a substrate having a silver coating on the surface via a bonding material, in which the periphery of the bonding material protrudes outward beyond the periphery of the chip. It is designed to prevent silver migration from occurring.

以下、実施例により本発明を説明する。The present invention will be explained below with reference to Examples.

第３図は本発明の一実施例によるトランジスタの一部を
切り欠いた状態を示す平面図、第４図は同じくチップ取
付状態を示す要部断面図、第５図（ａ）　、　（ｂ）は
同じくトランジスタの組立例を示す平面図である、この
実施例のトランジスタ１は、平行に並ぶ３本のリード３
を有している。リード３は常用の金属、たとえば４２７
０イから碌っている１、中央のリード３はコレクタリー
ド４となり、内端（右端）には幅広のタブ部５を形作っ
ている。また、他のリード３はエミッタリード７および
ベースリード８となり、ともに内端（右端）には幅広の
ワイヤボンディング部９を有している。前記ワイヤボン
ディング部９およびタブ部５は第４図および第５１％＋
　（〜に示すように母材１２の表面に銀めっき等によっ
て厚さ５μｍ程度の銀被膜１３が設けられている。FIG. 3 is a plan view showing a partially cut away state of a transistor according to an embodiment of the present invention, FIG. 4 is a cross-sectional view of the main part similarly showing a state in which a chip is attached, and FIGS. 5(a) and (b). 1 is a plan view showing an example of transistor assembly. The transistor 1 of this embodiment has three leads 3 arranged in parallel.
have. Lead 3 is a commonly used metal, for example 427
The center lead 3 extending from 0 is a collector lead 4, and a wide tab portion 5 is formed at the inner end (right end). The other leads 3 are an emitter lead 7 and a base lead 8, both of which have a wide wire bonding portion 9 at their inner ends (right ends). The wire bonding part 9 and the tab part 5 are shown in FIG. 4 and 51%+.
(As shown in ~, a silver coating 13 with a thickness of about 5 μm is provided on the surface of the base material 12 by silver plating or the like.

一方、前記タブ５の主面には金箔１１がスポット溶接等
の抵抗溶接によって固定されるとともに、この金箔１１
上にはトランジスタ用のチップ６が固定されている。金
箔１１Ｆｉ−辺の長さが０．４〜０．６４ｍ程度のチッ
プ６よりも犬きく、チップ６０周縁よりも数十〜数百μ
ｍ突出するようになっている。チップ６はチップ下面部
分で金とシリコンの共晶で接合される。チップ６のタブ
部５への接合に用いる接合材は金箔でなく金めつき層で
あってもチップ６の接合には何等支障はない。そして、
この金めつき層の場合にも、チップ６０周縁から金めつ
き層が数十〜数百μｍ突出するようにチップ６は固定さ
れている。On the other hand, a gold foil 11 is fixed to the main surface of the tab 5 by resistance welding such as spot welding.
A transistor chip 6 is fixed on the top. Gold foil 11Fi - sharper than chip 6 with a side length of about 0.4 to 0.64 m, several tens to several hundred microns thicker than the periphery of chip 60
m It is designed to protrude. The chip 6 is bonded with gold and silicon eutectic at the lower surface of the chip. Even if the bonding material used to bond the chip 6 to the tab portion 5 is a gold plating layer instead of gold foil, there is no problem in bonding the chip 6. and,
In the case of this gold plating layer as well, the chip 6 is fixed so that the gold plating layer protrudes from the periphery of the chip 60 by several tens to hundreds of μm.

他方、第３図で示すように、チップ６の電極（特に図示
せず）とエミッタリード７およびベースリード８のワイ
ヤボンディング部９とは金線のようなワイヤ１０で接続
されている。さらに、各リード３の内端部、チップ６、
ワイヤ１０はレジンパッケージ２によって被われている
。On the other hand, as shown in FIG. 3, the electrodes (not particularly shown) of the chip 6 and the wire bonding portions 9 of the emitter leads 7 and base leads 8 are connected by wires 10 such as gold wires. Furthermore, the inner end of each lead 3, the chip 6,
The wire 10 is covered with a resin package 2.

このようなトランジスタ１は第５図（ａ）　、　（ｂ）
に示すような段階を経て組み立てられる。すなわち、同
図（ａ）に示すように、トランジスタ１０組み立てにあ
っては、リードフレーム１６を基にして組み立てが行な
われる。リードフレーム１６は前記３本のリード３と、
これらリード３を連結するダム片１７および枠片１８と
からなっていて、リード３の先端（内端）はクロスハツ
チングで示すように銀被膜１３が表面に設けられている
。そこで、組立にあっては、同図（ｂ）に示すように、
タブ部５の主面中央にチップ６よりも大きな金箔１１を
溶接して固定した彼、所望温度下でチップ６１ｒ：金箔
１１の中央にこすり付けて金−シリコン共晶層を生じさ
せ、チップ６をタブ部５に固定する。その後、各リード
３の内端部、チップ６、ワイヤ１０をレジンモールドに
よって形成したレジンパッケージ２で被う。さらに、不
要な砕片１８．ダム片１７を切断除去することによって
、第３図で示すようなトランジスタ１を製造する。Such a transistor 1 is shown in FIGS. 5(a) and 5(b).
It is assembled through the steps shown below. That is, as shown in FIG. 2A, the transistor 10 is assembled based on the lead frame 16. The lead frame 16 includes the three leads 3,
It consists of a dam piece 17 and a frame piece 18 that connect these leads 3, and the tips (inner ends) of the leads 3 are provided with a silver coating 13 on the surface as shown by cross hatching. Therefore, when assembling, as shown in Figure (b),
A gold foil 11 larger than the chip 6 is welded and fixed to the center of the main surface of the tab portion 5, and the chip 61r is rubbed against the center of the gold foil 11 at a desired temperature to form a gold-silicon eutectic layer. is fixed to the tab portion 5. Thereafter, the inner end of each lead 3, chip 6, and wire 10 are covered with a resin package 2 formed by resin molding. Furthermore, unnecessary debris 18. By cutting and removing the dam piece 17, a transistor 1 as shown in FIG. 3 is manufactured.

このようなトランジスタ１では、チップ６はチップ６よ
りも大きな金箔１１からなる接合材の中央に固定される
ことから、チップ６の周縁から接合材の周縁は突出する
。この結果、コレクタリード４が陽極となるＮＰＮ形の
チップ６において、高温高湿逆バイアス試験を行った場
合、リーク電流のほとんどは接合材分流れ、従来のよう
な銀被膜１３部分からのリーク電流は極めて少い。この
結果、水分と高い電圧のもとにおいても銀のイオン化、
析出は生じにくくなり、銀マイグレーションによるチッ
プの耐圧劣化は起きにくくなり、信頼性の向上が図れる
。In such a transistor 1, since the chip 6 is fixed at the center of the bonding material made of gold foil 11 which is larger than the chip 6, the periphery of the bonding material protrudes from the periphery of the chip 6. As a result, when a high-temperature, high-humidity reverse bias test is performed on an NPN type chip 6 in which the collector lead 4 serves as an anode, most of the leakage current flows from the bonding material, whereas the leakage current from the silver coating 13 part as in the conventional case. are extremely rare. As a result, silver ionization occurs even under moisture and high voltage.
Precipitation is less likely to occur, chip breakdown voltage deterioration due to silver migration is less likely to occur, and reliability can be improved.

なお、本発明は前記実施例に限定されるものではない また、本発明は他の半導体装置にも適用できる。Note that the present invention is not limited to the above embodiments. Further, the present invention can be applied to other semiconductor devices.

以上のように、本発明によればチップ固定部の基板表面
に銀被膜を有する構造の半導体装置において、銀マイグ
レーションの発生を防止することができるため信頼性の
高い半導体装置を提供することができる。As described above, according to the present invention, it is possible to prevent silver migration from occurring in a semiconductor device having a structure in which the substrate surface of the chip fixing portion has a silver coating, thereby providing a highly reliable semiconductor device. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のトランジスタの一部を切り欠いた状態を
示す平面図、 第２図は同じくチップ取付状態を示す要部断面図、 第３図は本発明の一実施例によるトランジスタの一部を
切り欠いた状態を示す平面図、第４図は同じくチップ取
付状態を示す要部断面図・ 第５図（ａ）　、　（ｂ）は同じくトランジスタの組立
例を示す平面図である。 １・・・トランジスタ、３・・・リード、４・・・コレ
クタリード、５・・・タブ部、６・・・チップ、１０・
・・ワイヤ、１１・・・金箔、１３・・・銀被膜、１６
・・・リードフレー第　　１　　図 第　　２　図 第　　３　図 第　　４　　図 第　　５　　図Fig. 1 is a plan view showing a conventional transistor with a part cut away; Fig. 2 is a cross-sectional view of the main part similarly showing a state in which the chip is attached; Fig. 3 is a part of a transistor according to an embodiment of the present invention. FIG. 4 is a sectional view of the main part showing the state in which the chip is attached, and FIGS. 5(a) and 5(b) are plan views showing an example of transistor assembly. DESCRIPTION OF SYMBOLS 1... Transistor, 3... Lead, 4... Collector lead, 5... Tab part, 6... Chip, 10...
...Wire, 11...Gold foil, 13...Silver coating, 16
... Lead fly Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] １、表面に銀被膜を有する基板上に接合材を介してチッ
プを固定した半導体装置において、前記接合材の周縁は
チップの周縁よりも外方に突出していることを特徴とす
る半導体装置２、1. A semiconductor device in which a chip is fixed to a substrate having a silver coating on the surface via a bonding material, wherein the periphery of the bonding material protrudes outward beyond the periphery of the chip.
JP57197532A 1982-11-12 1982-11-12 Semiconductor device Pending JPS5988838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57197532A JPS5988838A (en) 1982-11-12 1982-11-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57197532A JPS5988838A (en) 1982-11-12 1982-11-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5988838A true JPS5988838A (en) 1984-05-22

Family

ID=16376028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57197532A Pending JPS5988838A (en) 1982-11-12 1982-11-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5988838A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426275A (en) * 1992-08-04 1995-06-20 Alps Electric Co., Ltd. Seesaw switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426275A (en) * 1992-08-04 1995-06-20 Alps Electric Co., Ltd. Seesaw switch

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