JPS5988790A - Ecd driving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION More specifically, the present invention relates to an ECD drive circuit suitable for quality inspection of nuclear ECD drive circuits.

In general, it is true that there are some defective products mixed in when manufacturing circuits, and therefore, quality inspection MQ
It is also true that there is a process for removing defective products.
).

As a matter of course, it is important to know how to prevent the production of defective products, but also how to remove the defective products in a simple manner when a defective product is unfortunately produced.

By the way, since the ECD drive circuit realizes low power consumption by making maximum use of the memory characteristics of the ECD, it is necessary to eliminate as much as possible factors that inhibit the memory characteristics.

In the ID CD drive circuit, if the insulation resistance between the output terminals (between the terminals that supply power to the segment electrodes of the ECD) decreases, the charges stored in the segments will be released through the insulation resistance. This will hinder the expected memory characteristics of ECD.

Therefore, it is essential to inspect the insulation resistance between the output terminals of the ECD drive circuit.

However, in conventional ECD drive circuits, the insulation resistance between the output terminals of the two 1]" forces ψ1Mγ (at least 2-)) to be measured is stored in the circuit in a memory state. The logic state of the control circuit must be adjusted seven times so that

And to measure the insulation resistance between all output terminals,
The logic states of the control circuits must be set one after another in response to the output terminals that are the target of the 1T11 constant. It had the following drawbacks.

In view of the following two drawbacks, the object of the present invention is to reduce the insulation resistance between all output terminals to 4111 constant 1-4.
) It is possible to measure the insulation resistance between all output terminals by inputting a set signal once per VC.
[σ+1i11 path is provided.

The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram of a pivoting circuit illustrating an embodiment of the present invention.

In FIG. 1, 1 is a plurality of segment electrodes 1a 111n and 1. - multiple segment electrodes 1a 11 ・1 n etc. four times 1 common electrode 1
EC material and electrolytic solution (shown in the figure -.1-) are external between x and electrochromic Mizuno, display element -r (hereinafter referred to as ECD), 2 is coloring power 1 ) w and electric power for erasing I) e, and a power source that outputs voltages V'dd and Vss Y for operating circuits 4.5 and 6, which will be described later, 6
is a power supply means for driving the ECI) 1, and the power supply means 6 is for driving each segment electrode 1
There are switch circuits 6a 61 and 3nY provided corresponding to each of a 1i -1n, and the switch circuit 6a
Each of the internal circuit configurations 61...6n has a circuit configuration.

For example, as shown in FIG.
The switch circuit 61 is composed of a P-channel type MO8+ transistor 101 and an N-channel type Mos+ transistor 111, and the switch circuit 61 is composed of a P-channel type MO8+ transistor 111.
- transistor 10n and N channel type MOS +- transistor 11n).

Reference numeral 4 denotes 10 stages of forced power stop circuits for forcibly outputting a power stop control signal to the power supply means 6.・41...4n are provided, and for example, as shown in the figure, the gate 1 circuit 4a is composed of NA, ND gate 1-12a and AN1) gate 13a, and Gate circuit 41 is NAN
The gate circuit 4n is composed of a D gate 121 and an AND gate 1-13i, and the gate circuit 4n is composed of a NAND gate 12n and an AN
D gate 16n.

5 is a signal E a 0.5 for setting each part of the segment electrodes 1a, . . . , 11, . ,
E 1-E n , and signals W a , , W i
-W n is a control circuit composed of an oscillation circuit, a frequency dividing circuit, a clock circuit, a tecoder, etc., and each of the signals E a -E i-E n of the control circuit 5 is connected to a NAND gate 12 a - 12 i, respectively. -12n, and the signals W a -W i -W n of the control circuit 5 are each connected to AND
The input terminals of the gates 1-13a to 13i-13n are connected to each other so as to be supplied with an input terminal.

6BANA N T,) Gate 12 a -12i -
Each other input terminal of 12n and AND game 1-13a...
This is a manual inspection means for supplying the signal Ps to each of the other input terminals of 161...13n, and one end of the input means 6 is connected to a voltage R8vC with logic "O", and the other end is connected to A voltage that is logic “1” is applied via the pull-up resistor 6b.
It consists of a switch 6a connected to ddK.

The operation will be explained below.

The control circuit 5 performs three types of control to bring the segment electrodes 1a, 11, . . . 1n into a desired display state. When the electrode 1n is placed in a coloring or decoloring memory state, the control circuit 5 outputs signals F, a, Ei, En and signals Wa, W i , W n as shown in Table 1 below.

Table 1 On the other hand, switch 6a of manual means B is in unrelated A/1 state and 1
In the normal case, the input means 6 may be
- No. 1 Ps is sent to the forced power stop circuit means 4, and the NAN
D game-1-12a 12 i-121'l and AN
D gate 15 a −= 13 i −13n &; l
- All are in game 1/open state.

Therefore, by the signal Wa−Wari)'', AND game 1.13
a outputs logic ``1'', and N-channel type MOS l
- Bring the range metal 11a' into the YON state, and apply coloring power pw to the -hygment electrode 1a.

In addition, the NAND game 1.1 is generated by the signal E+− ring processing 1.1”.
2I outputs the logic "]", turns on the P channel type MOS transistor 10i (not shown), and further applies decoloring power Pe to the segment electrode 11.

Therefore, the segment electric llf! , 1a operates in a coloring drive state, and the segment electrode 11 operates in a color erasing drive state.

In addition, the signal En-ring 90'' and the signal Wn-ring 1ゝO
" is a NAND game) 12n output is a logic coin A
Since the logic 1-13 of the ND gate 13n is 0, both the P-channel MOS transistor 10n and the N-channel MOS transistor 11n are OFF.
state and the segment electrode 1nY memory state.

The following is the constant operation of 11n.

Next, when the switch 6a of the human power means 6 is operated to set the output signal ps of the input means 6 to "0", the NAND games 1-12a...121-12 of the forced power stop circuit means 4 are
n and A N I) Gate 13a・-13i・13
All gates are closed, and signals Ea...EI...En and signals Wa...Wi from the control circuit 5 are output.
- Power supply means 6 regardless of the logic state of W n.
P channel type MO8+・Landisc 10a-10i
-1On and N channel (II M □ S transistor 11 a 11 i -1I n is all "C0FF
state, all segments'f% 4iiyi +
111...1n at the same time as the memory state and 1-ro.

As mentioned above (according to the present invention, the ECI) I!
I! When testing the insulation resistance between the output terminals of the ECD of 11 circuits, all segment electrodes are brought into a testable state with just 10 inputs using manual means, so the inspection work can be completed in an extremely short time. The ECD drive system has the advantage of terminating the process, and also has the effect of drastically reducing the number of input errors due to the simplicity of the manual setting process.

Although a switch knob 6a was used as the manual means 6 in this embodiment, a terminal was provided at Kili instead of this switch 6a, and a logic "0" signal was input from this terminal from a probe etc. of η[≦. The supply τ filter may also be configured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an ECD drive circuit showing an embodiment of the present invention. 1. No. 1 CD1 1a -l i 1n...Segment electrode, 2
・・Power supply, 3 ・・Power supply means, 6a・6I・
6n...Switch circuit, 4...Forced power stop circuit means, 4a...-4i -4n --Gate circuit. 5... Control '11 circuit, 6... Input means, 10 a ・10 i ・= 1 On -P channel type MOS transistor, 11 a-11i-1I n・-=・, N channel type M
O8)・Lansistor, 12a-12i-1'In--NAND gate, 13a-i3i・-j3n-・-
AN D goo 1-.

Claims (1)

[Claims] (E CI) having a plurality of segment electrodes, a power source that outputs electric power for selectively coloring and decolorizing the coloring electrodes, and a power source that outputs electric power for selectively coloring and decolorizing the coloring electrodes; and a control circuit that controls the power supply means to bring the plurality of segment electrodes of the ECD into a desired display state.
The CD drive circuit includes forced power stop circuit means for controlling the power supply means to stop supplying power from the power source to all of the segment electrodes, and a forced power stop circuit means for operating the forced power stop circuit means. An ECD drive circuit characterized by being equipped with manual means for inspection.