JP2659663B2 - LCD drive circuit with port function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an L port having a port function.
The present invention relates to a CD (liquid crystal display) drive circuit.

[0002]

2. Description of the Related Art In a device in which an integrated circuit is incorporated, the same integrated circuit can be allocated regardless of the number of drive signal terminals, the number of data signal input terminals, the number of data signal output terminals, and the like required for the integrated circuit. It has been considered to make the integrated circuit versatile so that it can be used. For example,
In a device incorporating an integrated circuit having ten terminals that can be electrically connected to the liquid crystal display and that includes an LCD driving circuit for driving the liquid crystal display, a driving signal of the liquid crystal display among the ten terminals is provided. When only eight terminals are required, the remaining two terminals are used as terminals for an input port or an output port.

[0003]

In such an integrated circuit, the use of the terminals is not set unless the operation mode for each terminal is determined. That is, after the device is reset by turning on the power, the program is read and the control means such as the CPU starts operating, and the terminal is used for any mode only in response to the mode selection command generated by the control means. Or set. Until then, the manufacturer's use settings are predetermined. Therefore, when a terminal for electrically connecting to a liquid crystal display is used as an input port terminal or an output port terminal of a data signal,
During the operation mode indefinite period after the reset until the terminal use setting of the device is completed, if the output state from the integrated circuit to the terminal and the state of the external circuit connected to the terminal are not appropriate, the element in the integrated circuit However, there is a problem in that a defect such as destruction is caused.

An object of the present invention is to provide an LCD drive having a port function capable of preventing occurrence of a problem with an external circuit connected to a terminal during a period from reset to completion of setting of terminal use. Is to provide a circuit.

[0005]

An LCD drive circuit having a port function according to the present invention comprises a terminal for connection to a liquid crystal display or a port, a liquid crystal display drive mode and a port as operation modes after a reset operation. Means for generating a mode selection command indicating one of the modes, and driving potential generation for selectively supplying one of a plurality of potentials to a terminal according to display data when the mode selection command indicates a liquid crystal display driving mode. LC having a port function, comprising: port means for inputting or outputting data via a terminal when the mode selection command indicates the port mode.
D drive circuit, wherein the drive potential generating means includes a transistor having a large on-resistance, and turns on the transistor until a mode selection command is generated after a reset operation, and applies a predetermined potential to the terminal via the transistor. It is characterized by being supplied to.

[0006]

According to the present invention, a transistor having a large on-resistance is provided, and the transistor is turned on to supply a predetermined potential to the terminal during a period until a mode selection command is generated after the reset operation. Acts as an up resistor.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an LCD driving circuit having an input / output port function according to the present invention. In this circuit, the terminal PAD is one of a plurality of terminals to which an LCD (not shown) is connected. LCD control circuit 1
Generates a potential selection signal for each row and column by decoding a display data signal supplied from a CPU (not shown) for display on the LCD. As shown in the figure, the LCD control circuit 1 generates a potential selection signal composed of four outputs for one terminal PAD. The output of the LCD control circuit 1 is connected to three NAND circuits 2 to 4 and an AND circuit 5. The NAND circuits 2 to 4 have three inputs, and
The circuit 5 has two inputs. The output signal of the LCD control circuit 1 is supplied to the second input of each of the NAND circuits 2 to 4 and the AND circuit 5.

The output of the NAND circuit 2 is connected to the gate of the transistor 6. The potential V3 is applied to the drain of the transistor 6, and the source is connected to the line L to the terminal PAD. A switch circuit 7 is connected to an output of the NAND circuit 3. The switch circuit 7 is a NAND
The circuit 3 is turned on according to the output level of the circuit 3, and at that time, the potential V2 is relayed to the line L. A switch circuit 8 is connected to an output of the NAND circuit 4. Switch circuit 8
Is turned on according to the output level of the NAND circuit 4, and at that time, the potential V1 is relayed to the line L. The output of the AND circuit 5 is connected to the gate of the transistor 10 via the OR circuit 9. A potential V0 which is a ground potential is applied to a source of the transistor 10, and a drain is connected to a line L to a terminal PAD. The transistor 6 is a P-channel field-effect transistor,
The transistor 10 is an N-channel field effect transistor.

In the LCD driving circuit according to the present invention, four D flip-flops 11 to 14 are provided. The D terminal of each of the flip-flops 11 to 14 is connected to a data bus (DATA BUS), and the R terminal is supplied with a reset signal RST. The flip-flop 11 holds the selection data SEL supplied to the D terminal in response to the write command signal W · SEL supplied to the C terminal and outputs it from the Q terminal. The Q terminal of the flip-flop 11 is connected to the NAND circuits 2 to 4 and the AND circuit 5
Is connected to a first input which is an inverting input of The flip-flop 12 receives the write command signal W supplied to its C terminal.
-The input / output switching data DDR supplied to the D terminal according to DDR is held and output from the Q terminal. The AND circuit 15 is connected to the Q terminal of the flip-flop 11.
The AND circuit 15 calculates the logical product of the selection data SEL and the input / output switching data DDR. The flip-flop 13 holds the output data DR supplied to the D terminal in response to the write command signal W • PORT supplied to the C terminal and outputs the output data DR from the Q terminal. A three-state buffer 16 is connected to the Q terminal of the flip-flop 13. The three-state buffer 16 relays the output data DR to the line L when the output of the AND circuit 15 is at a high level. The flip-flop 14 is provided with a write command signal W · LC supplied to its C terminal.
The control signal LCDE supplied to the D terminal according to DE is held and output from the Q terminal. Q of flip-flop 14
The terminal is connected to the third input of each of the NAND circuits 2 to 4 and the inverted input of the OR circuit 9. The OR circuit 9 performs an OR operation on the output data of the AND circuit 5 and the control signal LCDE held in the flip-flop 14, and supplies the result to the gate of the transistor 10.

The AND circuit 17 takes the logical product of the select data SEL and the logical level of the line L. A three-state buffer 18 is connected to the output of the AND circuit 17. The 3-state buffer 18 has a read command signal R / POR.
When T is supplied, the output data of the AND circuit 17 is relayed to a data bus (DATA BUS). Write command signals W · SEL, W · DDR, W · POR described above
T, W • LCDE, read command signal R • PORT, selection data SEL, input / output switching data DDR, output level data DR, and control signal LCDE are individually generated from the CPU according to the execution of the CPU program.
The selection data SEL goes to a low level indicating logic "0" when the operation mode in the circuit is set to the LCD drive mode, and goes to a high level indicating logic "1" when set to the input or output port mode. When selecting the input port mode, the input / output switching data DDR goes to a low level indicating logic "0",
When the output port mode is selected, it becomes a high level indicating a logic "1". The output data DR is transmission data itself that determines an output level when used in the output port mode. The control signal LCDE is data indicating ON / OFF of driving of the LCD when used as the LCD driving mode.
A low level indicating logic "0" indicates drive-off, and a high level indicating logic "1" indicates drive-on. The control signal LCDE is also data indicating whether or not the transistor 10 is used as a pull-down resistor when used in the input or output port mode. A low level indicating logic “0” indicates a non-pull-down resistance state, and a logic “1”. "Indicates a pull-down resistance state.

The CPU generates a read command signal R • PORT in accordance with the execution of the program to generate the read command signal R • PORT.
When a PORT occurs, data is read from the data bus (DATA BUS). Further, a reset signal RST is generated from a reset signal generation circuit (not shown) when the power is turned on. The potentials V0 to V3 are potentials for driving the LCD, and have a relationship of V0 <V1 <V2 <V3. Potential V0
Is equal to the potential Vss indicating the logic “0” of the input / output data.
Although the potential indicating the logic "1" of the input / output data is Vdd,
Potential Vdd need not be equal to potential V3.

In the LCD driving circuit having the above-described configuration,
When the power is turned on, a high-level reset signal RST is generated, and the flip-flop 1 is turned on in response to the reset signal RST.
Each of 1 to 14 is reset. As a result, the level of the Q terminal of each of the flip-flops 11 to 14 is forcibly set to the low level, so that the selection data SEL indicating the use as the LCD drive mode and the control signal LCDE indicating the drive OFF of the LCD are generated. It will be. NAND
The low level of the third input of circuits 2-4 causes its output to go high. However, since the gate of the transistor 6 and the control terminal of the switch circuits 7 and 8 are inverting inputs, both the transistor 6 and the switch circuits 7 and 8 are turned off. Therefore, none of the potentials V1 to V3 is supplied to the line L to the terminal PAD.

On the other hand, the OR circuit 9 produces a high-level output because its second input, which is its inverted input, is at a low level. This high level output causes transistor 10 to turn on. However, the ON resistance of the transistor 10 is several KΩ or more.
The transistor 10 acts as a pull-down resistor because it is as large as several tens of KΩ. Therefore, the potential V
0 is supplied to the line L via the transistor 10.
In other words, after the reset signal RST is generated, the operation of the terminal PAD during the operation mode indefinite period from when the CPU issues one of the selection data SEL, the input / output switching data DDR, and the control signal LCDE and holds and outputs the data to the corresponding flip-flop. , A potential V0 is applied via a pull-down resistor by the transistor 10.

When the operation mode in the circuit for the terminal PAD is the LCD drive mode, as shown in FIG. 2A, during the operation mode undetermined period after the reset period in which the reset signal RST is generated, The selection data SEL and the control signal LCDE output from the flip-flops 11 and 14 are both low as shown in FIGS. 2B and 2C, and the potential V0 is applied to the terminal PAD by the transistor 10 as described above. Since the voltage is applied through the pull-down resistor, the potential V0 is applied to one terminal of the LCD connected to the terminal PAD (FIG. 2D). Then the CPU
Starts a control operation according to a program and supplies a high-level control signal LCDE indicating drive-on of the LCD together with the write command signal W · LCDE to the flip-flop 14, and the control signal LCDE is held and output from the flip-flop 14. Then, the LCD driving mode period is set. This LC
During the D drive mode period, one of the four outputs of the LCD control circuit 1 becomes high level, and the output levels of the NAND circuits 2 to 4 and the OR circuit 9 change according to the four output levels of the LCD control circuit 1. , Transistors 6, 10 and switch circuits 7, 8 are selectively turned on. Therefore, as shown in FIG. 2D, one of the potentials V0 to V3 is selectively applied to the terminal PAD, that is, one terminal of the LCD, and the LCD is driven by these.

When the operation mode of the circuit for the terminal PAD is the input port mode, as shown in FIG. 3A, during the operation mode indefinite period after the reset period in which the reset signal RST is generated, the flip-flop is turned on. Step 1
The selection data SEL, input / output switching data DDR, and control signal LCDE output from 1, 12, and 14 are shown in FIG.
As shown in (b), (c) and (d), the level is low, and the potential V0 is applied to the terminal PAD through the pull-down resistor by the transistor 10 as described above. At this time, it is conceivable that the input data has already been supplied from the external circuit connected to the terminal PAD as shown in FIG. 3E, but even in such a case, the output impedance is sufficient due to the pull-down resistance of the transistor 10. Therefore, adverse effects on the drive circuit of the external circuit can be avoided.

For example, it is assumed that the drive circuit 21 of the external circuit includes transistors 22 and 23 as shown in FIG. In this circuit, the transistor 22.2
When a low-level signal is supplied to the gate of the transistor 3, the transistor 22 is turned on and the transistor 23 is turned off.
Therefore, a current due to the potential Vdd flows from the transistor 22 to the terminal PAD and to the ground via the transistor 10 as shown by an arrow. However, since the current is limited by the pull-down resistor of the transistor 10, the breakdown of the transistor 22 can be prevented.

During an operation mode undetermined period before the input port mode is entered, the CPU starts a control operation according to a program, and sends a write command signal W ·
When the high-level selection data SEL is supplied together with SEL, and the control signal LCDE is supplied to the flip-flop 14 together with the write command signal W · LCDE, the selection data S
The EL and the control signal LCDE are held and output from the flip-flops 11 and 14 as shown in FIGS. 3B and 3D, and the input port mode period is set. During this input port mode period, the data supplied to the terminal PAD is supplied to the three-state buffer 18 via the AND circuit 17,
U, the data held in the three-state buffer 18 is transferred to the data bus (DATA B)
US) to be read by the CPU.

When the operation mode of the circuit for the terminal PAD is the output port mode, as shown in FIG. 5A, during the operation mode indefinite period after the reset period in which the reset signal RST is generated, the flip-flop is turned on. Step 1
The selection data SEL, input / output switching data DDR and control signal LCDE output from 1, 12, 14 are shown in FIG.
As shown in (b), (c) and (d), the level is low, and the potential V0 is applied to the terminal PAD via the pull-down resistor by the transistor 10 as described above (FIG. 5 (e)). . Even if a data input circuit receiving data as an external circuit is connected to the terminal PAD, the terminal PAD is fixed to the potential V0, that is, indicates a low level, so that an unstable level signal may be given to the data input circuit. Be avoided.

During an operation mode undetermined period before the output port mode is entered, the CPU starts a control operation according to a program, and sends a write command signal W ·
It supplies high-level selection data SEL together with SEL, supplies high-level input / output switching data DDR together with write command signal W.DDR to flip-flop 12, and controls flip-flop 14 together with write command signal W.LCDE. When the signal LCDE is supplied, the selection data SEL, the input / output switching data DDR and the control signal LCDE are transmitted as shown in FIG.
As shown in (b), (c), and (d), the data is held and output from the flip-flops 11, 12, and 14 to enter the output port mode period. During this output port mode period, the three-state buffer 16 is turned on by the output signal of the AND circuit 15. Further, the CPU supplies the output data DR to the flip-flop 13 via the data bus (DATA BUS), and the data DR is held in the flip-flop 13 in response to the write command signal W • PORT. The held data DR is output to the terminal PAD via the three-state buffer 16, and is supplied to an external data input circuit.

In the above embodiment, the case where the potential Vss indicating the logic "0" of the input / output data is equal to the potential V0 has been described. However, the potential Vdd indicating the logic "1" of the input / output data is changed to the potential V3. If it is equal to, the transistor 6 is turned on during the operation mode indefinite period, and it may be used as a pull-up resistor. Further, although the LCD drive circuit in the above embodiment has an input / output port function, the present invention can be applied to an LCD drive circuit having only one of the input port function and the output port function.

[0021]

As described above, in the LCD driving circuit having the port function of the present invention, a transistor having a large on-resistance is provided, and the transistor is turned on during a period until a mode selection command is issued after the reset operation. By supplying a predetermined potential to a terminal via a transistor, the transistor is used as a pull-down resistor or a pull-up resistor. Therefore, no matter which one of the liquid crystal display, the data output drive circuit and the data input circuit is connected to the terminal, a defect occurs during a period until a mode selection command is issued after a reset operation due to a pull-down resistor or a pull-up resistor of a transistor. Can be prevented from occurring. For example, when a liquid crystal display is connected to a terminal, a predetermined potential is applied to all terminals of the liquid crystal display, so that flickering of the liquid crystal display is prevented and deterioration of the liquid crystal display is also prevented. be able to. When a drive circuit for data output is connected to the terminal, even if input data is supplied from the drive circuit during the above period, the output impedance is sufficiently large due to a pull-down resistor or a pull-up resistor by a transistor. A detrimental effect on the circuit is avoided. Further, when a data input circuit is connected to the terminal as an external circuit, the terminal is fixed at a predetermined potential during the above-mentioned period, so that an unstable level signal is not given to the data input circuit.

Further, when the port input mode or the port output mode is selected, the LCDE bit operates as a pull-down (pull-up) control bit. Therefore, whether to connect a pull-down (pull-up) resistor depends on the application. Can be arbitrarily selected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of each unit when the operation mode is an LCD drive mode.

FIG. 3 is an operation waveform diagram of each unit when an operation mode is an input port mode.

FIG. 4 is a diagram illustrating a current path in a mode indefinite period before a change to an input port mode.

FIG. 5 is an operation waveform diagram of each unit when the operation mode is an output port mode.

[Description of Signs of Main Parts]

 1 LCD control circuit 6,10 Transistor 7,8 switch circuit 11-14 D flip-flop

Claims (2)

(57) [Claims] 1. A terminal for connection to a liquid crystal display or a port, means for generating a mode selection command indicating one of a liquid crystal display drive mode and a port mode as an operation mode after a reset operation, Drive potential generating means for selectively supplying one of a plurality of potentials to the terminal according to display data when the mode selection command indicates the liquid crystal display drive mode, and the mode selection command indicating the port mode An LCD drive circuit having a port function for inputting or outputting data via the terminal, the driving potential generating means including a transistor having a large on-resistance, The transistor is turned on and a predetermined potential is applied through the transistor until the mode selection command is generated after the operation. An LCD driving circuit for supplying the signal to the terminal. 2. The method according to claim 1, wherein the predetermined potential is a maximum or minimum one of the plurality of potentials and a potential equal to a logical level of 0 or 1 of data input or output by the port means. The LCD drive circuit according to claim 1, wherein