JP2001358570A - Capacitive load driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid overlapping of timing by such a way that a high voltage side output OUT by bit serving as a mutual connection point of complementary FETs 3 and 4 connected to a high voltage power supply V2 has a value of H or L, by turning the FET 3 ON after turning the FET 4 OFF or by turning the FET 4 ON after turning the FET 3 OFF, and that, in a circuit for driving a capacitive load 01, a rise timing in which the output OUT rises from L to H is delayed largely compared to a fall timing in which the output OUT falls from H to L without an increase in the circuit size of an IC with respect to suppression of a circuit loss. SOLUTION: When the high voltage side output OUT is allowed to rise from L to H, a latch output Q is made to be H at a fall of a latch signal LT at the front end of a pulse to firstly turn the FET OFF. When the latch signal LT rises to H at the rear end of the pulse through a pulse duration, the output of a NAND circuit 121 is L and the FET is turned ON. Thus, the delay time can be adjusted by the pulse width of the latch signal LT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives a plurality of bits of a data signal generated by a low-voltage power supply and drives complementary output transistors via a level shift circuit or the like provided for each input bit. And a semiconductor integrated circuit that outputs H- and L-drive signals for each bit using a power supply of a relatively high voltage, and in particular, such loads as light-emitting elements such as plasma displays, fluorescent display tubes, and EL displays. The present invention relates to a capacitive load driving circuit as a circuit that drives a capacitive load that is capacitive at the same time as having a coupling capacitance with a load of an adjacent bit (accordingly, charges and discharges the load). In the drawings, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 3 shows a schematic configuration example including a load side of a 2-bit portion adjacent to a capacitive load driving circuit of this kind which constitutes a semiconductor integrated circuit. In the figure, 01 (0
1j, 01k) are output from adjacent j-th and k-th drive circuits, and IN (INj, INk) is output from a shift register (not shown).
A data signal to be input to 1k, OUTj and OUTk are high voltage side outputs which are outputs of the respective driving circuits 01j and 01k, and Cj and Ck are loads connected to the high voltage side outputs OUTj and OUTk, respectively (for example, a plasma display). Cjk is a capacitance existing between the loads of the adjacent high-voltage-side outputs OUTj and OUTk.

Note that Cij is a capacitance existing between the loads of the high-voltage output OUTj and the high-voltage output OUTi adjacent to the lower side in the figure, and Ckl is the same as the high-voltage output OUTk and the upper in the figure. High voltage side output OUT adjacent to the side
1 and the capacity existing between the loads. Each drive circuit 0
In 1j or 01k, V1 is a low-voltage power supply of, for example, several volts, V2 is a high-voltage power supply of, for example, several tens of volts, and the power supplies V1 and V2 use the ground GND as a common potential. Normally, the terminal of the ground GND is provided separately from the high-voltage power supply V2 and the low-voltage power supply V1 in order to prevent noise interference in the semiconductor integrated circuit. However, it is not impossible to share the terminals of the separate ground GND.

A low-voltage control circuit 1 operates under a low-voltage power supply V1. The low-voltage control circuit 1 controls a PchFET 3 via a level shift circuit 2 that operates under a high-voltage power supply V2 in accordance with H or L of a data signal INj or INk. , And directly NchFET4
Are respectively controlled. Here, PchFET3 and Nch
The connection point of the FET 4 is a high voltage side output OUTj.
Alternatively, a so-called complementary connection is provided in series between the high-voltage power supply V2 and the ground GND (a terminal of the ground GND shown is provided as the high-voltage power supply V2 side) so as to be OUTk.

In this embodiment, the data signal INj or INk
Is high, the PchFET 3 is turned on and the NchFET 4 is turned off, and the high voltage side output OUTj or OUTk is driven to H. On the other hand, when the data signal INj or INk is L, the PchFET 3 is turned off and the Nch
The FET 4 is controlled to be turned on, and the high voltage side output OU
Tj or OUTk is driven low.

FIG. 4 shows a capacitive load driving circuit 0 for one bit.
1 shows an example of a detailed configuration. In the figure, each means of 11 to 16 constitutes the low voltage control circuit 1 of FIG.
Is a latch circuit, 12 and 13 are delay circuits, 14 to 16 are N
It is an OT circuit. In this example, the latch circuit 11 latches the same H or L signal as the data signal IN and outputs it to the output terminal Q every time the leading edge of the latch signal LT input as a pulse of a predetermined cycle falls. The level shift circuit 2 shifts the level of the input signal at the point A,
It is assumed that H and L level signals corresponding to the H and L levels at point A are output as the gate potential of the PchFET 3.

Therefore, as a normal operation, the data signal IN
Is high, the latch output Q is high, and the potential at the point A is low via the delay circuit 12 and the NOT circuit 14, and therefore Pc
The gate potential of hFET3 becomes L, and PchFET3 turns on. At this time, the gate potential of the NchFET 4 becomes L through the delay circuit 13 and the NOT circuit 15,
Since the chFET 4 is turned off, the high voltage side output OUT becomes H
Becomes

Conversely, when the data signal IN is at L level, Pch
The gate potential of FET3 becomes H and PchFET3 turns off, while the gate potential of NchFET4 becomes H,
Since the NchFET 4 is turned on, the high voltage side output OUT becomes L
Becomes FIG. 5 is an operation timing chart showing, in an enlarged manner, the operation of FIG. 4 near the time of input of the pulse of the latch signal LT. Next, referring to FIG. 5 while referring to FIG.
The operation when H and L are switched will be described.

Conventionally, the data signal IN and therefore the output OUT
Is changed from H to L, as shown in FIG.
After T3 is sufficiently turned off, NchFET4 is turned on,
If the data signal IN, and hence the output OUT changes from L to H, the through current flowing from the FETs 3 to 4 is reduced, and the Nch FET 4 is sufficiently turned off as shown in FIG. Has been reduced.

That is, the latch signal LT to the latch circuit 11
However, when the signal falls from H to L at time t1, the latch circuit 11 latches H or L of the data signal IN, and the output Q of the latch circuit 11 becomes H or L, respectively. When the latch circuit output Q changes from H to L as shown in FIG. 5A), when the latch signal LT falls to L at time t1, the PchFET 3 is turned off with a delay of a certain short propagation delay time T _P1 . The delay time T _P1 is the gate capacitance charging time of the delay time and PchFET3 of the level shift circuit 2 is at most, the delay time of the delay circuit 12 to as small as possible, so that PchFET3 is turned off as fast as possible.

On the other hand, the NchFET 4 has a delay time T from the time t1 by the delay circuit 13 for reducing the through current.
It is turned on with a delay of _NDL , after which the high-voltage-side output OUT changes from H to L over a fall time tf.
Conversely, in the case of a bit where the latch circuit output Q changes from L to H as shown in FIG. 5B), when the latch signal LT falls to L at time t1, the PchFET 3 must be turned on.
It is necessary to turn off the NchFET 4 in advance to reduce the through current.

When the NchFET 4 is turned off, the delay time of the delay circuit 13 is set to be as small as possible.
_The P-channel FET 3 is turned off with a delay of _N1 , while the P-ch FET 3 is turned on with a delay time T _PDL from the time point t1 via the delay circuit 12. It should be noted here that the timing at which the high-voltage output OUT rises from L to H shown in FIG. 5B is later than the timing at which the high-voltage output OUT falls from H to L shown in FIG. It is that you are. This is because when there is a capacitance between adjacent bits of the high voltage side output OUT as shown in FIG.
This is because, when the outputs OUT adjacent to each other are simultaneously inverted from the H state, if the timings are the same, the current consumption of the capacitive load driving circuit 01 becomes larger than if the timings are shifted. For this reason, in the example of FIG.
PchF of the bit where the high-voltage side output OUT changes from L to H
ET3 is a high voltage side output OUT of a bit which changes from H to L.
Is increased to the L level, the delay time T _PDL until on-drive is extended.

[0013]

As described above, when the H and L levels of the high-voltage side output OUT are switched in the capacitive load drive circuit 01, the PchFET 3 requires a high voltage in addition to the delay control for reducing the through current. Further delay is required to prevent the timing when the side output OUT rises from H to L and the timing when it falls from L to H from overlapping.

That is, the delay time T _PDL until the PchFET 3 turns on in FIG. 5 is at least the delay time T P at the timing when the high-voltage-side output OUT changes from H to L.
_It is necessary to delay the time by adding the _NDL and the falling time tf of the high voltage side output OUT. However, especially in the case of semiconductor integrated circuits manufactured by applying the fine processing rules, creating a long delay time requires a large circuit scale due to a high signal transmission speed. The scale could be even larger.

Further, when the load capacitance connected to the high-voltage side output OUT changes, the time when the output OUT changes from H to L greatly changes particularly due to the change in the fall time tf. Settings (design)
There is a possibility that the timing of the delay time T _PDL shifts, and in some cases, the output inversion timing of the bit whose high-voltage side output OUT changes from H to L and the bit which changes from L to H may overlap.

Therefore, the present invention provides a method for reducing the number of bits in which the high-voltage output OUT is inverted in the opposite direction even if the load capacitance connected to the high-voltage output OUT changes without increasing the circuit scale of the semiconductor integrated circuit. It is an object of the present invention to provide a capacitive load driving circuit capable of preventing overlapping of inversion timings.

[0017]

According to a first aspect of the present invention, there is provided a capacitive load driving circuit comprising a predetermined low voltage power supply (V1) and a predetermined high voltage power supply higher than the low voltage. One or more common potential (ground GND) -side power terminals from (V2) and low-voltage power terminals and high-voltage power terminals as non-common-potential power terminals from the low-voltage power supply and the high-voltage power supply, respectively. And a series connection of a pair of a first (such as PchFET3) and a second output transistor (such as NchFET4) between the high-voltage power terminal and a common-potential-side power terminal that can correspond to the high-voltage power terminal. One output transistor is on the high-voltage power supply terminal side, and the mutual connection point of the pair of first and second output transistors is an output terminal for each bit (high-voltage output OUT). A plurality of pairs so as to be connected to the capacitive load of the unit, and further, a bit-by-bit input terminal corresponding to each of the bit-by-bit output terminals and to which a bit signal (data signal IN) generated by the low-voltage power supply is inputted. When,
A terminal for inputting a latch signal (LT) having a predetermined pulse width (Tw) output at a predetermined period; and a bit signal provided for each of the bit-by-bit input terminals. A latch circuit (11) for latching at the leading end (time t1) of each pulse, and each time the latch output value (Q) of the latch circuit is inverted, A first drive mode in which the corresponding second output transistor is turned off and the corresponding first output transistor is turned on so that the output value becomes a value corresponding to the inverted latch output value; or Turning off the corresponding first output transistor and turning on the corresponding second output transistor, respectively, in the second drive mode. In after the potential of the bit-specific output terminal according to one of the drive mode is stabilized, so that the potential change of the bit-specific output terminal according to the second drive mode is started,
Alternatively, an output transistor driving means (level shift circuit) that starts changing the potential of the bit-by-bit output terminal related to the first drive mode after the potential of the bit-by-bit output terminal related to the second drive mode is stabilized. 2, delay circuit 1
3, NOT circuits 14 to 16), the output transistor driving means comprising:
In the first and second drive modes, the on-drive of the output transistor related to the drive mode in which the potential change of the output terminal for each bit is on the subsequent side is performed at the end of the pulse of the latch signal (time t2). Delay means for delaying the transmission.

According to a second aspect of the present invention, there is provided the capacitive load driving circuit according to the first aspect, wherein the delay unit receives a latch output of the latch circuit and a latch signal as inputs. Circuit 121, NO
T circuit 122).

According to a third aspect of the present invention, in the capacitive load driving circuit according to the first or second aspect,
It shall constitute at least a part of the semiconductor integrated circuit. That is, the operation of the present invention is necessary for preventing the potential change timing of the high-voltage side output OUT from being overlapped between the bits where the high-voltage side output OUT is inverted in the opposite direction from H → L and L → H. A large delay time is obtained by the enlarged pulse width of the latch signal.

[0020]

FIG. 1 is a diagram showing a detailed configuration of one bit of a capacitive load driving circuit 01 as one embodiment of the present invention, and corresponds to FIG. 4, and FIG. 2 is a diagram showing a latch signal LT of FIG. FIG. 5 is an operation timing diagram corresponding to FIG. In FIG. 1, instead of the delay circuit 12 of FIG. 4, a NAND circuit 121 which receives the output Q of the latch circuit 11 and the latch signal LT as inputs, and the NAND circuit 121
And a NOT circuit 122 for inverting the output of.

[0021] Then, as shown in FIG. 2, by the present invention to increase the T _W (the length of the L period) the pulse width of the latch signal LT than conventional inverts the high voltage side output OUT from L to H In such a case, the above-described large delay time T _PDL for delaying the ON of the PchFET 3 is obtained. Next, according to the operation timing chart 2, the data signal I in FIG.
The operation at the time of switching between H and L of N will be described.

In FIG. 1, when the latch signal LT to the latch circuit 11 falls from H to L, the latch circuit 11 latches H or L of the data signal IN, and the latch circuit 1
The output Q of 1 is H or L, respectively. The operation for the bit whose latch circuit output Q changes from H to L at time t1 as in FIG. 2A) is almost the same as that in FIG. 5A).
When the latch signal LT falls to L at time t1, PchFE
T3 is turned off with a delay of T _P1 of a certain short transmission delay time (most of the delay time of the level shift circuit 2 and the charging time of the gate capacitance of the PchFET 3).

On the other hand, the NchFET 4 has a delay time T from time t1 by a delay circuit 13 for reducing a through current.
It turns on with a delay of _NDL , and then the high-voltage-side output OUT changes from H to L after a fall time tf. In this case, the time t
2, the latch circuit output Q
Remains at L, this state is maintained. If the latch circuit output Q is a bit that remains H after time t1, the NchFET 4 remains off.
The PchFET 3 is temporarily turned off from the on state for a time corresponding to the pulse width (L period) T _W of the latch signal LT.

However, in the off state, the drive circuit 01 side viewed from the load terminal (high voltage side output OUT) is kept in a high impedance state, and the period T _W is also extremely short, about 200 ns. Therefore, the voltage change due to the discharge of the capacitive load is small, and its influence can be ignored. Next, as shown in FIG.
Is changed from L to H, the output of the NAND circuit 121 remains H irrespective of the latch circuit output Q during the period T _W during which the latch signal LT falls to L, that is, P
There is a direction in which the chFET 3 is turned off. In this case Pc
Since the hFET 3 is off before the time t1 when the latch signal LT falls to L, the off state is maintained.

On the other hand, at the time t1
When the output Q of the latch circuit changes from L to H, the input of the delay circuit 13 changes to a signal for driving the NchFET 4 off. At this timing, as in the case of FIG.
Since the delay time of the delay circuit 13 is made as small as possible, the NchFET 4 is turned off with a delay of a certain short delay time T _N1 from the time point t1.

Next, when the latch signal LT returns to H at time t2, the latch circuit output Q is also H.
The output of the ND circuit 121 switches from H to L, and PchF
ET3 is delayed from the time point t2 by a certain short propagation delay time (the delay of the level shift circuit 2 and the charge time of the gate capacitance of the PchFET 3) T _P2 , that is, the delay time T _PDL = T _W + T _P2 from the time point t1. Will be turned on at such a time.

Therefore, the ON timing of the PchFET 3 is the timing of the rise of the latch signal LT from L to H (the rear end of the latch signal pulse), that is, the latch signal L.
Optionally can be controlled with the pulse width T _W T, then a conventional high-voltage side output OUT as for the through current reduction at the time of the H from L, a delay circuit 12 to purposely delay increases the ON PchFET3 was not needed As the delay circuit, it is only necessary to use the delay circuit 13 having a relatively small delay amount for delaying the ON timing of the NchFET 4 in order to reduce the through current when the high voltage side output OUT is changed from H to L.

The latch circuit 11 holds the data signal at the falling edge of the latch signal LT (that is, the leading end of the latch signal pulse) as in the above-described embodiment, and the rising edge of the latch signal LT (that is, the rising edge of the latch signal LT). A latch circuit that holds data at the end of the latch signal pulse) can be considered. However, in the latter latch circuit, when the data signal IN changes during the period of the pulse width of the latch signal LT, the latch output Q also changes. Therefore, in a case where the data signal IN is an output from a shift register operated by a clock, and it is not desired to stop the clock signal until the end of the pulse of the latch signal LT, in particular, as in this case, the pulse width period of the latch signal LT Is longer, a circuit which holds the data signal at the leading end of the pulse of the latch signal LT like the former latch circuit is preferable.

When the pulse of the latch signal LT is set to the H level, contrary to the embodiment, a NOT circuit may be inserted between the NAND circuit 121 and the latch signal LT. If you only want to reduce the current consumption of the capacitive load drive circuit 01,
Contrary to the timing of the above embodiment, the high voltage side output OU
A method is also conceivable in which the timing of inverting T from L to H is earlier than the timing of inverting T from H to L, and this is also included in the present invention.

However, in this case, since the high voltage side output OUT overlaps with the H period, the data signal becomes H data especially at the active timing of the scan side signal as in the plasma display panel. If only one bit emits light, there is a possibility that erroneous light emission will occur at this overlapping portion. Therefore, in the above embodiment, the circuit is configured in such a manner that the timing at which the high voltage side output OUT is inverted from L to H is later than the timing at which the high voltage output OUT is inverted from H to L.

[0031]

According to the present invention, a plurality of bits of a data signal generated by a low-voltage power supply are input, and output transistors which are complementarily connected to each other are driven via a level shift circuit or the like provided for each input bit. Then, in a circuit for driving a bit-by-bit capacitive load by obtaining bit-by-bit H and L drive signals using a relatively high voltage power supply as a high voltage side output OUT, H → L and L → H A large delay time for preventing the potential change timing of the high-voltage output OUT from overlapping between the bits where the high-voltage output OUT is inverted in the opposite direction and reducing the loss of the capacitive load driving circuit is determined by the latch signal. Since it was obtained by the expanded pulse width, there is no need to add an input signal,
The large delay time can be arbitrarily controlled by simply using the pulse width of the latch signal that has been conventionally used, so that it is possible to cope with various load capacities. Can be set. Further, it is not necessary to increase the circuit scale of the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a detailed configuration diagram of one bit of a capacitive load driving circuit as one embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of a main part of FIG. 1;

FIG. 3 is a schematic configuration diagram including a load side for adjacent two bits of a capacitive load drive circuit;

FIG. 4 is a configuration diagram of a conventional circuit corresponding to FIG.

FIG. 5 is a timing chart showing the operation of the main part of FIG. 4;

[Explanation of symbols]

01 Capacitive load drive circuit 2 Level shift circuit 3 PchFET 4 NchFET 11 Latch circuit 13 Delay circuit 14-16 NOT circuit 121 NAND circuit 122 NOT circuit 1N Data signal LT Latch signal V1 Low voltage power supply V2 High voltage power supply OUT High voltage side output pulse width of GND ground T _W latch signal

Continued on the front page F term (reference) 5J055 AX04 AX27 AX48 AX54 AX66 BX16 CX12 DX12 DX56 DX72 DX83 EX07 EX21 EY21 EZ07 EZ20 EZ25 EZ50 FX12 FX17 FX35 GX01 GX04 5J056 AA05 BB19 BB38 BB57 CC05 CC14 CC21 DD

Claims (3)

[Claims] 1. A power supply terminal on a common potential side from a predetermined low-voltage power supply and a predetermined high-voltage power supply higher than the low voltage, and a non-common power supply terminal from the low-voltage power supply and the high-voltage power supply, respectively. A low-voltage power supply terminal and a high-voltage power supply terminal as potential-side power supply terminals, and a first and a second output transistor between the high-voltage power supply terminal and a common potential-side power supply terminal that can correspond to the high-voltage power supply terminal Are connected in series such that the first output transistor is on the high-voltage power supply terminal side, and the mutual connection point of the first and second output transistors of the pair is an output terminal for each bit. A plurality of pairs so as to be connected to a capacitive load; and a bit-by-bit input terminal corresponding to each of the bit-by-bit output terminals and receiving a bit signal generated by the low-voltage power supply; And a latch for inputting a latch signal having a predetermined pulse width output at step (a), and a latch provided for each of the bit-by-bit input terminals and latching a bit signal input to the bit-by-bit input terminal at a leading end of a pulse of the latch signal. And a circuit provided for each of the latch circuits, so that each time the latch output value of the latch circuit is inverted, the output value of the corresponding bitwise output terminal becomes a value corresponding to the inverted latch output value. A first drive mode in which the corresponding second output transistor is turned off and the corresponding first output transistor is turned on, or the corresponding first output transistor is turned off and the corresponding The operation in the second drive mode for turning on the second output transistor is performed. At this time, the potential of the bit-by-bit output terminal related to the first drive mode is changed. To then was boss, so that the potential change of the bit-specific output terminal according to the second drive mode is started, or,
Output transistor driving means for starting to change the potential of the bit-by-bit output terminal related to the first drive mode after the potential of the bit-by-bit output terminal related to the second drive mode is stabilized A load drive circuit, wherein the output transistor drive means starts on-drive of an output transistor related to a drive mode in which a potential change of a bit-by-bit output terminal is a subsequent side in the first and second drive modes; A capacitive load driving circuit comprising delay means for performing the operation at the end of the pulse of the latch signal. 2. The capacitive load driving circuit according to claim 1, wherein said delay means includes a logic gate circuit which receives a latch output of said latch circuit and a latch signal. Load drive circuit. 3. The capacitive load driving circuit according to claim 1, wherein said capacitive load driving circuit forms at least a part of a semiconductor integrated circuit.