JPH11136119A - Input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To pull up or pull down an input level by signals held inside an LSI without depending on external control signals and to pull-up or pull-down for each input circuit. SOLUTION: This circuit is provided with means 3 and 4 for pulling up or pulling down an input net 5 inputted to an input buffer 1 by control signals U and D, a means 2 for holding the output signals of the input buffer 1 and the means 3 and 4 for pulling up and pulling down the input net by the output signals of the holding means 2 instead of the control signals U and D.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a semiconductor integrated circuit (hereinafter abbreviated as LSI), and more particularly to an input circuit having a function of pulling up or pulling down an external terminal.

[0002]

2. Description of the Related Art Conventionally, in an input circuit of an LSI, for example, as shown in Japanese Patent Application Laid-Open No. 6-53810,
When the signal level of the input terminal is pulled up by operating a pull-up resistor or pulled down by operating a pull-down resistor, a method of switching using a dedicated control signal from outside the LSI has been used. FIG. 6 is a circuit diagram showing an input circuit of the publication. The input signal 33 of the semiconductor integrated circuit 31 is pulled up by a pull-up resistor 41 or pulled down by a pull-down resistor 42. At this time, selection control between pull-up and pull-down is performed by a control signal 35 from outside the LSI.

[0003]

A first problem is that, in the prior art, external terminals of the LSI cannot be used effectively. The reason is that an LSI external terminal for inputting a control signal is required to select pull-up or pull-down.

[0004] The second problem is that in the conventional technology, it is not possible to freely select whether to pull up or pull down for each input circuit. The reason is LS
I pull-up or pull-down is selected by a control signal from outside,
If each input circuit has an individual control signal terminal, a large number of control signal terminals are required. Therefore, since control signals are distributed from one or a few control signal terminals to each input circuit in the LSI, input circuits to which the same control signal is distributed have the same pull-up or pull-down. This is because it is set.

[0005] An object of the present invention is to pull up or pull down an input level with a signal held inside an LSI without using an external control signal, so that an LSI input terminal is not used for an external control signal. , An input circuit that enables pull-up or pull-down control for each input circuit.

[0006]

An input circuit according to the present invention comprises:
In an input circuit having means for pulling up or pulling down an input net inputted to an input buffer by a control signal, means for holding an output signal of the input buffer, and pulling up the input net by an output signal of the holding means Or means for pull-down.

Further, the holding means holds the output signal of the input buffer by a clock signal and activates or deactivates the pull-up means, and activates or deactivates the pull-down means. And a second signal to be generated.

Further, the first signal and the second signal are signals corresponding to a high level state and a low level state of one signal.

Further, the holding means has a reset signal for generating first and second signals for disabling both the pull-up means and the pull-down means.

Further, the pull-up means and the pull-down means have a high conduction resistance which inverts a potential level of an input net maintained by pull-up or pull-down by a potential level of an external input.

Since the pull-up or pull-down is controlled by the register holding the output data of the input buffer, it is not necessary to supply a control signal from the outside to the LSI. Therefore, a terminal for a control signal is not required, and LS
The external terminal of I can be used effectively. Compared to the conduction resistance of the transistor that constitutes the output buffer of the LSI,
By making the pull-up resistance and the pull-down resistance sufficiently high, the pull-up or pull-down state can be changed according to the signal level given to the input circuit from outside the LSI. That is, it is possible to switch from pull-down to pull-up by giving a high level from the outside of the LSI to the pulled-down input circuit and applying a clock. Conversely, a pull-up input circuit can be switched from pull-up to pull-down by giving a low level from outside the LSI and applying a clock.

By using the bus connection section as a receiver circuit, it is possible to prevent the bus from entering a high impedance state. Therefore, a through current generated in the input buffer due to the bus having the intermediate potential is prevented, and power consumption can be reduced.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 1, in the preferred embodiment of the present invention, an input buffer 1 of an LSI is provided.
Are connected to a pull-up means 3 and a pull-down means 4. These pull-up means 3 and pull-down means 4 can be realized using, for example, transistors. The output signal of the input buffer 1 is LS
It is transmitted to the inside of I and input to the holding means 2 and held. The holding means 2 can be realized by using, for example, a flip-flop or the like.
The holding operation can be performed by applying the clock signal of The signal held by the holding means 2 is
The control signal is input to the pull-up means 3 and the pull-down means 4.

Next, the operation of this embodiment will be described. The pull-up means 3 normally separates the input net 5 of the input buffer 1 from the first power supply potential 6, but when the control signal U is applied, the input net 5 and the first power supply potential 6 are made conductive. , The potential of the input net 5 is raised. The pull-down means 4 normally disconnects the input net 5 of the input buffer 1 from the second power supply potential 7, but when the control signal D is supplied, the input net 5 and the second power supply potential 7
Is made conductive to lower the potential of the input net 5. what if,
If a high level is set in the holding means 2,
The control signal U is applied to the pull-up means 3, and the input net 5 and the first power supply potential 6 are conducted. At this time, since the pull-down means 4 separates the input net 5 from the second power supply potential 7, the potential of the input net 5 is raised to the first power supply potential 6, and is brought into a pull-up state. Since the input of the input buffer 1 is pulled up to the high level, the input buffer 1 outputs the high level, and the high level is set in the holding means 2 again. Therefore, when the high level is set in the negative holding means 2, the input circuit according to this embodiment is in the same state as the input terminal clamped to the high level. Assuming that the low level is set in the holding unit 2, the control signal D is applied to the pull-down unit 4, and the input net 5 and the second power supply potential 7 are conducted. At this time, since the pull-up means 3 separates the input net 5 from the first power supply potential 6, the potential of the input net 5 is lowered to the second power supply potential 7, and the pull-down state is established. The input buffer 1 outputs the low level since the input is pulled down to the low level, and the low level is set in the holding means 2 again. Therefore, once the low level is set in the holding means 2, the input circuit according to this embodiment is in the same state as when the input terminal is clamped at the low level.

The pull-up means 3 connects the input net 5 and the first power supply potential 6 with high resistance when conducting. The pull-down means 4 also connects the input net 5 and the second power supply potential 7 with a high resistance when conducting. Thus, when a signal level different from the current clamp state is given to the input net 5 from outside the LSI, the logical value of the input net 5 can be inverted. When the logical value of the input net 5 is inverted, the input buffer 1
Is inverted, and as a result, the value held by the holding means 2 is also inverted. Therefore, the relationship between the operation and non-operation of the pull-up means 3 and the pull-down means 4 is switched between them, and the switching is performed so that the same logic value as the signal level given from outside the LSI is continuously clamped by the input circuit. In this manner, by forcibly applying a signal level from outside the LSI, it is possible to freely rewrite the clamp state, whether pull-up or pull-down.

Next, a first embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 2, the transistor 13 of the pull-up means 3 has a drain terminal and a source terminal connected to the input net 5 and the power supply potential VDD, respectively. When a low-level signal is applied to the gate terminal of the transistor 13, the transistor 13 conducts between the drain and the source. The transistor 14 of the pull-down means 4 has a drain terminal and a source terminal connected to the input net 5 and the power supply potential GND, respectively.
And connected to. When a high-level signal is applied to the gate terminal of the transistor 14, the transistor 14 conducts between the drain and the source. The register 12 captures and holds the output signal of the input buffer 1 using the clock signal 8 as a trigger signal. The output of the register 12 of the holding means 2 is connected to each gate terminal of the transistors 13 and 14.

Assuming that the high level is set in the register 12, the transistor 13 is turned off, disconnecting the input net 5 from VDD. At this time, since the transistor 14 is turned on, the input net 5 and the GND are made conductive. As a result, the input net 5 is pulled to the GND potential and becomes low level. Since the input net 5 is at a low level, the output of the input buffer 1 forming the inverter circuit is at a high level, which is transmitted to the inside of the LSI and also transmitted to the input of the register 12. Therefore, no matter how many times the clock signal 8 is applied in this state, the high level is always set in the register 12, so that the input net is always clamped to the low level.

If the low level is set in the register 12, the transistor 14 is turned off, disconnecting the input net 5 from GND. At this time, since the transistor 13 is turned on, the input net 5 and the VDD are made conductive. As a result, the input net 5 is pulled to the VDD potential and becomes a high level. Since the input net 5 has become high level, the output of the input buffer 1 becomes low level, which is transmitted to the inside of the LSI and also transmitted to the input of the register 12. Therefore, no matter how many times the clock signal 8 is applied in this state, the register 12 is always low.
Since the level is set, the input net is always clamped to a high level.

Next, the operation of the first embodiment for forcibly changing from the pull-up state to the pull-down state or from the pull-down state to the pull-up state will be described with reference to FIG. According to FIG. 3, a signal is supplied to the input circuit 20 according to the first embodiment from a driver circuit 21 which is another LSI output. The driver circuit 21 includes transistors 17 and 18. The on-resistance of the transistors 13 and 14 of the input circuit 20 is determined by the transistors 17 and 18 of the driver circuit 21.
The transistor is designed so as to have a value sufficiently larger than the on-resistance of the transistor. It is assumed that a high level is set in the register 12, and the input net 5 is clamped to a low level and is in a pull-down state. To change the input net 5 to the pull-up state, the driver circuit 21
Gives a high level signal to the input net 5. At this time, in the four transistors connected to the drain terminal connected to the input net 5, 14 and 17 are turned on,
13 and 18 are turned off. Therefore, input net 5
Is a value obtained by dividing the potential difference between GND and VDD by the ON conduction resistance “R1” of the transistor 14 and the ON conduction resistance “R2” of the transistor 17. That is, the potential Vs of the input net 5 is represented by the following formula.

Vs = (VDD−GND) × R1 ÷ (R1 + R2) Since the on-state conduction resistance “R1” of the transistor 14 is sufficiently higher than the on-state conduction resistance “R2” of the transistor 17, the input net 5 The potential becomes a value close to a high level. For example, “R1” is 5 kilohms, “R2” is 5
Assuming that 0 ohms, VDD is 5V, and GND is 0V, the potential Vs of the input net 5 is calculated from the above formula by using the formula 4.
95V, which is almost the same as the high level of 5V. As a result, the output of the input buffer 1 becomes low level, and the signal is transmitted to the inside of the LSI and the register 1
A low level is also given to the input terminal of the second, at this time,
When the clock signal 8 is applied, the value of the register 12 becomes low.
Rewritten to level. When the output of the register 12 goes low, the transistor 13 switches to the on state and the transistor 14 switches to the off state, and the potential of the input net 5 rises to 5 V and stabilizes. Therefore, it is possible to easily switch from the pull-down state to the pull-up state by supplying a high-level signal from another driver circuit 21 to the input circuit 20 as described above. Similarly, when switching from the pull-up state to the pull-down state, the low level is set in the register 12 and the input net 5 is clamped at the high level. Give a bell signal. At this time, the transistors 13 and 18 are turned on, and the transistors 14 and 17 are turned off. The on-resistance “R3” of the transistor 13 is
, The potential of the input net 5 becomes a value close to a low level. Therefore, the output of the input buffer 1 constituting the inverter circuit becomes high level, and the signal is transmitted to the inside of the LSI.
The input terminal of the register 12 is also given a high level.
At this time, when the clock signal 8 is applied, the register 12
Is rewritten to a high level. The high level of the output of the register 12 causes the transistor 14
Is turned on, the transistor 13 is turned off, and the potential of the input net 5 is lowered to the GND potential and stabilized. Therefore, by providing a low level signal from the other driver circuit 21 to the input circuit 20 as described above,
It is possible to easily switch from the pull-up state to the pull-down state.

Referring to FIG. 4 of the second embodiment, in FIG. 2, the control signal U for turning on / off the pull-up and the control signal D for turning on / off the pull-down are separately distributed from the register 12. Regarding the control of the pull-up means and the control of the pull-down means, when the negative side is turned on when the high level is set and the other side is turned on when the low level is set, As shown in FIG.
And the control signal D can be one signal. In this case, the same operation as that of FIG. 2 can be realized by one control wiring, which is advantageous in wiring of the LSI as compared with FIG.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention. In FIG. 5, a register having a reset function is used as the register 22, and the reset signal 9 is input to the register 22. When the reset signal 9 is input, at the output of the register 22, the control signal U goes high and the control signal D goes low. Therefore, both the transistor 13 and the transistor 14 are turned off. Therefore, the input net 5 can be in a state where neither pull-up nor pull-down is performed. Thus, when measuring the DC characteristics of the transistor constituting the input buffer 1, the influence of the current flowing through the pull-up means or the pull-down means can be suppressed, and more accurate measurement can be performed.

Although the embodiments shown in FIGS. 2, 4 and 5 are described as a single input circuit, a bus is constructed using an output circuit with a tri-state function and an input circuit according to the present invention. It is also possible to form a bidirectional circuit for performing the operation. By using this input circuit, the bus potential does not go into a floating state, and a through current generated in the input buffer 1 when the bus potential becomes the intermediate potential can be prevented to realize power saving.

[0024]

The first effect is that the external terminals of the LSI can be used effectively. The reason is that a terminal for externally inputting a special control signal to the LSI is not required to control whether the input net of the input circuit is pulled up or pulled down.
In particular, in the case where pull-up or pull-down is individually set for each input terminal, the input circuit according to the present invention can be freely set without a control signal terminal. Can be used more effectively.

The second effect is that the state can be easily changed by giving a signal level from the outside of the LSI to the input circuit pulled up or pulled down. The reason is that the conduction resistance of the pull-up means and the conduction resistance of the pull-down means of the input circuit according to the present invention are made sufficiently higher than the ON conduction resistance of the driver circuit for driving the input circuit. That's why. Since the signal drive capability of the driver circuit is higher, the setting state can be forcibly changed from pull-up to pull-down or from pull-down to pull-up.

A third effect is that power consumption can be reduced by using the input circuit of the present invention as a bus receiver circuit. The reason is that the bus is kept at a high level or a low level by the input circuit of the present invention even when all the driver circuits connected to the bus are in a high impedance state. Therefore, when the bus has the intermediate potential, a through current generated in each input buffer is prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing the operation of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment.

FIG. 5 is a circuit diagram showing a third embodiment.

FIG. 6 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input buffer 2 holding means 3 pull-up means 4 pull-down means 5 input net 6 first power supply potential 7 second power supply potential

Claims (5)

[Claims] 1. An input net to be input to an input buffer,
An input circuit having means for pulling up or pulling down by a control signal, comprising: means for holding an output signal of the input buffer; and means for pulling up or pulling down the input net according to an output signal of the holding means. An input circuit characterized by the above. 2. The method according to claim 1, wherein the holding unit holds an output signal of the input buffer in response to a clock signal, and activates or deactivates the pull-up unit. 2. The input circuit according to claim 1, further comprising: 3. The holding means according to claim 2, wherein the first signal and the second signal are signals corresponding to a high level state and a low level state of one signal. 4. The holding means according to claim 2, wherein said holding means has a reset signal for generating first and second signals for disabling both said pull-up means and said pull-down means. . 5. The apparatus according to claim 1, wherein said pull-up means and said pull-down means have a high conduction resistance that inverts a potential level of an input net maintained by pull-up or pull-down with a potential level of an external input. Item 2. The input circuit according to Item 1.