JPH06205338A - Liquid crystal display controller driver - Google Patents

Abstract

PURPOSE:To execute the test of a liquid crystal display device at a high speed by using a test driver driving the liquid crystal display device at a higher speed than the speed of a liquid crystal display driver. CONSTITUTION:When a signal TEST is received, an output control circuit 10 controls a test driver 14 based on 1st and 2nd outputs. With segment data set to an H level under this control, a transistor (TR) 19 is turned off and a TR 18 is turned on, a voltage VDD is outputted to an external lead 8 and segments of the liquid crystal display device are lighted. With the segment data set to an L level, the TR 18 is turned off and the TR 19 is turned on, a voltage VSS is outputted to the external lead 8 and segments of the liquid crystal display device are extinguished. A 3rd output of the circuit 10 stops the operation of a segment control voltage conversion circuit 3. A liquid crystal display data memory 1 and a liquid crystal display bias control circuit 9 are driven by a high speed clock, segment data are sequentially read and the test of the liquid crystal display device is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display controller driver having a circuit for testing a liquid crystal display device or a liquid crystal display driver.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional liquid crystal display controller.
FIG. 3 is a block diagram of a main part of a driver, showing one segment driver for driving one segment of a liquid crystal display device and a liquid crystal display controller. The segment data of the liquid crystal display data memory 1 is input to the segment control voltage conversion circuit 3 via the data line 2, converted into a voltage capable of controlling the segment driver 5, and input to the segment driver 5 via the control line 4. It

The segment driver 5 comprises a P-channel transistor 6 and an N-channel transistor 7. The gates of both transistors 6 and 7 are connected and connected to the control line 4 as an input terminal. The drains of both transistors 6 and 7 are connected to each other, and are connected as output terminals to a segment of a liquid crystal display device (not shown) through an external lead 8.
The sources of both transistors 6 and 7 are supplied with operating voltage from the liquid crystal display bias control circuit 9.

The liquid crystal display bias control circuit 9 has four types of liquid crystal display voltages V _L3 , V _L2 , V _L1 , V _SS (V _L3 >) from the outside.
V _L2 > V _L1 > V _SS ) is supplied, and from these four types of voltage, 2
Select seed voltage. This voltage selection is based on the voltage V
_L3 (V _SS ) and voltage V _L2 (V _L1 ) are alternately selected based on the timing of a clock signal (not shown). The selected voltage V _L3 (V _L2 ) is supplied to the source of the transistor 6 as the voltage V _SH , and the selected voltage V _L3 (V _L2 ) is supplied.
_SS (V _L1 ) is supplied to the source of the transistor 7 as the voltage V _SL . The voltage V _L3 (V _SS ) is applied to the transistor 6 (7).
When the voltage is supplied is called the display mode, the voltage V
_The case where _L2 (V _L1 ) is supplied is called a non-display mode. The display mode and the non-display mode are configured to be repeated alternately based on the clock signal.

Next, the operation will be described. The segment control voltage conversion circuit 3 outputs a voltage for controlling the segment driver 5 in accordance with the segment data of the liquid crystal non-data memory 1, and one of the transistors 6 and 7 is turned on by the control voltage and the other is turned off. Become. When the segment data is (1) H ", the transistor 6 is turned on. In this case, in the display mode, the voltage V _L3 is output and the segment of the liquid crystal display device is turned on.
In the non-display mode, the voltage V _L2 is output and the segment of the liquid crystal display device is turned off. Segment data is ■ L "
In the case of, the transistor 7 is turned on. In this case, the voltage V _SS is output in the display mode and the voltage V _L1 is output in the non-display mode, and the segment of the liquid crystal display device is turned off at any time.

The segment data of the liquid crystal display data memory 1 is sequentially read by a clock signal (not shown) to drive the segment driver, and a screen corresponding to the segment data is displayed on the liquid crystal display device. Even when the segments of the liquid crystal display appear to be lit continuously, the display mode and non-display mode are repeated alternately,
The segment repeats lighting and extinguishing.

[0007]

In the conventional liquid crystal display controller / driver, the driving capability of the segment driver is set extremely low in order to suppress the current flowing through the segment driver that drives the liquid crystal display device. Therefore, since a propagation delay occurs, a relatively low speed clock signal is used. The liquid crystal display controller / driver may be used to test the liquid crystal display device, but in this case, it is necessary to use the low-speed clock signal, and thus the test requires a long time.

Further, when a segment driver built in the liquid crystal display controller driver is tested, a specific voltage required for the test is applied to the two transistors constituting the segment driver for a period required for the test. Must be sourced. Therefore, the function of the liquid crystal display bias control circuit is controlled to generate a required voltage for a required period. Therefore, the test time of the liquid crystal display driver requires more time to control the function of the liquid crystal display bias control circuit, and thus the total test time becomes long.

As described above, the conventional liquid crystal display controller
The long time required to test the liquid crystal display device or the liquid crystal display driver using the driver causes an increase in the production cost of the liquid crystal display device or the liquid crystal display controller / driver. For this reason, there is currently a demand for the development of a technique for realizing these tests at high speed. The present invention has been made to solve such a problem, and a liquid crystal display that realizes a test at high speed by using a test driver that operates at a high speed or a liquid crystal display controller driver that generates an arbitrary test voltage. The purpose is to provide a display controller driver.

[0010]

A liquid crystal display controller / driver according to a first aspect of the present invention comprises a test driver for driving a liquid crystal display device at a higher speed than the liquid crystal display driver, and an output control circuit for controlling the test driver. The output of the driver and the output of the liquid crystal display driver are output from the same output path. The liquid crystal display controller driver of the second invention of the present application is characterized by further comprising means for driving the test driver and the liquid crystal display driver in parallel when testing the liquid crystal display device.

A liquid crystal display controller according to the third invention of the present application
The driver, when testing the liquid crystal display driver, is a clock control signal for alternately producing a test control signal for selecting a voltage to be tested from a plurality of voltages and a display mode voltage and a non-display mode voltage. And switching means for switching between test data and segment data for determining which of the two transistors forming the liquid crystal display driver is to be tested.

[0012]

In the first aspect of the invention, when testing a liquid crystal display device,
The output control circuit operates the test driver and stops the operation of the liquid crystal display driver. Since the test driver drives the liquid crystal display device at high speed according to the liquid crystal display data, the output propagation delay is small and the test can be executed at high speed even when the capacitance associated with the input part of the liquid crystal display device is large. In the second invention, when the liquid crystal display device is tested, the output control circuit drives both the test driver and the liquid crystal display driver. Therefore, the test of the liquid crystal display device can be performed with a larger output than when the test driver alone tests.

In the third invention, when testing the built-in liquid crystal display driver, the test mode and test time can be arbitrarily selected by the test control signal, and the transistor to be tested can be arbitrarily selected by the test data. Therefore, the voltage required for the test can be arbitrarily selected.

[0014]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 1 is a block diagram of a main part of a first embodiment of a liquid crystal display controller / driver according to the first invention of the present application, which is a liquid crystal display driver 5 for driving one segment of a liquid crystal display device and a liquid crystal display as a test object. A test driver 14 and a liquid crystal display controller for driving one segment of the device at high speed are shown.

This liquid crystal display controller driver is
When driving a normal liquid crystal display device, the operation proceeds based on a low-speed clock signal from a clock source (not shown), and when testing the liquid crystal display device, the operation proceeds based on a high-speed clock signal. When the test signal TEST for executing the test operation is input, the output control circuit 10 controls by the first and second outputs according to the segment data input from the liquid crystal display data memory 1 through the data line 2. The test driver 14 is controlled at high speed via the lines 12 and 13, and the operation of the segment control voltage conversion circuit 3 is stopped via the control line 15 by the third output.

When driving a normal liquid crystal display device, the test signal TEST is not input, and the segment control voltage conversion circuit 3 operates in accordance with the segment data input from the liquid crystal display data memory 1 via the data line 2. The display driver 5 is controlled at a low speed. The first output and the second output are respectively input to the gates of the transistor 6 and the transistor 7 of the liquid crystal display driver 5 via the control line 16 and the control line 17, respectively.

The liquid crystal driver 5 comprises a P-channel transistor 6 and an N-channel transistor 7. The drains of both transistors 6 and 7 are connected to each other and the liquid crystal display driver 5 is connected.
Is connected to the output of the test driver 14 and the external lead 8. The sources of the transistors 6 and 7 are connected to the liquid crystal display bias control circuit 9, respectively.

The liquid crystal display bias control circuit 9 is provided with four types of liquid crystal display voltages V _L3 , V _L2 , V _L1 , V _SS (V _L3 > from the outside).
V _L2 > V _L1 > V _SS ) is supplied, and two types of voltages V _SH (V _L3 or V _L2 ) and V _SL (V _L1 or V _SS ) are output from the four types. The liquid crystal display bias control circuit 9 has two modes: a display mode for displaying the liquid crystal display device and a non-display mode for not displaying. In the display mode, the voltage V _L3 is supplied as the voltage V _SH and the voltage V _SL is supplied as the voltage V _L3.
SS is supplied. For non-display mode, the voltage V _L2 is supplied as a voltage V _SH, a voltage V _L1 is supplied as a voltage V _SL. The display mode and the non-display mode are alternately repeated according to the clock signal. The voltage V _SH is supplied to the source of the transistor 6, and the voltage V _SL is supplied to the source of the transistor 7.

Either of the voltages V _SH and V _SL is output to the external lead 8 by the switching of both the transistors 6 and 7 and is supplied to the segment of the liquid crystal display device. The test driver 14 is a driver that drives the liquid crystal display device at a higher speed than the liquid crystal display driver, and is composed of a P-channel transistor 18 and an N-channel transistor 19 whose driving capability is several times or more that of the liquid crystal display driver. The drains of both transistors 18 and 19 are connected and connected to the external lead 8 as the output of the test driver 14, and the sources of both transistors 18 and 19 are directly connected to the operating power supply (voltage V _DD and voltage V _SS ) of the entire circuit. Has been done.

Next, the operation will be described. This liquid crystal display controller driver has a test mode in which the test driver is controlled by the segment data read with a high-speed clock to test the liquid crystal display device as a test target, and a low-speed clock to drive a normal liquid crystal display device. The signal TEST has two modes, a segment output mode in which the liquid crystal display driver is controlled by the segment data read in step 1) and a test mode is executed.

(Operation in the segment output mode) Since the signal TEST is not input, the segment control voltage conversion circuit 3 uses the first and second outputs of the segment control voltage conversion circuit 3 in accordance with the segment data to transmit the liquid crystal display driver through both control lines 16 and 17. Control 5 By this control, when the segment data is H, the transistor 7 is turned off and the transistor 6 is turned on, and the voltage V _SH is output to the external lead 8.
The voltage V _L3 and the voltage V _L2 appear alternately in the voltage V _SH , and the segments of the liquid crystal display device are repeatedly turned on and off.
Transistor 6 when segment data is L
Is turned off, the transistor 7 is turned on, and the voltage V
_SL is output to the external lead 8. Voltage V _L1 in the voltage V _SL
And the voltage V _SS alternately appear, and in each of them, the segment of the liquid crystal display device is turned off. The liquid crystal display data memory 1 and the liquid crystal display bias control circuit 9 are driven by a low-speed clock, the segment data are sequentially read from the liquid crystal display data memory 1, and the liquid crystal display device displays a screen according to the read data.

(Operation in Test Mode) When the signal TEST is input, the output control circuit 10 controls the test driver 14 by the first and second outputs. By this control, when the segment data is (1) H ", the transistor 19 is turned off and the transistor 18 is turned on, the voltage V _DD is output to the external lead 8, and the segment of the liquid crystal display device is turned on. If L ", transistor
When the transistor 18 is off, the transistor 19 is turned on, the voltage V _SS is output to the external lead 8, and the segment of the liquid crystal display device is turned off.

The third output of the output control circuit 10 stops the operation of the segment control voltage conversion circuit 3. The liquid crystal display data memory 1 and the liquid crystal display bias control circuit 9 are driven by a high-speed clock to sequentially read out segment data,
A liquid crystal display device test is performed. Also, when the LCD display is different from the normal display during the test,
It is necessary to monitor the content of the segment data of the liquid crystal display controller / driver before judging the quality of the liquid crystal display device. However, although the liquid crystal display driver has the ability to drive the segments of the liquid crystal display device, it does not have the ability to drive the test device for checking the output voltage of the segment data for monitoring. In such a case, the test driver can monitor the contents of the segment data.

FIG. 2 is a block diagram of a main part of a second embodiment according to the first invention of the present application, which is a segment 1 of the liquid crystal display device.
The figure shows a liquid crystal display driver 5 for driving each one, a test driver 14 for driving one segment of a liquid crystal display device as a test object at high speed, and a liquid crystal display controller. The liquid crystal display controller driver shown in the present embodiment is used for not only the test mode and the segment output mode but also the general-purpose mode for inputting / outputting various data, so as to capture external data, output the captured data, and external lead 8. It is configured to perform three operations of receiving data from the connected external device.

General-purpose output data input from the outside is input to the general-purpose output data holding circuit 20 via the data line 21, and the write signal WR on the signal line 22 is used to latch the input data. It is given to the holding circuit 20.
The general-purpose output data holding circuit 20 takes in and holds general-purpose output data on the data line 21 at the timing of the signal WR. The held data is output to the output control circuit 10 via the data line 23. Then, the signal PORT for executing the general-purpose mode is input to the output control circuit 10 via the signal line 24.

When the signal PORT is input, the output control circuit 10
Is not the segment data of the liquid crystal display data memory 1, but the general-purpose output data input from the general-purpose output data holding circuit via the data line 23, and the first and second outputs are selected according to the selected data. The test driver is controlled at high speed, and the segment control voltage conversion circuit 3 is controlled by the third output.
The operation of is stopped. To receive data from an external device connected to the external lead 8,
The external lead 8 is connected to a circuit (not shown) via the general-purpose input circuit 25 and the data line 21. When the read signal RD is given to the general-purpose input circuit 25 through the signal line 26, the data from the external device is read. Other configurations are the same as those in FIG. 2, and thus description thereof will be omitted.

Next, the operation will be described. (Operation in General Mode) External data is held in the general-purpose output data holding circuit 20 by inputting the signal WR. When the signal PORT is input, the output control circuit 10 controls the test driver 14 by the first and second outputs. By this control, when the general-purpose output data is 1H ", the transistor 19 is off and the transistor 18 is on so that the voltage V _DD is output to the external lead 8. When the general-purpose output data is 1L". Causes the transistor 18 to be off and the transistor 19 to be on so that the voltage V _SS is output to the external lead 8. Further, the output control circuit 10 stops the operation of the segment control voltage conversion circuit 3 by the third output.

The general-purpose output data holding circuit 20 is driven by a high-speed clock, the data of the general-purpose output data holding circuit 20 is sequentially read, and is output to an external device connected via the external lead 8 for various general-purpose data. Can be used for purposes. The data transmitted from the external opposing device is read from the external lead 8 via the general-purpose input circuit 25 and the data line 21 by inputting the signal RD.

FIG. 3 is a block diagram of the essential parts of a first embodiment of a liquid crystal display controller / driver according to the second invention of the present application, showing one liquid crystal display driver 5 and one test driver 14 and a liquid crystal display controller. Therefore, the liquid crystal display driver 5 and the test driver 14 are configured to be driven in parallel in the test mode. The liquid crystal display driver 5 is supplied with the voltages V _DD and V _{SS, and} is provided with power source changeover switches 27 and 28 so that it can be switched between the voltages V _SH and V _SL . That is, the voltage V _SH (V _SL ) is applied to one terminal of the power source changeover switch 27 (28) and the voltage V _DD (V _SL ) is applied to the other terminal.
_SS ), and the common terminal is transistor 6
It is connected to the source of (7). Further, when the signal TEST is given to the power source changeover switch 27 (28) through the signal line 11, the voltage V _DD (V
_It is a normal state when _SS ) is supplied and the signal TEST is not supplied, and the voltage V _SH (V _SL ) is supplied. Both power source changeover switches 27, 28 are composed of transistors.

The output control circuit 10 controls the test driver 14 according to the segment data from the liquid crystal display data memory 1, and does not participate in the operation of the segment control voltage conversion circuit 3. The segment control voltage conversion circuit 3 is an output control circuit 10
Regardless of the above, the segment data from the liquid crystal display data memory 1 is converted to a voltage for controlling the liquid crystal display driver 5, and is output to the gates of both transistors 6 and 7 of the liquid crystal display driver 5 via the control line 4. There is. Other configurations are the same as those in FIG. 2, and thus description thereof will be omitted.

Next, the operation will be described. (Operation in test mode) When the signal TEST is input, the power supply changeover switch 27 (28) switches so that the source voltage of the transistor 6 (7) becomes the voltage V _DD (V _SS ). Then, the output control circuit 10 controls the test driver 14 and the segment control voltage conversion circuit 3 controls the liquid crystal display driver according to the segment data. By this control, the voltage V _DD is output to the external lead 8 when the segment data is (1) H ", and the voltage V _SS is output when the segment data is (1) L". In this way, the test of the liquid crystal display device is executed with a larger output than the test driver 14 alone.

(Operation in segment output mode) Since the signal TEST is not input, the power source changeover switch 27 (28) continues to be in the normal state, and the voltage V _SH (V _SL ) is supplied to the source of the transistor 6 (7). It And output control circuit
The segment control voltage conversion circuit 3 controls the liquid crystal display driver 5 according to the segment data. By this control, the voltage V _SH is output to the external lead 8 when the segment data is (H) and the voltage V _SL is output when the segment data is (L), thereby driving the segment of the liquid crystal display device. In this way, a screen corresponding to the segment data is displayed on the liquid crystal display device.

FIG. 4 is a block diagram of the essential parts of a second embodiment according to the second aspect of the present invention, showing a liquid crystal display driver 5, a test driver 14 and a liquid crystal display controller. The liquid crystal display controller driver according to the present embodiment is configured such that the liquid crystal display driver 5 and the test driver 14 are driven in parallel in the test mode, and also in the general mode.

General-purpose output data input from the outside is
The write signal WR, which is input to the general-purpose output data holding circuit 20 via the data line 21 and latches the input data, is applied to the general-purpose output data holding circuit 20. The general-purpose output data holding circuit 20 takes in and holds general-purpose output data on the data line 21 at the timing of the signal WR. The held data is output to the output control circuit 10 via the data line 23.

The signal PORT for executing the general mode is
When input to the output control circuit 10 via the signal line 24, the output control circuit 10 selects not general data but general-purpose output data and fetches it, and the test driver outputs the first and second outputs according to the selected data. 14 is controlled at high speed, and the data is transmitted to the segment control voltage conversion circuit 3 via the data line 35. The segment control voltage conversion circuit 3 takes in not the segment data but general-purpose output data on the data line 35, and drives the liquid crystal display driver 5 at high speed according to the data. The signal PORT is given to the power source changeover switch control circuit 29 via the signal line 24 and the signal TEST is given to the power source changeover switch control circuit 29 via the signal line 11, and further controls both power source changeover switches 27, 28 via the control line 30. Yes.

In the general-purpose mode, it is possible to receive data from an external device connected to the external lead 8. The external lead 8 is connected to a circuit (not shown) via the general-purpose input circuit 25 and the data line 21. However, when the read signal RD is given to the general-purpose input circuit 25 through the signal line 26, the data from the external device is read. The other configuration is similar to that of FIG. 4, and thus the description is omitted.

Next, the operation will be described. (Operation in segment output mode) Since neither signal TEST nor signal PORT is input, the power switch
27 and 28 continue the normal state, and transistor 6
The voltage V _SH (V _SL ) is supplied to the source of (7). The liquid crystal display bias control circuit 9 is driven by a low speed clock, and the voltage V _L3 (V _SS ) and the voltage V _L2 (V _L1 ) are alternately selected and supplied to the liquid crystal display driver 5 as the voltage V _SH (V _SL ). To be done. Then, the segment data of the liquid crystal display data memory 1 is read at a low speed clock, drives the liquid crystal display driver 5 via the segment control voltage conversion circuit 3, and the voltage V _SH (V _SL ) according to the segment data is externally supplied. It is output to the segment of the liquid crystal display device through the lead 8. In this way, the screen is displayed on the liquid crystal display device according to the segment data.

(Operation in test mode) When the signal TEST is input, the voltage changeover switches 27 and 28 are switched, and the voltage V _DD (V _SS ) changes to the liquid crystal display driver 5 and the test driver.
Supplied to 14. Then, the segment data of the liquid crystal display data memory 1 is read at a high speed clock, drives the test driver 14 via the output control circuit 10, and drives the liquid crystal display driver 5 via the segment control voltage conversion circuit 3. The test driver 14 and the liquid crystal display driver 5 driven in parallel by the segment data output the voltage V _DD (V _SS ) according to the segment data to the liquid crystal display device to be tested through the external lead 8. In this way, the liquid crystal non-device test is executed with a larger output than the test driver 14 alone.

(Operation in general mode) When the signal PORT is input, the power source changeover switches 27, 28 are switched and the voltage V _DD (V _SS ) is supplied to the liquid crystal display driver 5. Then, the general-purpose output data of the general-purpose output data holding circuit 20 is read at a high-speed clock, and the test driver 14 and the liquid crystal display driver 5 are driven in parallel via the output control circuit 10 and the segment control voltage conversion circuit 3, and The voltage V _SH (V _SL ) corresponding to the output data is output to the external device through the external lead 8. In this way, an output larger than that output by the test driver 14 alone is provided for various general-purpose applications.

FIG. 5 is a block diagram of an essential part of a liquid crystal display controller / driver according to the third invention of the present application, showing one liquid crystal display driver 5 and one liquid crystal display controller. This LCD display controller driver operates in the segment output mode to drive a normal LCD device, and the operation progresses based on the low-speed clock CLK. The operation proceeds based on the test control signal and the test data input from the.

The segment data of the liquid crystal display data memory 1 is read by the low speed clock CLK and input to the input selection switching circuit 32 via the data line 2. The test data is data for selecting a voltage required for the test from the voltage V _SH and the voltage V _SL, and is also input to the input selection switching circuit 32 via the data line 33. The signal TEST is given to the input selection switching circuit 32 both through the signal line 11 and the inverted signal TEST bar of the signal TEST through the signal line 34. The input selection switching circuit 32 selects the segment data by the signal TEST bar and the test data by the signal TEST,
The selected data is output to the segment control voltage conversion circuit 3. The segment control voltage conversion circuit 3 converts the input segment data or test data into a voltage that can control the liquid crystal display driver 5 and outputs the voltage to the liquid crystal display driver 5 via the control line 4.

The liquid crystal display driver 5 comprises a P channel transistor 6 and an N channel transistor 7. The gates of both transistors 6 and 7 are connected and connected to the signal line 4 as input ends, and the drains of both transistors 6 and 7 are connected and connected to the external lead 8 as output ends. The external lead 8 is connected to the liquid crystal display device in the segment output mode, and connected to a tester (hereinafter referred to as a tester) for testing the semiconductor integrated circuit in the test mode. The sources of the transistors 6 and 7 are supplied with the voltages V _SH and V _SL generated by the liquid crystal display bias control circuit 9, respectively.

The test control signal TEST CONT is
L "is not a signal that alternates with each other, but" H "is a signal that continues for a certain period, and then" L "is a signal that continues for a certain period. The duration is determined in advance, but the progress of the test The signal TEST CONT and the low-speed clock CLK are input to the control signal switching circuit 36, and the signal TEST is also supplied to the control signal switching circuit 36. Switching circuit
36 selects the signal TEST CONT when the signal TEST is applied, selects the low speed clock CLK when the signal TEST is not applied, and outputs the selected signal to the liquid crystal display bias control circuit 9. LCD bias control circuit 9 is a voltage V _L3 of four _{externally, V L2, V L1, V} SS (V L3> V L2> V L1> V
_{When SS} ) is supplied and the low-speed clock CLK is input, the voltage _VL3 ( _VSS ) and the voltage _VL2 ( _VL1 ) are alternately selected according to the low-speed clock, and the signal TEST CONT becomes When it is input, it is selected according to the signal TEST CONT, and in any case, it is supplied to the liquid crystal display driver 5 as two kinds of voltages V _SH and V _SL .

Next, the operation will be described. (Operation in segment output mode) Do not input signal TEST and signal TEST CONT. Since the control signal switching circuit 36 selects and outputs the low speed clock CLK, the liquid crystal display bias control circuit 9 selects the low speed clock from the display mode voltage _VL3 ( _VSS ) and the non-display mode voltage _VL2 ( _VL1 ). One of the modes is alternately selected on the basis of, and the transistor 6 of the liquid crystal display driver 5 is set as the voltage V _SH and the voltage V _SL.
Supply to (7). Further, the signal TEST bar causes the input selection switching circuit 32 to select the segment data instead of the test data. The segment data is obtained by driving the liquid crystal display driver 5 at a low speed via the segment control voltage conversion circuit 3.
The voltage V _SH (V _SL ) is output to the external lead 8 to turn on (turn off) the segment of the liquid crystal display device.

(Operation in Test Mode) When the signal TEST and the signal TEST CONT are input, the control signal switching circuit 36 selects and outputs the signal TEST CONT. The liquid crystal display bias control circuit 9 selects one mode corresponding to the signal TEST CONT from the voltage V _L3 (V _SS ) in the display mode and the voltage V _L2 (V _L1 ) in the non-display mode to select the voltage V _SH and the voltage V _{SH. It} is supplied to both transistors 6 and 7 of the liquid crystal display driver 5 as _SL . Further, the input selection switching circuit 32 selects not the segment data but the test data by the signal TEST and outputs it to the segment control voltage conversion circuit 3. The test data is converted by the segment control voltage conversion circuit 3 to control the liquid crystal display driver 5. By this control, the test data can be
(3) L ″), the transistor 7 (6) is in the off state and the transistor 6 (7) is in the on state, and the voltage V _SH (V _SL ) is output to the external lead 8. Eventually, four types of voltage (V _L3 , V _L2 , V _L1 , V _SS ) is selected and output according to the test data and the signal TEST CONT and tested by the tester via the external lead 8. As described above, The display mode or the non-display mode is selected according to the signal TEST CONT, and two kinds of voltages of the selected mode are supplied to the liquid crystal display driver. The display drivers are sequentially driven, and the output current thereof flows through the resistance of the tester, and the test of the liquid crystal display driver proceeds by checking the voltage of this resistance.

[0046]

As described above in detail, the liquid crystal display controller / driver according to the first and second inventions of the present application uses a test driver for driving the liquid crystal display device at a higher speed than the liquid crystal display driver, and thereby An effect that the test of the display device can be executed at high speed is achieved. The liquid crystal display controller / driver according to the third invention of the present application can arbitrarily generate the voltage necessary for testing the built-in liquid crystal display driver, and therefore, the effect of rapidly executing the test of the liquid crystal display driver can be obtained. Play.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display controller / driver according to a first invention of the present application.

FIG. 2 is a block diagram of another liquid crystal display controller / driver according to the first invention of the present application.

FIG. 3 is a block diagram of a liquid crystal display controller / driver according to a second invention of the present application.

FIG. 4 is a block diagram of another liquid crystal display controller / driver according to the second invention of the present application.

FIG. 5 is a block diagram of a liquid crystal display controller / driver according to a third invention of the present application.

FIG. 6 is a block diagram of a conventional liquid crystal display controller / driver.

[Explanation of symbols]

 1 liquid crystal display data memory 3 segment control voltage conversion circuit 5 liquid crystal display driver 8 external lead 9 liquid crystal display bias control circuit 10 output control circuit 14 test driver 20 general-purpose output data holding circuit 27, 28 power supply selector switch 29 power supply selector switch control circuit 32 Input selection switching circuit 36 Control signal switching circuit

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[Procedure amendment]

[Submission date] May 31, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction content]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display controller driver having a circuit for testing a liquid crystal display controller or a liquid crystal display driver.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

When the signal PORT is input, the output control circuit 10
Is not the segment data of the liquid crystal display data memory 1, but the general-purpose output data input from the general-purpose output data holding circuit via the data line 23, and the first and second outputs are selected according to the selected data. The test driver is controlled at high speed, and the segment control voltage conversion circuit 3 is controlled by the third output.
The operation of is stopped. To receive data from an external device connected to the external lead 8,
The external lead 8 is connected to a circuit (not shown) via the general-purpose input circuit 25 and the data line 21. When the read signal RD is given to the general-purpose input circuit 25 through the signal line 26, the data from the external device is read. It omitted since the other structures are the same as in FIG.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

In the general-purpose mode, it is possible to receive data from an external device connected to the external lead 8. The external lead 8 is connected to a circuit (not shown) via the general-purpose input circuit 25 and the data line 21. However, when the read signal RD is given to the general-purpose input circuit 25 through the signal line 26, the data from the external device is read. The other configuration is similar to that of FIG. 3, and thus the description is omitted.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

(Operation in test mode) When the signal TEST is input, the voltage changeover switches 27 and 28 are switched, and the voltage V _DD (V _SS ) changes to the liquid crystal display driver 5 and the test driver.
Supplied to 14. Then, the segment data of the liquid crystal display data memory 1 is read at a high speed clock, drives the test driver 14 via the output control circuit 10, and drives the liquid crystal display driver 5 via the segment control voltage conversion circuit 3. The test driver 14 and the liquid crystal display driver 5 driven in parallel by the segment data output the voltage V _DD (V _SS ) according to the segment data to the liquid crystal display device to be tested through the external lead 8. In this way, the liquid crystal display is displayed with a larger output than the test driver 14 alone.
The device test is performed.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

Next, the operation will be described. (Operation in segment output mode) Do not input signal TEST and signal TEST CONT. Since the control signal switching circuit 36 selects and outputs the low speed clock CLK, the liquid crystal display bias control circuit 9 selects the low speed clock from the display mode voltage _VL3 ( _VSS ) and the non-display mode voltage _VL2 ( _VL1 ). Are alternately selected based on the above, and are supplied to the transistor 6 (7) of the liquid crystal display driver 5 as the voltage V _SH and the voltage V _SL . Further, the signal TEST bar causes the input selection switching circuit 32 to select the segment data instead of the test data. The segment data drives the liquid crystal display driver 5 at a low speed through the segment control voltage conversion circuit 3 and outputs the voltage V _SH (V _SL ) to the external lead 8 to turn on (turn off) the segment of the liquid crystal display device.

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (3)

[Claims] 1. A liquid crystal display controller driver including a liquid crystal display driver for driving a liquid crystal display device under the control of a liquid crystal display controller, comprising: a test driver for driving the liquid crystal display device at a higher speed than the liquid crystal display driver.
A liquid crystal display controller comprising: an output unit that outputs the outputs of the liquid crystal display driver and the test driver from the same output path; and a control unit that controls output / non-output of the test driver and the liquid crystal display driver. driver. 2. The liquid crystal display controller driver according to claim 1, further comprising means for driving the test driver and the liquid crystal display driver in parallel. 3. A liquid crystal display controller / driver for selecting a required voltage from a plurality of voltages based on a clock signal and supplying the selected voltage to a liquid crystal display driver, and driving the liquid crystal display driver according to segment data displayed on the liquid crystal display device. Switching means for switching between a test control signal for selecting a voltage for testing the liquid crystal display driver from the plurality of voltages and the clock signal, and switching for switching between test data for testing the liquid crystal display driver and the segment data And a liquid crystal display controller / driver.