JPS5987841A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS5987841A
JPS5987841A JP19752382A JP19752382A JPS5987841A JP S5987841 A JPS5987841 A JP S5987841A JP 19752382 A JP19752382 A JP 19752382A JP 19752382 A JP19752382 A JP 19752382A JP S5987841 A JPS5987841 A JP S5987841A
Authority
JP
Japan
Prior art keywords
hybrid
case
substrates
integrated circuit
hybrid substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19752382A
Other languages
Japanese (ja)
Inventor
Kunio Kobayashi
邦雄 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19752382A priority Critical patent/JPS5987841A/en
Publication of JPS5987841A publication Critical patent/JPS5987841A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the degree of integration of an electronic part and miniaturize the part by disposing a plurality of hybrid substrates in a resin through spacers. CONSTITUTION:The electronic parts 5 are each mounted to both hybrid substrates 1, both substrates are separated by the spacers 6, stacked and unified while leads 4 are fitted, and both hybrid substrates 1 are hung and encased in a case 3, and the resin 2 is poured and encased into the case 3 under the state and the circuit is assembled. The case 3 is not enlarged because mutually stacked structure is formed even when two of the hybrid substrates 1 are used, and the size of the hybrid substrates 1 need not be enlarged even when the number of outgoing terminals increases because lead fitting sections are formed to the whole circumferential edges of two hybrid substrates 1, and the circuit is miniaturized.

Description

【発明の詳細な説明】 本発明は混成集積回路に関する。[Detailed description of the invention] The present invention relates to hybrid integrated circuits.

一般に、高機能電子機器化に伴なって電子回路の高東積
小型化が要求されてらるが、これらの要求は混成集積回
路にも同様に要求されている。In general, as electronic devices become more sophisticated, electronic circuits are required to be smaller in size and higher in size, and these requirements are also required for hybrid integrated circuits.

従来、ケース内に樹脂を用いてハイブリッド基板上封入
しｆｃ構造の混成集積回路は、第１図お工ひ第２図に示
す構造のものが知られている。第１図のものは、セラミ
ンク配線板からなるハイブリッド基板１全樹脂２を用い
てケース３内に封入しに構造となっていて、ハイブリッ
ド基板１０周縁に一端を固定した多数のリード４はその
他端を樹脂２から突出させケース３外に突出させた構造
とガっている。また、各種電子部品（チップ等も含む）
５はハイブリッド基板１の一面にのみ実装されている。2. Description of the Related Art Conventionally, a hybrid integrated circuit having an FC structure in which resin is used in a case and sealed on a hybrid substrate is known, and the structure shown in FIG. 1 and shown in FIG. 2 is known. The one in Fig. 1 has a structure in which a hybrid board 1 made of a ceramic wiring board 1 is entirely sealed in a case 3 using resin 2, and a large number of leads 4, one end of which is fixed to the periphery of the hybrid board 10, are fixed to the other end. It has a structure in which it protrudes from the resin 2 and protrudes outside the case 3. In addition, various electronic components (including chips, etc.)
5 is mounted only on one side of the hybrid board 1.

しかし、この構造はハイブリッド基板ｌの占有面積が大
きい割・合に内蔵回路が少なく、小型化が図９難い欠点
がある。However, this structure has the disadvantage that the area occupied by the hybrid substrate l is large and the number of built-in circuits is small, making it difficult to downsize.

そこで、−・イブリント基板？大きくすることなく実装
密度を向上させ内蔵回路を多くするものとして、第２図
に示すものが採用されている。この混成集積回路はｔ子
部品５ｔハイブリッド基板１０両面に実装したものであ
シ、第１図のものに比較して実装量は略２倍となる。し
たがって、回しの電子部品５を実装しｆｃ場合には、第
１図のハイブリッド基板１の一面にのみ実装したものに
比較して略半分の大きさの−・イブリント基板ｌでよく
、小型化が図れる。So, - Evelint board? The one shown in FIG. 2 has been adopted to improve the packaging density and increase the number of built-in circuits without increasing the size. This hybrid integrated circuit has 5t child components mounted on both sides of the hybrid board 10, and the amount of mounting is approximately twice that of the one shown in FIG. Therefore, when mounting electronic components 5 on the circuit board 1, it is only necessary to use a hybrid board l that is approximately half the size of the one mounted only on one side of the hybrid board 1 shown in FIG. I can figure it out.

しかし、この両面実装構造は一枚のハイブリンド基板の
表裏面にそれぞれ電子部品を実装するため、実装時に下
面（裏面）の電子部品の破損防止に注意を払って上面（
表面）の電子部品の実装全行なわなければならず、組立
がし難い欠点がある。However, in this double-sided mounting structure, electronic components are mounted on the front and back sides of a single hybrid board, so care must be taken to prevent damage to the electronic components on the bottom (back) surface during mounting.
The disadvantage is that it is difficult to assemble, as all the electronic components on the front surface must be mounted.

また、この構造では、電子部品の実装にあってはハイブ
リッド基板１の大きさを大きくする必侠はない場合であ
っても、電子部品の高実装化によるリード数の増大によ
って、リードのすべてがノ）イブリッド基板１の周縁に
取シ付けることができなくなることもあり、リード配設
のために・・イブリッド基板１０大型化？図ってリード
取付部を確保しなければならないこともあシ、小型化に
逆行してしまう。In addition, with this structure, even if there is no need to increase the size of the hybrid board 1 when mounting electronic components, all of the leads may be (g) It may not be possible to attach it to the periphery of the hybrid board 1, and in order to arrange the leads... Will the hybrid board 10 be made larger? In addition, it is necessary to secure a lead attachment part, which goes against the trend of miniaturization.

さらに、この構造では、ノ１イブリッド基板１の両面に
電子部品５′に取ｐ付けた後でないと回路特性検査が行
なえない。このため、−面側にのみ不良部分があるよう
な場合でも全体は不良となるため歩留が低下し易い傾向
にある。Furthermore, with this structure, the circuit characteristics cannot be tested until after the electronic components 5' are attached to both sides of the hybrid board 1. For this reason, even if there is a defective part only on the negative side, the entire part becomes defective, and the yield tends to decrease.

しｋがって、本発明の目的は電子部品の高集租度化が図
れるとともに小型化が図れかつ組立歩留が高くなるよう
な構造の混成集積回路を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a hybrid integrated circuit having a structure that allows high integration of electronic components, miniaturization, and high assembly yield.

このような目的を達成するために本発明は、ケースと、
このケース内に絶縁性樹脂によって封入され、かつ電子
部品を取ル付けたノ・イブリッド基板と、この−・イブ
リッド基板の周縁に一端が固定され他端がケース外に突
出する複数のリードと、から々る混成集積回路において
、前記ハイブリッド基板はスペーサを介して複数枚樹脂
内に配設されてなるものであって　以下実施例により本
発明を説明する。In order to achieve such an objective, the present invention includes a case,
A hybrid board sealed with an insulating resin in the case and having electronic components attached thereto; a plurality of leads having one end fixed to the periphery of the hybrid board and the other end protruding outside the case; In the hybrid integrated circuit, a plurality of the hybrid substrates are disposed in a resin via spacers.The present invention will be explained below with reference to Examples.

第３図は本発明の一実施例による漣成集積回路全示す一
部を断面とした概略鋼視図である。同図に示すように、
この実施例の混成集積回路は、ケース３内にセラミック
配線板からまる２枚のハイブリッド基板１を配し、ハイ
ブリッド基板１は樹脂２によって封入されている。２枚
のハイブリッド基板１はスペーサ６によって一定間隔を
隔てて平行に配設されている。スペーサ６は棒状体（ビ
ン構造）からなるとともに、両端に細い挿嵌部上宿し、
この挿僚部全それぞれのバイブＩＪ　２ド基板１め僚合
孔に止ま９嵌めによって固定している。FIG. 3 is a schematic perspective view, partially in section, showing the entire integrated circuit according to an embodiment of the present invention. As shown in the figure,
In the hybrid integrated circuit of this embodiment, two hybrid substrates 1 made of ceramic wiring boards are arranged in a case 3, and the hybrid substrates 1 are sealed with a resin 2. The two hybrid substrates 1 are arranged in parallel with a constant interval between them by a spacer 6. The spacer 6 is made of a rod-shaped body (bottle structure), and has thin fitting portions on both ends.
All of these insertion parts are fixed in the first mating holes of the two-vibrator board by fitting with a stopper 9.

・　　そして、一方（上部）のハイブリッド基板１には
上面にチップ等全含む電子部品５を常用の実装構造で実
装し、他方（下部）のハイブリッド基板ｌには下面に同
様に電子部品５を実装している。前記ケース３は樹脂あ
るいは金属ケースからなり、ハイブリッド基板１を封入
する樹脂２は絶縁性のものと外っている。また、スペー
サ６は絶縁体あるいは、両ハイブリッド基板１の一部配
紐層間を導通させるための役割會果たすように金属から
なっていてもよい。また、スペーサ６とハイブリッド基
板１との接合は止まシ嵌め構造ではなく半田等の鑞材あ
るいは接着剤を用いてもよい。- Then, on one (upper) hybrid board 1, electronic components 5 including all chips etc. are mounted on the upper surface using a conventional mounting structure, and on the other (lower) hybrid board l, electronic components 5 are similarly mounted on the lower surface. are doing. The case 3 is made of a resin or metal case, and the resin 2 that encloses the hybrid board 1 is insulating. Further, the spacer 6 may be made of an insulator or a metal so as to serve to provide electrical continuity between some of the wiring layers of both hybrid substrates 1. Further, the spacer 6 and the hybrid substrate 1 may be joined to each other by using a soldering material such as solder or an adhesive instead of a lock-fitting structure.

一方、両ハイブリッド基板１の周縁には回定間隔にリー
ド４が固定（半田あるいはクランプ構造で）されている
。そして、これら各リード４の外端は樹脂２を突き抜け
てケース３外に突出している。On the other hand, leads 4 are fixed to the peripheral edges of both hybrid substrates 1 at regular intervals (by solder or a clamp structure). The outer ends of these leads 4 penetrate through the resin 2 and protrude outside the case 3.

このような混成集積回路はその組立にあっては、両ハイ
ブリッド基板１にすれぞれ電子部品５を実装した後、ス
ペーサ６によって両者を離間して重ね合せて一体化する
とともにリード４の増シ付は全行い、その後、ケース３
内に両ハイブリッド基板１會吊して入れ、この状襲でケ
ース３内に樹脂２′に流し込んで封入を行なうことによ
って組立を行う。また、前記組立は両ハイブリッド基板
１１スヘーサ６によって一体化する前に、両ハイブリッ
ド基板１を別々に検査して回路特性を確認し、良品のみ
を組み合せるようにする。When assembling such a hybrid integrated circuit, after mounting electronic components 5 on both hybrid substrates 1, they are separated by a spacer 6 and then stacked and integrated. All attachments are done, and then case 3
Both hybrid substrates are suspended and put into the case 3, and then the resin 2' is poured into the case 3 and sealed, thereby assembling the case. In addition, before the assembly is performed, both hybrid boards 11 are inspected separately to confirm their circuit characteristics, and only non-defective products are combined before being integrated by the spacer 6.

このような実′＃例によれば、２枚のハイブリッド基板
１に電子部品５を実装することから実装密度が高くなる
。また、ハイブリッド基板ｌは２枚使用しても、相互に
重ね合せるような構造となるため、ケース３は大きくは
ならずかつ背丈も高くならない。したがって、小型化が
図れる。According to such an actual example, since the electronic components 5 are mounted on two hybrid boards 1, the mounting density becomes high. Furthermore, even if two hybrid substrates 1 are used, the structure is such that they are stacked on top of each other, so the case 3 does not become large or tall. Therefore, miniaturization can be achieved.

また、リード取付部は２枚のハイブリッド基板１の全周
縁と力ることから、引出端子数が多くなってもハイブリ
ッド基板１の大きさを大きくする必蚤もなく、小型化が
図れる。Further, since the lead attachment portion is in contact with the entire periphery of the two hybrid boards 1, even if the number of lead-out terminals increases, there is no need to increase the size of the hybrid board 1, and miniaturization can be achieved.

また、電子部品は両ハイブリッド基板の一面にのみ実装
すればよいことから、一枚の−・イブリッド基板の表裏
面に実装する場合に比較して実装し易い。Furthermore, since electronic components only need to be mounted on one surface of both hybrid substrates, it is easier to mount them than when mounting them on the front and back surfaces of a single hybrid substrate.

さらに、２枚のハイブリッド赤；板は一体化前にそれぞ
れ回路特性検査を行々い、良品のみを組み合せることか
ら、歩留も高く力る。Furthermore, the circuit characteristics of each of the two hybrid red boards are inspected before they are integrated, and only good products are combined, resulting in a high yield.

なお、本発明は前記実ｍ例に限定されない。たとえば、
スペーサはビン構造のものに替えて折状のものｔ使用し
ても前記同様な効果が期待できる。Note that the present invention is not limited to the above-mentioned example. for example,
The same effect as described above can be expected even if a folded spacer is used instead of a bottle-shaped spacer.

また、ハイブリッド基板？さらに多数使用すれば、混成
共秋回路の高集積化、小型化がさらに図れる。Also, a hybrid board? If a larger number of them are used, the hybrid circuit can be further integrated and miniaturized.

以上のように、本発明によれば、高集積化、／ト型化が
可能でかつ組立が容易となシ、さらに組立の歩留が高い
湿成集掃回路？折供することができる。As described above, according to the present invention, it is possible to achieve high integration and/or T-type wet sweep circuits that are easy to assemble and have a high assembly yield. It can be offered as an offering.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の渭成集秋回路を示す一部？断面とじた概
略角枳図、 第２図は同じく他の涼成集積回路の概略余１視図、第３
図は本発明の一実障的による漣成集積回路を示す一部を
断面としｆｃ邪路余１祝図である。 １・・・ハイブリッド基板、２・・・樹脂、３・・・ケ
ース、４・・・リード、５・・・電子部品、６・・・ス
ペーサ。Is Figure 1 a part of the conventional Shusei integrated circuit? Figure 2 is a schematic diagram with a closed cross section, Figure 2 is a schematic perspective view of another integrated circuit, Figure 3
The figure is a partial cross-sectional view of an integrated circuit according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Hybrid board, 2...Resin, 3...Case, 4...Lead, 5...Electronic component, 6...Spacer.

Claims (1)

【特許請求の範囲】[Claims] １、ケースと、このケース内に絶縁性樹脂によって封入
され、かつ電子部品を取り付けたハイブリッド基板と、
このハイブリッド基板の周縁に一端が固定され他端がケ
ース外に突出する検数のリードと、からなる混成集積回
路において、前記ハイブリッド基板はスペーサを介して
復数枚配設されたこと？特徴とする渭成祭積回路。1. A case, a hybrid board sealed with an insulating resin inside the case and equipped with electronic components,
In a hybrid integrated circuit consisting of a lead whose one end is fixed to the periphery of the hybrid board and whose other end protrudes outside the case, several hybrid boards are arranged via spacers? The characteristic product circuit of Weisei.
JP19752382A 1982-11-12 1982-11-12 Hybrid integrated circuit Pending JPS5987841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19752382A JPS5987841A (en) 1982-11-12 1982-11-12 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19752382A JPS5987841A (en) 1982-11-12 1982-11-12 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5987841A true JPS5987841A (en) 1984-05-21

Family

ID=16375878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19752382A Pending JPS5987841A (en) 1982-11-12 1982-11-12 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5987841A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625656U (en) * 1985-06-25 1987-01-14
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625656U (en) * 1985-06-25 1987-01-14
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices

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