JPS5986741U

JPS5986741U - Input signal detection circuit

Info

Publication number: JPS5986741U
Application number: JP18271182U
Authority: JP
Inventors: 平本　行雄; 正己武内; 和義岡田; 浩一村上
Original assignee: 日産自動車株式会社
Priority date: 1982-12-02
Filing date: 1982-12-02
Publication date: 1984-06-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の入力信号検出回路の構成を示すブロック
図、第２図は第１図の各部の信号状態を示す波形図、第
３図は本考案に係わる入力信号検出回路の第１実施例の
構成を示すプロ゛ジク図、第４図は第３図における各部
の信号状態を示す波形図、第５図は本考案に係わる入力
信号検出回路の第２実施例の構成を示すブロック図、第
６図は第５図における各部の信号状態を示す波形図であ
る。１・・・・・・初段のＤ型フリップフロップ、２・・・
・・・遅延用り型フリップフロップ、３・・・・・・終
段のＤ型、フリップフロップ、４・・・・・・ＡＮＤゲ
ート、５・・・・・・移相用り型フリップフロップ、６
・・・・・・Ｔ型フリップフロップ、７・・・・・・イ
ンバータ、φ亡・・・・第１の基準クロック、ユ２・・
・、・・・第２の基準クロック。 ’２　　　　　　　−　　　−− φ。 φ２　　　　　　　　　　　　　　　　　　−φ１　　
　−　　　　　−　− −１　１１　　ｔ−Fig. 1 is a block diagram showing the configuration of a conventional input signal detection circuit, Fig. 2 is a waveform diagram showing signal states of each part in Fig. 1, and Fig. 3 is a first implementation of the input signal detection circuit according to the present invention. 4 is a waveform diagram showing the signal state of each part in FIG. 3; FIG. 5 is a block diagram showing the structure of the second embodiment of the input signal detection circuit according to the present invention. , FIG. 6 is a waveform diagram showing the signal state of each part in FIG. 5. 1...First stage D-type flip-flop, 2...
... Delay type flip-flop, 3... Final stage D type flip-flop, 4... AND gate, 5... Phase shift type flip-flop ,6
...T-type flip-flop, 7...Inverter, φ2...1st reference clock, U2...
. . . second reference clock. '2 − − φ. φ2 −φ1
- - - -1 11 t-

Claims

[Claims for Utility Model Registration] A first-stage flip-flop that reads a binary signal supplied to an input terminal in synchronization with a first reference clock; and a binary output of the first-stage flip-flops that are connected in series with each other. N delay flip-flops consisting of a first stage to an Nth stage that sequentially shift I in synchronization with the first reference clock; a binary output of the Nth stage delay flip-flop; a final-stage flip-flop read in synchronization with the first reference clock; The 2nd
an S-phase flip-flop read in synchronization with the reference clock; each non-inverted output of the first stage and the first to (N-1) stage flip-flops; the inverted output of the final stage flip-flop; a logic gate that obtains an AND with a non-inverting output of a phase shifting flip-flop; the logic state of the binary signal at the input terminal is "1" at least N times the period of the first reference clock; An input signal detection circuit characterized in that the input signal detection circuit is configured to obtain a detection pulse of a predetermined width from the logic gate only in some cases.