JPS5984448A - Resin sealed type semiconductor device and manufacture thereof - Google Patents
Resin sealed type semiconductor device and manufacture thereofInfo
- Publication number
- JPS5984448A JPS5984448A JP57194547A JP19454782A JPS5984448A JP S5984448 A JPS5984448 A JP S5984448A JP 57194547 A JP57194547 A JP 57194547A JP 19454782 A JP19454782 A JP 19454782A JP S5984448 A JPS5984448 A JP S5984448A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- film
- semiconductor
- integrated circuit
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Non-Volatile Memory (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Read Only Memory (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、小型にして安価で量産性の高い樹脂封止型
半導体装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device that is small, inexpensive, and highly mass-producible, and a method for manufacturing the same.
集積回路素子を収容する７４ツケージには種々の形態が
ある。すなわち、キャンパッケージ、デュアルインライ
ンパッケージ、フラット／ゼッヶージ、アキシャル♂ン
パッケージ、リードレスチップキャリヤｉｊツケージな
どである。There are various forms of 74 cages that house integrated circuit devices. That is, they include can packages, dual in-line packages, flat/square packages, axial female packages, and leadless chip carrier packages.
これらのパッケージの中で、最も大量に用いられている
ものは、デュアルインラインパッケージ（以下、ＤＩＰ
と云う）である、このＤＩＰは使用材料により、セラミ
ックＤＩＰ、ＣＥＲ−ＤＩＰ。Among these packages, the one most widely used is the dual inline package (hereinafter referred to as DIP).
Depending on the material used, this DIP can be ceramic DIP or CER-DIP.
プラスチックＤＩＰ （モールドＤＩＰ）に分けられる
。Divided into plastic DIP (mold DIP).
これらのうち、特に、量産性や価格の面から、プラスチ
ックＤＩＰがすぐれておシ、最も大量に使用されている
。したがって、集積回路素子はその種類によらず、グラ
スチックＤＩＰに収容することが望まれている。Among these, plastic DIP is particularly superior in terms of mass production and cost, and is used in the largest quantity. Therefore, regardless of the type of integrated circuit element, it is desired to house it in a plastic DIP.
しかしながら、集積回路素子の特性などにより、プラス
チックＤＩＰに収容するに適さない素子がある。たとえ
ば、続出専用メモリの中で書込み、消去可能なＥＰＲＯ
Ｍ （Ｅｒａｓａｂｌｅ ＰｒｏｇｒａｍＩｍａｂｌｅ
Ｒｅａｄ ０ｎｌｙ Ｍｅｍｏｒ）’）は多品種少量生
産的な装置や製品の記憶素子として最適であシ、新製品
の開発や設計および仕様の変更に対し、従来とは異なる
融通性を与えている。However, due to the characteristics of integrated circuit elements, some elements are not suitable for being accommodated in a plastic DIP. For example, an EPRO that can be written and erased in a dedicated memory
M (Erasable Program Imable
The ReadOnly Memory) is ideal as a memory element for devices and products produced in high-mix, low-volume production, and provides flexibility that is different from the conventional technology for the development of new products and changes in design and specifications.
近年ＥＰＲＯＭの需要は増加の一途をたど９、今や民生
用、産業用を問わず、多くの製品に使われているが、Ｅ
ＦＲＯＭにおいては、メモリの消去を行うに、フローテ
ィングゲートに残された負電荷を４３ ｅＶ以上の紫外
線（２５３７＾＝ ４．９ ｅＶ）で励起し、Ｓｉ基板
に放電させて行う。Demand for EPROMs has been increasing in recent years9, and they are now used in many products, both consumer and industrial.
In FROM, memory is erased by exciting the negative charges left on the floating gate with ultraviolet rays of 43 eV or more (2537 = 4.9 eV) and discharging them onto the Si substrate.
さらに詳細に記述すると、ＥＰＲＯＭのメモリセル構造
および記憶方法を説明する。メモリセルは基本的ニＮ゛
チャンネルのＭＯＳ）ランジスタ構造であシ、これに電
荷蓄積用の７四−ティングｒ−トが付加されている。初
期の状態では、フローテ（７グ）ｒ”−トに電荷はなく
、スレックヨールト電圧は小さい。More specifically, the memory cell structure and storage method of EPROM will be described. The memory cell has a basic two-channel MOS (MOS) transistor structure, to which is added a 74-ring gate for charge storage. In the initial state, there is no charge on the float (7g) r''-to, and the Sleckjord voltage is small.
書込み時はドレインとコントロールゲートに高電圧をか
け、アンパランシュ降伏時に発生させたホットエレクト
ロンをフローティングダートにチャージさせる。このフ
ローティングゲートは絶縁されておシ、電荷は電源を切
っても残っておシ、記憶内容が保持されている。During writing, a high voltage is applied to the drain and control gate to charge the floating darts with hot electrons generated during unparanche breakdown. This floating gate is insulated, so the charge remains even when the power is turned off, and the memory contents are retained.
このとき、ＭＯＳトランジスタはフローティングクー・
−トにチャージされた負電荷によシ、そのＩＤ８− Ｖ
Ｇ８曲線が右にシフトする。読出し時には、ダート電圧
（ＶＯ２）を適当な値に固定し、電流（ＩＤ８ ）の有
無をセンスアップで判定し、情報の「１」または「０」
を出力する。At this time, the MOS transistor is a floating cooler.
- Due to the negative charge charged to the ID8-V
The G8 curve shifts to the right. When reading, the dart voltage (VO2) is fixed at an appropriate value, the presence or absence of current (ID8) is determined by sense-up, and the information is set as "1" or "0".
Output.
消去は前述したように、紫外線を照射することニヨシ、
フローティングダートに残された負電荷をＳｉ基板に放
′電させて行う。この結果、ＭＯＳトラン、ジスタのＩ
ｎｓ −ＶＧｓ曲線は左にシフトし、書込み前の状態に
戻る。As mentioned above, erasing is done by irradiating with ultraviolet light.
This is done by discharging the negative charges left on the floating darts onto the Si substrate. As a result, the I of the MOS transistor and transistor
The ns-VGs curve shifts to the left and returns to the state before writing.
ここで、従来のＥＦＲＯＭのノ’？ツケージを第１図（
ａ）、第１図（ｂ）に示す。第１図（ａ）は斜視図であ
り、第１図（ｂ）は第１図（ａ）の断面図である。この
第１図（ａ）、第１図（ｂ）の両図において、前述した
ように、ＥＦＲＯＭは紫外線を照射する必要上、パッケ
ージのベレットマウント部２の封止用のキャップに紫外
線透過用部材１であるサファイヤまたは透明アルミナ製
υッドを低融点ガラスなどの接着剤で貼ジ付けたり、あ
るいは紫外線透過ガラス（ＵＶガラス）をキャップに埋
め込んだりしている。Here, what about conventional EFROM? Figure 1 (
a) and shown in FIG. 1(b). FIG. 1(a) is a perspective view, and FIG. 1(b) is a sectional view of FIG. 1(a). In both FIG. 1(a) and FIG. 1(b), as mentioned above, since the EFROM needs to be irradiated with ultraviolet rays, an ultraviolet transmitting member is attached to the sealing cap of the bullet mount portion 2 of the package. 1, a sapphire or transparent alumina υ pad is pasted with an adhesive such as low-melting glass, or an ultraviolet-transparent glass (UV glass) is embedded in the cap.
ところが、従来構造においては、リッドの貼付けや、埋
込みのために特別な工程が必要であり、工数が多くなる
他に、リッド貼付は部の機械的および熱的衝撃に弱く、
半導体装置の信頼性低下の原因となるおそれがあるなど
の欠点がある。However, in the conventional structure, a special process is required for attaching and embedding the lid, which not only increases the number of man-hours but also makes the lid attaching vulnerable to mechanical and thermal shocks.
There are drawbacks such as the possibility of causing a decrease in reliability of the semiconductor device.
したがって、これらを解決するために、封止用のキャッ
プ自体を紫外線透過材料で形成する試みがある。しかし
ながら、この方法も、グラスチックＤＩＰ＋７５形態に
はなシ得ず、量産性、コストの面において不十分である
。Therefore, in order to solve these problems, attempts have been made to form the sealing cap itself from an ultraviolet-transparent material. However, this method is also incomparable to the glass DIP+75 form, and is insufficient in terms of mass production and cost.
この発明は、上記従来の欠点を解消するためになされた
もので、低コスト、量産性にすぐれ、・しかも信頼性も
すぐれ、ＥＰＲＯＭのモールド形パッケージに利用する
ことのできる樹脂封止型半導体装置およびその製造方法
を提供することを目的とする。This invention was made to eliminate the above-mentioned conventional drawbacks, and is a resin-sealed semiconductor device that is low cost, excellent in mass production, and has excellent reliability, and can be used in a molded package of EPROM. The purpose is to provide a method for producing the same.
以下、この発明の樹脂封止型半導体装置およびその製造
方法の実施例について図面に基づき説明するが、具体的
実施例の説明に先立ち、まず、この発明の特徴について
概述することにする。Embodiments of a resin-sealed semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.Prior to describing specific embodiments, the features of the present invention will first be outlined.
この発明の樹脂封止型半導体装置の製造方法の特徴は紫
外線消去形ＥＰＲＯＭのノ＋ツケージ方法において、従
来のパッケージのごとく、透明アルミナあるいは紫外線
透過ガラスあるいは透明グラスチックのキップをパッケ
ージに接着させる構造とは異なり、集積回路素子製造プ
ロセスにおいて、ウェハの状態、すなわら、素子を分割
しない状態において、紫外線透過形態硬化性樹脂浴液を
ウェハに塗浄し、加熱工程を経た後、熱硬化性樹脂膜を
形成し、周知のホトリソグラフィにより、谷素子のメモ
リ部の所望・ぞターン以外、を除去するようにしている
。The feature of the method for manufacturing a resin-sealed semiconductor device of the present invention is that in the packaging method of an ultraviolet erasable EPROM, a cap made of transparent alumina, ultraviolet transmitting glass, or transparent glass is bonded to the package, as in the case of conventional packages. In contrast, in the integrated circuit device manufacturing process, an ultraviolet-transparent curable resin bath liquid is applied to the wafer in the wafer state, that is, in a state where the devices are not divided, and after a heating process, a thermosetting resin bath liquid is applied to the wafer. A resin film is formed, and the memory portion of the valley element except for the desired turns is removed using well-known photolithography.
したがって、スクライプラインあるいはポンプイングツ
４ツド部などは何等後工程であるワイヤデンディングあ
るいはスクライプラインなどへの影響はない。Therefore, the scribe line or the pumping tube 4 joint portion has no effect on subsequent processes such as wire endings or scribe lines.
その後、ウエノ・を後処理工程であるスクライブあるい
はワイヤボンディングなど、組立て工程を経て、最後に
モールド樹脂材、たとえは、エポキシ樹脂により、前記
熱硬化性樹脂膜の所望部以外を除いて、樹脂封止するこ
とによシ、これまで困難であったＥＰＲＯＭのモールド
形パッケージヲ可能とするものである。これによシ、素
子の量産性、コストおよび信頼性が大幅に向上すると云
う利点を有するものである。After that, the urethane film goes through an assembly process such as scribing or wire bonding, which is a post-processing process, and is finally resin-sealed with a molding resin material, for example, an epoxy resin, except for the desired parts of the thermosetting resin film. By stopping the process, it becomes possible to create an EPROM mold package, which has been difficult up to now. This has the advantage that the mass productivity, cost, and reliability of the device can be greatly improved.
次に、この発明の樹脂封止型半導体装置の製造方法の＝
実施例について図面に基づき説明する。Next, = of the method for manufacturing a resin-sealed semiconductor device of the present invention
Examples will be described based on the drawings.
第２図（ａ）ないし第２図（ｇ）はその−実施例の工程
説明図である。。まず、第２図（ａ）に示すように、半
導体基板１１上にＥＰＲＯＭ型集積回路素子１２を形成
する。FIG. 2(a) to FIG. 2(g) are process explanatory diagrams of this embodiment. . First, as shown in FIG. 2(a), an EPROM type integrated circuit element 12 is formed on a semiconductor substrate 11.
次いで、半導体塞板１１上に、紫外線透過形のポリイミ
ド樹脂前駆体溶液ＰＩ２５６６ （商品名ｒユポン社（
米国）Ｍ品名）を塗布し、その後、１００°（！ＩＨ，
２００°ＱＩＨおよび３５０°ＣＩＨで（窒素中循環雰
囲気中）加熱し、ポリイミド膜１３をおよそ１〜１００
μｍの厚さに形成する。Next, an ultraviolet-transmissive polyimide resin precursor solution PI2566 (trade name: Yupon Co., Ltd.) was placed on the semiconductor blocking plate 11.
100° (!IH,
Heating at 200°QIH and 350°CIH (in a nitrogen circulating atmosphere), the polyimide film 13
Formed to a thickness of μm.
その後、第２図（ｂ）に示すように、周知のホトリソグ
ラフィ法により、ＥＦＲＯＭの所望メモリ部をカバーす
るように、レジストパターン１４を形成する。このレジ
ストパターン１４はその後のポリイミド膜１３を第２図
（ｃ）に示すごとくにエツチングする際のマスクであシ
、プラズマによりポリイミド膜１３をエツチングするに
は、ボッ型レジストであるＭＰ １４００レジスト（商
品名であυ、シラプレー社（米国））あるいはポリシリ
コン膜やシリコン窒化膜あるいはアルミニウムなどの金
属膜が適している。Thereafter, as shown in FIG. 2(b), a resist pattern 14 is formed by a well-known photolithography method so as to cover a desired memory portion of the EFROM. This resist pattern 14 is used as a mask when etching the polyimide film 13 as shown in FIG. The product name is υ, Silapray Corporation (USA)), a polysilicon film, a silicon nitride film, or a metal film such as aluminum is suitable.
一方、湿式エツチングによシ、ポリイミド膜１３をエツ
チングするには、ネガ形しノストＫＭＲ７４７レジスト
（商品名であシ、コダック社製）が適している。これら
を用いて、前記方法によりポリイミド膜１３をエツチン
グする。On the other hand, for etching the polyimide film 13 by wet etching, a negative type Nost KMR747 resist (trade name: Ashi, manufactured by Kodak Corporation) is suitable. Using these, the polyimide film 13 is etched by the method described above.
この湿式エツチングでは、ヒドラジン系溶液全温度３０
°Ｃ〜４０℃にして、前記半導体基板１１をこのヒドラ
ジン系溶液内に約１０〜２０分間浸漬し、ポリイミド膜
１３の膜厚をおよぞ５０μｍエツチングする。In this wet etching, the total temperature of the hydrazine solution was 30
The semiconductor substrate 11 is immersed in this hydrazine solution for about 10 to 20 minutes at a temperature of .degree. C. to 40.degree. C., and the polyimide film 13 is etched to a thickness of about 50 .mu.m.
その後、第２図（ｄ）に示すように、不要のレジストパ
ターン１４を除去する。この後、半導体基板１１は周知
の後処理工程を経て、ＥＰＲＯＭ集積回路素子片に分割
すると、第２図（ｅ）の外観斜視図のごとくになる。こ
の第２図（ｅ）の１６は一つの半導体チップを示す。Thereafter, as shown in FIG. 2(d), unnecessary resist pattern 14 is removed. Thereafter, the semiconductor substrate 11 undergoes a well-known post-processing process and is divided into EPROM integrated circuit element pieces, resulting in an appearance as shown in the perspective view of FIG. 2(e). Reference numeral 16 in FIG. 2(e) indicates one semiconductor chip.
このようにして得られたＥＰＲＯＭ型集積回路素子片の
半導体チツ−７’１６は第２図（ｆ）に示すごとく、周
知の組立て工程で組み立てられる。The semiconductor chip 7'16 of the EPROM type integrated circuit element piece thus obtained is assembled by a well-known assembly process, as shown in FIG. 2(f).
この第２図（ｆ）において、マウントアイランド１５に
上記の半導体チップ１６をマウント材１７（Ａｕあるい
はエポキシ系有機銀ペースト）によシ接着する。その後
、Ａｕ線あるいはＡ、ｄ線によるワイヤ１９をリード片
１８と半導体チップ１６のｌ？ンデイングパッド部とを
接続する。In FIG. 2(f), the semiconductor chip 16 is bonded to the mounting island 15 using a mounting material 17 (Au or epoxy organic silver paste). After that, wires 19 made of Au wires or A and d wires are connected to the lead piece 18 and the semiconductor chip 16. Connect to the binding pad section.
その後、封入樹脂２０により、ＥＩＲＯＭのメモリ部に
紫外線照射を要する所望領域を除いて封入すると、その
完成品は第２図（ｇ）の斜視図のごとくになる。なお、
第２図（ｆ）、第２図（ｇ）における２１は紫外線照射
孔である。Thereafter, the memory section of the EIROM is sealed with a sealing resin 20 except for the desired area requiring ultraviolet irradiation, and the finished product becomes as shown in the perspective view of FIG. 2(g). In addition,
Reference numeral 21 in FIGS. 2(f) and 2(g) indicates an ultraviolet irradiation hole.
以上説明したように、第１の実施例では、紫外線透過形
のポリイミド樹脂を半導体基板に塗布してポリイミド膜
を形成し、ＥＦＲＯＭの紫外線照射を要する所望領域に
選択的にパターンを形成し、ＥＰＲＯＭ型集積回路素子
に対応するポリイミド膜以外を除去して樹脂村正イるＳ
う１ｚしｒ：ので、を棗田難テアったＥＰＲＯＭのモー
ルドパッケージが可能となる。したがって、量産性、コ
スト、信頼性向上の点で大きな利点がある。As explained above, in the first embodiment, a polyimide film is formed by coating a semiconductor substrate with an ultraviolet-transmissive polyimide resin, and a pattern is selectively formed in a desired area of the EFROM that requires ultraviolet irradiation. Muramasa resin is removed by removing the polyimide film that corresponds to the type integrated circuit element.
1zr: Therefore, it becomes possible to mold package the EPROM, which was difficult to achieve by Natsuda. Therefore, there are great advantages in terms of mass productivity, cost, and reliability improvement.
以上のように、この発明の樹脂封止型半導体装置および
その製造方法によれば、ＥＰＲＯＭ型集積回路素子を形
成した半導体基板に紫外線に対して透明な熱硬化性樹脂
を塗布および加熱して熱硬化性樹脂膜を形成し、この熱
硬化性樹脂膜をＥＰＲＯＭ型集積回路素子の部分を除い
て除去して半導体基板をスクライプ分割して得た半纏体
チップをマウント材に接着させかつ所定の接続を行った
後、熱硬化性樹脂膜の表面を除いて封入樹脂で封入する
ようにしたので、モールドパッケージが可能となる。As described above, according to the resin-sealed semiconductor device and its manufacturing method of the present invention, a thermosetting resin transparent to ultraviolet rays is coated and heated on a semiconductor substrate on which an EPROM type integrated circuit element is formed. A curable resin film is formed, this thermosetting resin film is removed except for the EPROM type integrated circuit element, and the semi-integrated chips obtained by scribing and dividing the semiconductor substrate are adhered to a mounting material and predetermined connections are made. After this, the entire surface of the thermosetting resin film is encapsulated with an encapsulating resin, making it possible to form a mold package.
したがって、量＝Ｂならびに信頼性が向上するとともに
、コストダウンが可能となる利点を有しＥＰＲＯＭのモ
ールド形・七ツケージに利用することができる。Therefore, the quantity B and reliability are improved, and the cost can be reduced, and it can be used in a mold type EPROM and a seven-stage cage.
第１図（ａ）は従来のＥＦＲＯＭのパッケージの斜視図
、第１図（ｂ）は第１図（ａ）の断面図、第２図（ａ）
ないし第２図（ｇ）はそれぞれこの発明の樹脂封止型−
ト得体装置の製造方法の一実施例の工程説明図である。
１１・・・半導体基板、１２・・・ＥＰＲＯＭ型集積回
路素子、１３゛・・・ポリイミド膜、１４・・・ンジス
トパターン、１５・・・マウントアイランド、１６・・
・半導体チップ、１７・・・マウント材、１８・・・リ
ード片、１９・・・ワイヤ、２０・・・封入樹脂、２１
・・・紫外線照射孔。
特許出願人 沖電気工業株式会社
手続補正書
昭和５８年杓月Ｎ、９日
特許庁長官若杉和夫 殿
１、事件の表示
昭和５７年 特 許 願第 １９４５４７ 号２、
発明の名称
樹脂封止型半導体装縫およびその製造方法３、補正をす
る者
事件との関係 特 許 出願人（０２９）沖電
気工莱株式会社
４、代理人
５、補正命令の日刊 昭和 年 月 日 （自
発）６、補正の対象
ランシエ」とＩＪ正する。Fig. 1(a) is a perspective view of a conventional EFROM package, Fig. 1(b) is a sectional view of Fig. 1(a), and Fig. 2(a)
2(g) to 2(g) respectively show resin-sealed molds of the present invention.
FIG. 2 is a process explanatory diagram of an embodiment of a method for manufacturing a toner body device. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, 12... EPROM type integrated circuit element, 13'... Polyimide film, 14... Insist pattern, 15... Mount island, 16...
- Semiconductor chip, 17... Mounting material, 18... Lead piece, 19... Wire, 20... Encapsulating resin, 21
...UV irradiation hole. Patent Applicant: Oki Electric Industry Co., Ltd. Procedural Amendment No. 9, 1982, Kazuo Wakasugi, Commissioner of the Japan Patent Office, 1, Indication of Case, 1981, Patent Application No. 194547, 2,
Name of the invention: Resin-encapsulated semiconductor packaging and its manufacturing method 3; Relationship with the case of the person making the amendment Patent Applicant (029) Oki Denki Korai Co., Ltd. 4, Agent 5, Daily publication of the amendment order Monthly, Showa year (Voluntary) 6. Rancier subject to correction,” IJ corrected.
Claims (3)
かつこのＥＰＲＯＭ型集積回路素子上に紫外線に対して
透明な熱硬化性樹脂膜を有する半導体チップと、この半
導体チップをマウントするマウント材と、上記半導体チ
ップに接続されたリードと、上記熱硬化性樹脂膜の表面
の紫外線を入射する面を残して上記リードの一部ととも
に上記半導体チップを包囲するように封入した封入樹脂
とよシなる樹脂封止型半導体装置。(1) A semiconductor chip having an EPROM type integrated circuit element on a semiconductor substrate and having a thermosetting resin film transparent to ultraviolet rays on the EPROM type integrated circuit element, and a mounting material for mounting this semiconductor chip. , a lead connected to the semiconductor chip and an encapsulating resin that is encapsulated so as to surround the semiconductor chip together with a part of the lead, leaving a surface of the thermosetting resin film on which ultraviolet rays are incident. Resin-sealed semiconductor device.
特徴とする特許請求の範囲第１項記載の樹脂封止型半導
体装置。(2) The resin-sealed semiconductor device according to claim 1, wherein the thermosetting resin film is a polyimide resin film.
る工程と、上記ＥＰＲＯＭ型集積回路素子を形成した半
導体基板に紫外線に対して透明な熱硬化性樹脂を塗布し
て加熱することＫよ多熱硬化性樹脂膜を形成する工程と
、上記熱硬化性樹脂膜上において上記ＥＰＲＯＭ型集積
回路素子の領域にレジストパターンを形成しかつこのレ
ジストパターンをマスクとして上記熱硬化性樹脂膜をエ
ツチングするとともにこのエツチング後上記レジストパ
ターンを除去する工程と、上記半導体基板をスクライプ
して半導体チップに分割する工程と、との半導、体チツ
ゾをマウントア、イランドにマウントスるとともに上記
熱硬化性樹脂膜の紫外線入射部分を除いて封入但丁脂に
よシ封入する工程とよシなる樹脂封止型半導体装置の製
造方法。 （４Ｊ熱硬化性樹脂はポリイミド樹脂であることを特徴
とする特許請求の範囲第３項記載の樹脂封止型半導体装
置の製造方法。(3) The process of forming an EPROM type integrated circuit element on a semiconductor substrate, and applying a thermosetting resin transparent to ultraviolet rays to the semiconductor substrate on which the EPROM type integrated circuit element is formed and heating it. forming a curable resin film, forming a resist pattern on the thermosetting resin film in the area of the EPROM type integrated circuit element, and etching the thermosetting resin film using the resist pattern as a mask; After etching, the resist pattern is removed; the semiconductor substrate is scribed into semiconductor chips; A method for manufacturing a resin-sealed semiconductor device that is different from the step of encapsulating the incident part with a resin. (The method for manufacturing a resin-sealed semiconductor device according to claim 3, wherein the 4J thermosetting resin is a polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57194547A JPS5984448A (en) | 1982-11-08 | 1982-11-08 | Resin sealed type semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57194547A JPS5984448A (en) | 1982-11-08 | 1982-11-08 | Resin sealed type semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5984448A true JPS5984448A (en) | 1984-05-16 |
| JPH049381B2 JPH049381B2 (en) | 1992-02-20 |
Family
ID=16326346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57194547A Granted JPS5984448A (en) | 1982-11-08 | 1982-11-08 | Resin sealed type semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984448A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4894707A (en) * | 1987-02-12 | 1990-01-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a light transparent window and a method of producing same |
| US5037779A (en) * | 1989-05-19 | 1991-08-06 | Whalley Peter D | Method of encapsulating a sensor device using capillary action and the device so encapsulated |
| US5079190A (en) * | 1988-02-09 | 1992-01-07 | Canon Kabushiki Kaisha | Method of eliminating uneven refractive index in resin of a resin encapsulated photoelectric converting device |
| US5424249A (en) * | 1992-01-23 | 1995-06-13 | Mitsubishi Denki Kabushiki Kaisha | Method of making mold-packaged pressure sensing semiconductor device |
| US5622873A (en) * | 1994-01-24 | 1997-04-22 | Goldstar Electron Co., Ltd. | Process for manufacturing a resin molded image pick-up semiconductor chip having a window |
-
1982
- 1982-11-08 JP JP57194547A patent/JPS5984448A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4894707A (en) * | 1987-02-12 | 1990-01-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a light transparent window and a method of producing same |
| US5079190A (en) * | 1988-02-09 | 1992-01-07 | Canon Kabushiki Kaisha | Method of eliminating uneven refractive index in resin of a resin encapsulated photoelectric converting device |
| US5037779A (en) * | 1989-05-19 | 1991-08-06 | Whalley Peter D | Method of encapsulating a sensor device using capillary action and the device so encapsulated |
| US5424249A (en) * | 1992-01-23 | 1995-06-13 | Mitsubishi Denki Kabushiki Kaisha | Method of making mold-packaged pressure sensing semiconductor device |
| US5622873A (en) * | 1994-01-24 | 1997-04-22 | Goldstar Electron Co., Ltd. | Process for manufacturing a resin molded image pick-up semiconductor chip having a window |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH049381B2 (en) | 1992-02-20 |
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