JPS598351Y2 - Semiconductor wafer processing jig - Google Patents

Semiconductor wafer processing jig

Info

Publication number
JPS598351Y2
JPS598351Y2 JP6456578U JP6456578U JPS598351Y2 JP S598351 Y2 JPS598351 Y2 JP S598351Y2 JP 6456578 U JP6456578 U JP 6456578U JP 6456578 U JP6456578 U JP 6456578U JP S598351 Y2 JPS598351 Y2 JP S598351Y2
Authority
JP
Japan
Prior art keywords
wafer processing
processing jig
semiconductor wafer
semiconductor
jig
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6456578U
Other languages
Japanese (ja)
Other versions
JPS54167676U (en
Inventor
誠 今川
勇 長尾
哲郎 古川
和敏 天野
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP6456578U priority Critical patent/JPS598351Y2/en
Publication of JPS54167676U publication Critical patent/JPS54167676U/ja
Application granted granted Critical
Publication of JPS598351Y2 publication Critical patent/JPS598351Y2/en
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 この考案は半導体ウエハの処理治具にか・り、半導体ウ
エハの処理泊具を複数個連接して処理装置に内装するも
ので、この処理治具に支持した半導体ウエハ間の間隔を
処理装置の接続部を含め等しからしめた半導体ウエハの
処理治具の構造に関する。
[Detailed description of the invention] This invention is based on a semiconductor wafer processing jig, in which a plurality of semiconductor wafer processing fixtures are connected and installed inside the processing equipment, and the semiconductor wafers supported on this processing jig are The present invention relates to the structure of a processing jig for semiconductor wafers, in which the spacing between the processing equipment and the connecting portions of the processing equipment is made equal.

半導体装置の製造において、半導体ウエハにデポジショ
ン、酸化、拡散等を施すに第1図に一部を切欠して斜視
図示する処理装置が用いられる。
2. Description of the Related Art In manufacturing semiconductor devices, a processing apparatus shown in a partially cutaway perspective view in FIG. 1 is used to perform deposition, oxidation, diffusion, etc. on semiconductor wafers.

図において、1は石英で筒状に形或された炉芯管で、そ
の一端のノズル部11から反応ガス、一例の酸化性零囲
気ガスを流し、高温(例えば800〜1250℃)に保
った炉芯管内に配置された半導体ウエハ2(複数個の中
の1つを破線図示する)に上記ガスをあて、炉芯管の開
放口より排出する。
In the figure, reference numeral 1 indicates a cylindrical furnace core tube made of quartz, through which a reactive gas, an example of an oxidizing ambient gas, is flowed through a nozzle section 11 at one end, and maintained at a high temperature (e.g., 800 to 1250 degrees Celsius). The above gas is applied to the semiconductor wafers 2 (one of the plurality of wafers is shown by a broken line) placed in the furnace core tube, and is discharged from the open port of the furnace core tube.

上記半導体ウエハを炉芯管内の所定部分に配置するため
の半導体ウエハの処理治具3は、第2図に斜視図示する
如く、石英のロツドで細長くだ円型になるとともに半導
体ウエハの径より小なる間隔dの平行部分が長く形威さ
れ、かつ上記平行部分の上面に半導体ウエハを支持する
溝13.13′・・・・・・が形或されてなる。
The semiconductor wafer processing jig 3 for placing the semiconductor wafer in a predetermined portion within the furnace core tube is made of quartz rod and has an elongated oval shape and is smaller in diameter than the semiconductor wafer, as shown in a perspective view in FIG. The grooves 13, 13', . . . for supporting the semiconductor wafer are formed on the upper surface of the parallel portions.

また、上記処理治具における非平行部(両端部)は隣接
する処理治具の端部に支持された半導体ウエハとの間隔
を狭めるため、平面部ないし凹部23に形或される。
Further, the non-parallel portions (both end portions) of the processing jig are shaped into flat portions or concave portions 23 in order to narrow the distance between the semiconductor wafers supported by the ends of the adjacent processing jig.

次に第3図にウエハの処理装置におけるウエハの処理治
具3,3′の接続部の状況を断面図示する。
Next, FIG. 3 shows a cross-sectional view of the connecting portion of the wafer processing jigs 3 and 3' in the wafer processing apparatus.

図に示す如く、ウエハを挿入支持する溝によって半導体
ウエハ間の間隔が決定されるが、接続部は上記平面部ま
たは凹部23によって間隔の短縮がはかられるがなお処
理治具における半導体ウエハ間の間隔Dよりも大なる間
隔D′になる。
As shown in the figure, the distance between the semiconductor wafers is determined by the groove into which the wafers are inserted and supported, and although the distance between the semiconductor wafers in the processing jig is reduced by the flat portion or recess 23 at the connecting portion, The distance D' is larger than the distance D.

上記を実態につき説明する。The above will be explained in detail.

ウエハの処理治具は半導体ウエハの自動処理化、作業性
等を考えて、炉芯管の均熱長に比し短かいものが適用さ
れることが多い、これを使用して熱処理を行なう場合、
前記治具を複数個同時に載せるのに充分な石英製のボー
ト受け台(第1図4)に載せ炉芯管の均熱長に合わせて
ウエハ処理治具を直列に並べる。
In consideration of automatic processing of semiconductor wafers and workability, wafer processing jigs are often short compared to the soaking length of the furnace core tube.When performing heat treatment using these jigs, ,
The wafer processing jigs are placed on a quartz boat holder (FIG. 1, FIG. 4) that is large enough to hold a plurality of the jigs at the same time, and the wafer processing jigs are arranged in series according to the soaking length of the furnace core tube.

このように並べて熱処理を施すとき、処理治具の接続部
にて半導体ウエハ間の間隔が上述の如く大となり、これ
により処理ガスの流れが不均一になり、拡散不純物層に
むらを生じて均一な拡散が不可能になった。
When heat treatment is performed side by side in this way, the distance between the semiconductor wafers becomes large at the connection part of the processing jig as described above, which causes the flow of processing gas to become uneven, causing unevenness in the diffused impurity layer and making it difficult to maintain uniformity. diffusion has become impossible.

また一回に拡散処理を施す半導体ウエハの枚数が少ない
などの欠点があった。
Another disadvantage is that the number of semiconductor wafers that can be subjected to diffusion treatment at one time is small.

この発明は上記従来の欠点に対し、これを改良する半導
体ウエハの処理治具を提供するものである。
The present invention provides a semiconductor wafer processing jig that overcomes the above-mentioned conventional drawbacks.

この発明の半導体ウエハの処理治具は直列に並べて使用
するとき、この治具に支持されたウエハ間の間隔が治具
の接続部を含めて等しくなる特徴を有するものである。
The semiconductor wafer processing jig of the present invention is characterized in that when used in series, the distance between the wafers supported by the jig is equal, including the connection portions of the jig.

次にこの発明を一実施例の半導体ウエハの処理治具につ
き図面を参照して詳細に説明する。
Next, the present invention will be described in detail with reference to the drawings regarding an embodiment of a semiconductor wafer processing jig.

半導体ウエハにテ゛ポジション、酸化、拡散等を施すに
第4図に一部を切欠して斜視図示する処理装置が用いら
れる。
A processing apparatus shown in a partially cutaway perspective view in FIG. 4 is used to subject semiconductor wafers to processing such as positioning, oxidation, and diffusion.

図において、1は石英で筒状に形或された炉芯管で、そ
の一端のノズル部11から反応ガス、一例の酸化性零囲
気ガスを流し、高温(例えば800〜1250℃)に保
った炉芯管内に配置された半導体ウエハ2(複数個の中
の1つを破線図示する)に上記ガスをあて、炉芯管の開
放口より排出する。
In the figure, reference numeral 1 indicates a cylindrical furnace core tube made of quartz, through which a reactive gas, an example of an oxidizing ambient gas, is flowed through a nozzle section 11 at one end, and maintained at a high temperature (e.g., 800 to 1250 degrees Celsius). The above gas is applied to the semiconductor wafers 2 (one of the plurality of wafers is shown by a broken line) placed in the furnace core tube, and is discharged from the open port of the furnace core tube.

上記半導体ウエハを炉芯管内の所定部分に設置するため
の処理治具33は、第5図に斜視図示する如く、2本の
石英ロツド33 a ,33 a’を平行に固定し前記
炉芯管の軸線に平行に複数個33.33’,33″・・
・・・・連接装入する。
As shown in a perspective view in FIG. 5, the processing jig 33 for installing the semiconductor wafer in a predetermined portion within the furnace core tube fixes two quartz rods 33a and 33a' in parallel. Multiple pieces 33.33', 33'', parallel to the axis of
...Continuously charge.

そして上面に半導体ウエハを主面に対向せしめて支持す
るための溝43 .43′・・・・・・が形威されてな
る。
A groove 43 is provided on the upper surface for supporting the semiconductor wafer facing the main surface. 43'... is an expression of this.

次にこのウエハの処理治具の接続部における半導体ウエ
ハの位置関係を第6図により示す。
Next, the positional relationship of the semiconductor wafer at the connection portion of the processing jig for this wafer is shown in FIG.

図に示される如く、半導体ウエハを支持する溝間の間隔
Pは治具接続部間においても前記と同一の間隔Pになる
As shown in the figure, the interval P between the grooves that support the semiconductor wafer is the same as the interval P between the jig connection parts.

この考案にか・る治具を用い半導体ウエハで一例のボロ
ン、またはリンを含む不純物拡散源が塗着されたものを
装着し、拡散に好適する炉芯管温度に保持された炉芯管
内にて零囲気を炉芯管ノズルより導入された酸化性ガス
により形威してウエハの表面にデポジョンを施す。
Using a jig according to this invention, a semiconductor wafer coated with an impurity diffusion source containing boron or phosphorus is mounted inside a furnace core tube maintained at a temperature suitable for diffusion. Then, the zero atmosphere is shaped by oxidizing gas introduced from the furnace core tube nozzle to form a deposit on the surface of the wafer.

そして炉内におけるウエハの表面層抵抗分布を処理治具
の配置とともに第8図に示す。
FIG. 8 shows the surface layer resistance distribution of the wafer in the furnace together with the arrangement of processing jigs.

図に示される如く、きわめて高い均一度が得られている
が、従来の処理治具による一例を第7図に示す。
As shown in the figure, extremely high uniformity was obtained, and an example using a conventional processing jig is shown in FIG.

従来のものに比し炉芯管内における零囲気ガス流のむら
がないことがそのま・表面層抵抗値に表わされ、きわめ
て顕著な効果が認められた。
Compared to the conventional method, the uniformity of the ambient gas flow within the furnace core tube was reflected in the resistance value of the surface layer, and a very remarkable effect was recognized.

この考案は実施例に限定されることなく、広く半導体ウ
エハに対する気相反応に広く適用できる。
This invention is not limited to the examples, but can be widely applied to gas phase reactions on semiconductor wafers.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のウエハ処理治具が装入されている炉芯管
の一部を切欠して示す斜視図、第2図は従来のウエハ処
理治具の斜視図、第3図は従来のウエハ処理治具を説明
するための一部の断面図、第4図はこの考案にか・る一
実施例のウエハ処理治具が装入されている炉芯管の一部
を切欠して示す斜視図、第5図はこの考案の一実施例の
ウエハ処理治具の斜視図、第6図はこの考案の一実施例
のウエハ処理治具を説明するための一部の断面図、第7
図は従来のウエハ処理治具による効果を、また第8図は
この考案の一実施例のウエハ処理治具の効果を各々示す
図である。 なお図中同一符号は同一または相当部分を夫々示すもの
とする。 2・・・・・・半導体ウエハ、3u,3U’・・・・・
・ウエハ処理治具、43.43’・・・・・ウエハ処理
泊具の溝。
Fig. 1 is a partially cutaway perspective view of a furnace core tube into which a conventional wafer processing jig is inserted, Fig. 2 is a perspective view of a conventional wafer processing jig, and Fig. 3 is a perspective view of a conventional wafer processing jig. FIG. 4 is a cross-sectional view of a portion of the wafer processing jig for explaining the wafer processing jig. FIG. FIG. 5 is a perspective view of a wafer processing jig according to an embodiment of this invention, FIG. 6 is a partial sectional view for explaining the wafer processing jig according to an embodiment of this invention, and FIG.
The figure shows the effects of a conventional wafer processing jig, and FIG. 8 shows the effects of a wafer processing jig according to an embodiment of the invention. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 2... Semiconductor wafer, 3u, 3U'...
・Wafer processing jig, 43.43'...Groove of wafer processing jig.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 上面の溝に半導体ウエハを互に主面を対向させて整列支
持する半導体ウエハの処理治具を直列に複数個連接して
処理装置に内装し、支持した半導体ウエハ間の間隔を連
設した半導体ウエハの処理治具間の接続部を含め等しか
らしめた半導体ウエハの処理治具。
A semiconductor device in which a plurality of semiconductor wafer processing jigs are connected in series and arranged and supported in grooves on the upper surface with the semiconductor wafers aligned and supported with their main surfaces facing each other, and the gaps between the supported semiconductor wafers are set continuously. A processing jig for semiconductor wafers that is tightly sealed, including the connections between the wafer processing jigs.
JP6456578U 1978-05-16 1978-05-16 Semiconductor wafer processing jig Expired JPS598351Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6456578U JPS598351Y2 (en) 1978-05-16 1978-05-16 Semiconductor wafer processing jig

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6456578U JPS598351Y2 (en) 1978-05-16 1978-05-16 Semiconductor wafer processing jig

Publications (2)

Publication Number Publication Date
JPS54167676U JPS54167676U (en) 1979-11-26
JPS598351Y2 true JPS598351Y2 (en) 1984-03-15

Family

ID=28968796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6456578U Expired JPS598351Y2 (en) 1978-05-16 1978-05-16 Semiconductor wafer processing jig

Country Status (1)

Country Link
JP (1) JPS598351Y2 (en)

Also Published As

Publication number Publication date
JPS54167676U (en) 1979-11-26

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