JPS598350A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve element characteristic and realize high integration density by chaning thickness of field oxide film in accordance with the required element region. CONSTITUTION:High concentration impurities 7, 9 for element isolation and field oxide films 8, 10 by selective oxidation are provided. At this time, a thin field oxide film 10 is provided in the region from where crystal defect must be removed. Thereby, a high threshold value is given to a parasitic MOS transistor and a thick field oxide film is provided to the region where a small wiring capacitance must be given. This semiconductor device can be obtained by the steps that an oxide film 2, a nitride film 3, oxide films 4a, 4b for defining element regions are provided on a substrate 1, the nitride film 3 which is exposed while covering the cell region is removed by a photo resist 6. Thereafter, a thick field oxide film 8 is formed by the oxidation, the nitride film 3 is removed with the oxide films 4a, 4b used as the mask, and a thin field oxide film 10 can be obtained by oxidation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an element isolation method in a semiconductor integrated circuit device, and particularly relates to a MOS type semiconductor integrated circuit device.

The conventional device isolation method is known from Japanese Patent Publication No. 50-7425 or No. 52-9355, in which a highly concentrated impurity layer (guard ring impurity layer) of the same conductivity type as the substrate is formed on the main surface of the substrate, and the impurity is A gartling region is used in which a thick oxide film (field oxide film) that is self-aligned with the impurity layer is disposed on the layer using selective placement. In this method, the field oxide film and the guard ring impurity layer dig into the device region during selective oxidation, which is disadvantageous for ultra-high density integrated circuit devices. For example, CCD
The image sensor includes a photoelectric conversion photodiode section, a COD shift register section that transfers the signal charge photoelectrically converted by the photodiode to a detection circuit (these will be collectively referred to as a cell section), and the signal charge. In the peripheral circuit section, the reduction in the element area during the formation of the buried field oxide film can be countered by pattern design that takes this reduction into account in advance. In response to high integration, the above measures involve an increase in chip size in proportion to the increase in the number of cells. This situation is similar to Dynam jc -I (andom -Acce
The same goes for ss-Memory (D-RAM).

One way to solve this disadvantage is to make the field oxide film thinner, but simply making the field oxide film thinner uniformly over the whole chip will increase the capacitance between the circumferential wiring and the detour wiring and the substrate, and reduce the parasitic MOS transistor. This results in a decrease in the threshold value.

In view of such drawbacks, the present invention provides the following according to the required element area:
It is an object of the present invention to provide a highly integrated integrated circuit device with good multi-element characteristics by appropriately using the field oxide film thickness.

According to the present invention, in the area where it is desired to minimize the reduction of the element area and the crystal defects during field oxidation according to the prior art,
A thin field oxide film is used to reduce the capacitance between the electrode wiring and the substrate, increase the threshold of the parasitic MO8) transistor, and
By placing a thick field oxide film on the substrate and opposite conductivity type diffusion layer, which are the sources, drains, and interconnections of the OS transistor, in the areas where there is a thick core that increases the withstand voltage, good device characteristics can be achieved. This makes it possible to obtain an element that can be integrated easily and highly integrated.

For example, as explained in the examples below, in the cell part, in the CCD imaging device, there is no impurity diffusion layer of the opposite conductivity type to the substrate corresponding to the drain of the MO8 transistor, and in the -RAM, there is no impurity diffusion layer of the opposite conductivity type to the substrate, which corresponds to the drain of the MO8 transistor. When wiring is not done in the diffusion layer, the impurity concentration can be formed at a low level. Therefore, the guard ring impurity concentration can be increased, and a sufficient parasitic MO8) transistor threshold can be secured, so the field oxide film can be made thinner. The reduction in element area can be suppressed,
If the field oxide film buried in the substrate is thick, stress will be applied to the edges of the oxide film, causing crystal defects or large oxidation rusting stacking faults (0,8,F,).
Although leakage current is generated, thinning the field oxide film suppresses the generation of crystals and improves the charge retention characteristics of the cell portion.

On the other hand, by forming a thick field oxide film in the peripheral circuit section, a highly integrated circuit device with low wiring capacitance, high threshold voltage of parasitic MOS transistors, and high voltage resistance can be obtained.

Next, one embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows the cell section of the interrun CCDjl imager.
FIG. 7 is a plan view of a pattern defining an element area in an element limited to ×9 picture elements. In this figure, the shaded area corresponds to the element area, the inside surrounded by the dotted line represents the cell part, and the outside represents the peripheral circuit part. Regarding the AA' cross section in the figure,
2 to 8, the method of forming two types of folded oxide films according to LOCO8 in each manufacturing process in this embodiment will be explained.

As shown in FIG. 2, 50 OA of oxide wX2 was grown on one main surface of a P-type silicon substrate 1 with a specific resistance of 10 to 15 Ω, and a nitride film 3 of selective oxidation was grown in an atmospheric phase for 1500 Ω, and then After the grown oxide film 4 is deposited to a thickness of 200 OA, a photoresist pattern 5 defining an element region is formed by photolithography. Thereafter, the exposed vapor-grown oxide film is etched using a hydrofluoric acid-based or reactive sputtering device using the vagina photoresist material as a mask, and the photoresist mask material is removed to form the oxide film 4 shown in FIG. Pattern 4a,
Obtain the structure of 4b.

Next, as shown in FIG. 4, a photoresist pattern 6 covering the cell area is formed. The photoresist pattern is a pattern that covers the irradiated nitride film in the cell area surrounded by the dotted line in FIG. The entire produced nitride film is etched using a device, and the first guard ring impurity layer 7 is etched at 50KeV 2 × 101si.
It is formed by ion implantation of on/Cr/l teboron. Thereafter, the photoresist material is removed, and by selective oxidation, a thick first field oxide film 8, which will become a field oxide film in the peripheral circuit area, is grown to a thickness of 1 μm to obtain the structure shown in FIG.

Next, after etching the exposed nitride film using a plasma device as a mask material for the vapor grown oxide films 4a and 4bl, the second guard ring impurity layer 9 in the cell area is etched at 50KeV3X10.
The structure shown in FIG. 6 is obtained by ion-implanting boron with ion/7. It goes without saying that the boron ion-implanting dose can be set arbitrarily as required, separately from the first guard ring layer. stomach.

As shown in FIG. 7, after removing the mask materials 4a and 41) with a hydrofluoric acid-based etching solution, a thin second field oxide film, which becomes a cell area no-field oxide film, is formed using a selective oxidation method.
After 0OA growth, the nitride film of the mask material used for selective oxidation is removed with hot phosphoric acid etching solution.

Thereafter, as shown in FIG. 8, the oxide film 2 used as the pad oxide film of the mask nitride film is refreshed and etched to expose the substrate surface that will become the element region 1, and the gate oxide film is etched. The silicon gate MO8 type half-layer, CCDCD imaging is carried out in one process.

In this example, as shown in FIGS. 1 and 2, the device regions of the peripheral circuit section and the cell section were defined by seven photoresist etchings at one time. After forming the first field oxide film portion by simultaneously forming a photoresist pattern 6 in 4b shown in FIG. 4 without using the vapor-grown oxide film 4 as shown in FIG. Alternatively, a method may be used in which a pattern that completely covers the area corresponding to 4b is formed using a photoresist material to form the second field oxide film portion. If this method is used, there will be a misalignment of the eyes at the junction between the peripheral circuit part element area and the cell part element area (the part crossed by the dotted line in the diagonal area in FIG. 1) compared to the above embodiment. 1. 2nd
Since the photoresist material used as a mask material when forming the guard ring impurity layer is thick, boron ion implantation energy can be increased, and there is no oxide film removal process for the nitride film mask materials 4a and 41) shown in FIG. There are advantages such as no reduction in the first field oxide film.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a pattern defining an element area of a CCD imaging device according to an embodiment of the present invention, and FIGS. 2 to 8 are cross-sectional views of the pattern in this plan view. FIG. 4 shows a cross-sectional view during the manufacturing process in an example. In the figure, 1...semiconductor substrate, 2...
- Pad oxide film of nitride film for selective oxidation, 3... Selective oxidation mask nitride film, 4, 4a, 4b... Vapor phase growth oxide film, 5.6... Photoresist material, 7
．． 9...Represents the first and second guard ring impurity layers, respectively; 8.10...Represents the first and second field oxide films, respectively. 7 24-6"?1 .-, y"/Q '7" small q spear, 6
shi J 葎, 8 shi]

Claims (1)

[Claims] A highly concentrated impurity layer for element isolation is formed on the surface of the semiconductor, and selective oxidation is applied to the impurity layer! 7. In a semiconductor integrated circuit device in which a field oxide film is arranged and required elements are formed between the isolation layers, the field oxide film has a film thickness of at least 2 mm or more depending on the required area. A semiconductor integrated circuit device characterized by: