JPS598344A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS598344A
JPS598344A JP11752382A JP11752382A JPS598344A JP S598344 A JPS598344 A JP S598344A JP 11752382 A JP11752382 A JP 11752382A JP 11752382 A JP11752382 A JP 11752382A JP S598344 A JPS598344 A JP S598344A
Authority
JP
Japan
Prior art keywords
layer
type
semiconductor substrate
type semiconductor
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11752382A
Other languages
Japanese (ja)
Inventor
Sazuku Kamata
鎌田 授
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11752382A priority Critical patent/JPS598344A/en
Publication of JPS598344A publication Critical patent/JPS598344A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To remove a semiconductor product with a nonstandardized semiconductor substrate positively by making sure a resistivity value of a semiconductor substrate by a breakdown voltage value of a P-N junction. CONSTITUTION:An N<+> type buried layer 4 is formed to the P type semiconductor substrate 5, and N-type epitaxial growth layers 8 are formed onto the layer 4. P type layers 3 for isolating an element are formed to the eptaxial layers 8 so as to be surrounded at distances not joined with the N<+> type buried layer 4 while a P type semiconductor layers 3' is formed in an internal region of the layer 8 so as to join with the upper layer of the N<+> type buried layer 4. An electrode extracting port is formed to the upper surface of the P type semiconductor layer 3', and the layer 3' is wired by a metallic electrode 1. An external metallic wiring terminal A for testing characteristic is formed to the wiring 1. The breakdown voltage of the PN junction between the N<+> type buried layer 4 and the P type semiconductor substrate 5 is measured by applying positive voltage to the electrode section A. The resistivity value (impurity concentration) of the substrate 5 is inspected from the breakdown voltage value.

Description

【発明の詳細な説明】 本発明は半導体装置に係シ、特にP型半導体基板上にN
型エピタキシャル成長層が形成され、この表面に素子が
形成され製造される集積回路装置(以下、ICと称す)
、トランジスタに於いて、比抵抗値が所望の値と異った
前記P型半導体基板が使用され製品化されることを防ぐ
為の素子を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly relates to a
An integrated circuit device (hereinafter referred to as IC) in which an epitaxial growth layer is formed and elements are formed on the surface of the integrated circuit device (hereinafter referred to as IC).
, relates to a semiconductor device having an element for preventing the P-type semiconductor substrate having a specific resistance value different from a desired value from being used and manufactured in a transistor.

一般に、バイポーラ型ICの構造は第1図の様になって
いる。P型半導体基板5の上面にN+型半導体層が形成
された半導体基板上に、エピタキシャル成長によυN型
半導体層8が形成され、該N型半導体層上面に所望の素
子が形成される。上記半導体基板5は通常1〜20Ω−
cmの比抵抗値を持つものが使用されるが、これは製造
される製品の回路や特性によシ、それぞれ選定されて、
最適とされる比抵抗値の半導体が用いられる。
Generally, the structure of a bipolar IC is as shown in FIG. A υN type semiconductor layer 8 is formed by epitaxial growth on a semiconductor substrate having an N+ type semiconductor layer formed on the upper surface of the P type semiconductor substrate 5, and a desired element is formed on the upper surface of the N type semiconductor layer. The semiconductor substrate 5 is usually 1 to 20Ω-
A resistor with a specific resistance value of cm is used, but this is selected depending on the circuit and characteristics of the product being manufactured.
A semiconductor with an optimal resistivity value is used.

この様に多種類に区分された半導体基板を使用するに当
っては充分な管理が行われているが、時としてまったく
使用目的の異る規格の物や製造バラツキによる規格外の
物が混入することが発生する。比較的電流容量を必要と
するアナログIC等では、前記P型半導体基板は1〜1
0Ω−cm程度の比抵抗値の物が使用される。もしこの
半導体基板の中に10Ω−cm以上の高い比抵抗値の物
が入っでいると次の様な不具合を生ずることになる。。
Although sufficient management is carried out when using these various types of semiconductor substrates, sometimes products with completely different specifications for intended use or products outside the specifications due to manufacturing variations are mixed in. Something happens. In analog ICs etc. that require a relatively high current capacity, the P-type semiconductor substrate has 1 to 1
A material with a specific resistance value of about 0 Ω-cm is used. If this semiconductor substrate contains a substance with a high specific resistance value of 10 Ω-cm or more, the following problems will occur. .

先ず第1に前述した第1図の半導体装置構造□のI’C
で、N型エピタキシャル層8上面に形成された素子から
、P型半導体基板5に電流を流し込み該基板を通過した
後N型エピタキシャル層8上素子に流れる回路動作に於
いて、電流値、及び比抵抗値が大きい程、基板中での電
、圧降下が大きくなる。一般的には基板は最低電位とし
て使用されておシ、電圧降下分だけ最低電位が土ること
になる。
First of all, the I'C of the semiconductor device structure □ in FIG.
In the circuit operation, a current is caused to flow from the element formed on the upper surface of the N-type epitaxial layer 8 to the P-type semiconductor substrate 5, and after passing through the substrate, flows to the element on the N-type epitaxial layer 8. The greater the resistance value, the greater the voltage and voltage drop within the substrate. Generally, the substrate is used as the lowest potential, and the lowest potential is lowered by the voltage drop.

この結果回路上の電位分布が変動し回路機能が動作不良
となってしまう1゜ 第2の欠陥として例えば比抵抗が5Ω−Cnlと15Ω
−cmとでは不純物濃度は10分の1程度も低くなる。
As a result, the potential distribution on the circuit fluctuates and the circuit function malfunctions.1゜The second defect is, for example, when the specific resistance is 5Ω-Cnl and 15Ω.
-cm, the impurity concentration is about one-tenth lower.

この様な基板は素子を形成後ケースに組み込む際金属系
ソルダーを使用して半導体基板とケースとで合金化して
接着するが、この時半導体基板の表面にN型層が形成さ
れてしまう。この様な構造になるとN型エピタキシャル
成長層中に形成されるP型半導体層7から始って一エピ
タキシャル成長層8のN、P型半導体基板5のP、P型
半導体基板下面に出来るN型層とでPNPN構造による
寄生サイリスタ特性を生じ回路特性上重大な欠陥となっ
てしまう。
When such a substrate is assembled into a case after forming an element, a metal solder is used to alloy and bond the semiconductor substrate and the case, but at this time an N-type layer is formed on the surface of the semiconductor substrate. In such a structure, starting from the P-type semiconductor layer 7 formed in the N-type epitaxial growth layer, the N of one epitaxial growth layer 8, the P of the P-type semiconductor substrate 5, and the N-type layer formed on the bottom surface of the P-type semiconductor substrate. This causes parasitic thyristor characteristics due to the PNPN structure, resulting in serious defects in circuit characteristics.

以上の様な欠陥を持つ半導体装置は素子形成後行われる
特性試験で不良として完全に除去出来れば良いのである
が実際には使用される条件により、いろいろと異り特性
測定だけで除去するのは非常に困難で、製品となって外
部へ出て重大な不良発生になる恐れがあった。しかしな
がらこの種の半導体基板の規格外れ品の混入を防ぐ為、
基板を1枚1枚検査することは作業性の面から大変費用
がかかシ難ずかしいことであった。
It would be good if semiconductor devices with defects such as those mentioned above could be completely eliminated as defects through characteristic tests conducted after device formation, but in reality, they vary depending on the conditions under which they are used, and it is difficult to eliminate them only by measuring characteristics. It was extremely difficult to do so, and there was a risk that the product would be shipped outside and cause serious defects. However, in order to prevent the contamination of this type of semiconductor substrate with non-standard products,
Inspecting each board one by one is very expensive and difficult in terms of workability.

本発明の目的は、以上の様な欠点を防ぐ為に特性試験時
に確実に不良を除去することが可能な半導体装置を提供
することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which defects can be reliably removed during characteristic testing in order to prevent the above-mentioned drawbacks.

本発明の特徴は、第一導電型の半導体基板の上面に第二
導電型の半導体層を選択的に形成し、この半導体基板上
に第二導電型のエピタキシャル成長層を形成し、該エピ
タキシャル成長層に第一導電型の絶縁分離層を第二導電
型の半導体層と接合しない距離に囲む様に形成し、同時
に絶縁分離層と同じ第一導電型の半導体層を前記第二導
電型の半導体層の上層に接合するように形成し電極取υ
出し口を該半導体層上面に設けた半導体装置にある。
The present invention is characterized in that a semiconductor layer of a second conductivity type is selectively formed on the upper surface of a semiconductor substrate of a first conductivity type, an epitaxial growth layer of a second conductivity type is formed on the semiconductor substrate, and an epitaxial growth layer of a second conductivity type is formed on the semiconductor substrate of the first conductivity type. An insulating separation layer of a first conductivity type is formed so as to surround the semiconductor layer of a second conductivity type at a distance that does not contact the semiconductor layer, and at the same time, a semiconductor layer of the same first conductivity type as the insulating separation layer is formed between the semiconductor layer of the second conductivity type. Formed so as to be bonded to the upper layer.
A semiconductor device has an outlet provided on the upper surface of the semiconductor layer.

この様な素子を基板内に設けることによって特性試験時
に確実に不良を除去することが出来る。
By providing such an element in the substrate, defects can be reliably removed during characteristic testing.

以下、本発明の実施例を、第2図(a)、(b)を参照
にして説明する。先ず、P型半導体基板層5にN士型層
4を形成する。
Embodiments of the present invention will be described below with reference to FIGS. 2(a) and 2(b). First, the N-type layer 4 is formed on the P-type semiconductor substrate layer 5 .

次に、各N型エピタキシャル成長層8をこの上面に形成
する。該エピタキシャル成長層8に素子の絶縁分離の為
にP型半導体層3を前記N十型半導体層4に接合しない
距離に囲む様に形成する。
Next, each N-type epitaxial growth layer 8 is formed on this upper surface. A P-type semiconductor layer 3 is formed in the epitaxial growth layer 8 so as to surround it at a distance that does not contact the N0-type semiconductor layer 4 for insulation isolation of the elements.

同時にこの様に囲まれた内部領域に前記N++半導体層
4の上層と接合する様にP型半導体層3′を形成する。
At the same time, a P-type semiconductor layer 3' is formed in the inner region thus surrounded so as to be in contact with the upper layer of the N++ semiconductor layer 4.

そして該P復学導体層3′の上面に1極取り出し口を設
けて、金属電極1で配線する。この配線は特性試験が可
能な様に外1部金属配線端子Aを形成する。
A one-pole outlet is provided on the upper surface of the P return conductor layer 3', and a metal electrode 1 is used for wiring. This wiring forms an outer metal wiring terminal A so that a characteristic test can be performed.

PN接合の降服電圧は、各々の不純物濃度によシ異υ、
その値は一般的に知られている。この発明ではこの点を
利用したものである。P型半導体基板5に対して電極部
Aに正電圧を加えるとP型半導体層3′とN+型半導体
rf44とは順方向電圧であシ、N++半導体4とP型
半導体基板5とは逆方向電圧となる。この時の逆方向電
圧でのPN接合の降服電圧を測定する。絶縁分離層のP
型半導体層3とN型エピタキシャル成長層8の接合は逆
方向電圧も逆方向電圧になるが、PN接合の降服電圧値
は不純物濃度の高い程低い値となシ、ここではN+型型
溝導体層4P型半導体基板5との接合の降服電圧値が得
られる。N+型型溝導体層4不純物濃度は素子の特性と
して充分管理が可能であシ、P型半導体基板5の不純物
濃度に対応した降服電圧値を設定出来る。この様にして
P型半導体基板5の比抵抗値(不純物濃度)の確認をP
N+接合の降服電圧値により検査可能となる。
The breakdown voltage of the PN junction varies depending on the impurity concentration υ,
Its value is generally known. This invention takes advantage of this point. When a positive voltage is applied to the electrode part A with respect to the P-type semiconductor substrate 5, the P-type semiconductor layer 3' and the N+ type semiconductor rf44 have a forward voltage, and the N++ semiconductor 4 and the P-type semiconductor substrate 5 have a voltage in the opposite direction. voltage. At this time, the breakdown voltage of the PN junction at the reverse voltage is measured. P of insulating separation layer
The junction between the type semiconductor layer 3 and the N type epitaxial growth layer 8 also has a reverse voltage, but the breakdown voltage value of the PN junction becomes lower as the impurity concentration increases. The breakdown voltage value of the junction with the 4P type semiconductor substrate 5 is obtained. The impurity concentration of the N+ type trench conductor layer 4 can be sufficiently controlled as a device characteristic, and the breakdown voltage value corresponding to the impurity concentration of the P type semiconductor substrate 5 can be set. In this way, the specific resistance value (impurity concentration) of the P-type semiconductor substrate 5 can be confirmed by P.
Testing is possible based on the breakdown voltage value of the N+ junction.

以上の様な素子を設けて特性試験時に回路試験と同時に
検査が出来、規格外の半導体基板を持った半導体製品は
事前に除去することが出来、品質面や製造上大きな効果
を上げることが出来る。
By installing the above-mentioned elements, it is possible to conduct characteristic tests at the same time as circuit tests, and semiconductor products with non-standard semiconductor substrates can be removed in advance, which can greatly improve quality and manufacturing. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一般的に使用される半導体装置を示す断面図、
第2図(a)は本発明の実施例を示す半導体装置の断面
図、第2図(b)はその上面図である。 陶、図において、1・・・・・・金属電極、2・・・・
・・絶縁被膜、3.3’・・・・・P型半導体層、4・
・・・・・N″1半導体層、5・・・・・・P型半導体
基板、6・・・・・・N中型半導体層、7・・・・・・
P型半導体層、8・・・・・・N型エピタキシャル成長
層、A・・・・・・電極の外部取り出し金属配線部であ
る。 第1 図 草2 図
FIG. 1 is a cross-sectional view showing a commonly used semiconductor device.
FIG. 2(a) is a sectional view of a semiconductor device showing an embodiment of the present invention, and FIG. 2(b) is a top view thereof. In the figure, 1...metal electrode, 2...
...Insulating coating, 3.3'...P-type semiconductor layer, 4.
...N''1 semiconductor layer, 5...P type semiconductor substrate, 6...N medium semiconductor layer, 7...
P-type semiconductor layer, 8...N-type epitaxial growth layer, A...metal wiring portion for taking out the electrode to the outside. 1st figure grass 2 figure

Claims (1)

【特許請求の範囲】[Claims] 第一導電型の半導体基板の上面に第二導電型の半導体層
が選択的に形成され、該半導体基板上および該第二導電
型の半導体層上に第二導電型q・エピタキシャル成長層
が形成され、該エピタキシャル成長層に第一導電型の半
導体層が絶縁分離層として前記第二導電型の半導体層と
接合しない距離に囲む様に形成され且つ該内部領域へ前
記第二導電型半導体層の上層と接合するように形成され
て電極域シ出し口が該半導体層上面に設けられているこ
とを特徴とする半導体装置。
A semiconductor layer of a second conductivity type is selectively formed on the upper surface of the semiconductor substrate of the first conductivity type, and a q-epitaxial growth layer of a second conductivity type is formed on the semiconductor substrate and the semiconductor layer of the second conductivity type. , a first conductivity type semiconductor layer is formed as an insulating separation layer in the epitaxial growth layer so as to surround the second conductivity type semiconductor layer at a distance that does not contact the second conductivity type semiconductor layer, and an upper layer of the second conductivity type semiconductor layer is formed in the inner region. 1. A semiconductor device, characterized in that the semiconductor layer is formed so as to be bonded to each other, and an electrode area outlet is provided on the upper surface of the semiconductor layer.
JP11752382A 1982-07-06 1982-07-06 Semiconductor device Pending JPS598344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11752382A JPS598344A (en) 1982-07-06 1982-07-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11752382A JPS598344A (en) 1982-07-06 1982-07-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS598344A true JPS598344A (en) 1984-01-17

Family

ID=14713879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11752382A Pending JPS598344A (en) 1982-07-06 1982-07-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS598344A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0421415U (en) * 1990-06-12 1992-02-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0421415U (en) * 1990-06-12 1992-02-24

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