JPS5980014A - Arithmetic device of space filter - Google Patents

Abstract

PURPOSE:To obtain an arithmetic device of high performance with a simple constitution by providing an arithmetic circuit which uses plural multipliers to perform simultaneously the processing for coefficients of adjacent filters and the addition processing with the result of the preceding processing. CONSTITUTION:The original picture data Gi and (j) are latched by original picture data latches 5A and 5B; and at the same time the 1st and the 2nd filter coefficient data are latched by coefficient data lathes 5C and 5D respectively. Then the output of the processed picture data latch 50 supplied via a data bus line l12 is multiplied 5F by the output of the latch 5A. At the same time, the output of the latch 5D supplied via the line l12 is multiplied 5G by the output of the latch 5B. These outputs of multipliers 5F and 5G added 5H together, and the output of the addition 5H is added 5I to the output of a latch 5E supplied via the line l12. As a result of this addition result, the picture data is latched 5J. In such a way, it is possible to obtain an arithmetic device of space filter with which the address control is easy with a high processing speed and high general-purpose properties.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a spatial filter calculation device that processes original image data to perform image enhancement, image sharpening, and the like.

[Technical background of the invention and its problems]

Spatial filter calculation means, for example, that matrix Fk, Z as a spatial filter function shown in equation (2) is applied to the original image matrix Gi, j shown in equation (1) to obtain matrix R shown in equation (3).
This is an operation to obtain 4,j.

Here, Ri,j is expressed by the following equation (4).

By the way, the conventional spatial filter arithmetic device has only one multiplier, and the processing unit Ri, j4fi of the original image is
Since the l- calculation was performed, the setting of memory addresses and timing relationships were complicated (I), and the calculation time became long.

[Purpose of the invention]

The purpose of the present invention is to provide a spatial filter arithmetic device having a simple configuration, easy address control, and improved processing speed and versatility. It is something to do.

[Summary of the invention]

Hehe An arithmetic circuit comprising a plurality of multipliers that perform predetermined spatial filter multiplication on the Asahihara image data C2, and a second adder that adds the outputs of each multiplier. It is.

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a 6×3 filter calculation device.

In the figure, reference numeral 1 denotes a filter calculation device 1], which is composed of a calculation control section 1A, an original image memory 6, and first and second working memories 7.8.

One arithmetic controller has the first to sixth address generation circuits 2 to 6.
4, an arithmetic circuit 5, a pass line selector 9, and a central processing control unit (CPU) 11 that includes an external control section 12, an internal control section 13, and a control signal generation circuit 10. , an address bus line 1 is provided between each of the address generation circuits 2 to 4 and each of the memories 6 to 8.
1~j! 3 are provided, and data bus lines 1.3 are provided between each of the memories 6 to 8 and the pass line selector 9. 17 are provided [ ], and data bus lines 18 to 17 are provided between each address generation circuit 2 to 4 and the pass line selector 9.
11° is provided, and furthermore (nibus line selector 9
and the arithmetic circuit 5 are data bus lines 11, -11.
3 is provided. The operation of the pass line selector 9 is controlled by a control signal from a control signal generating circuit 10 within the CPU 11. Said CPU
A control signal generation circuit 10 is provided in the area 11.
~Control signals 81 to S3 for third address generation circuits 2 to 4
．． Control signals 84-S for each memory 6-8, control signal S7 for arithmetic circuit 5, control signal S8 for bus line selector 9. The control signal S9 of the external control section 12 is outputted respectively. By the way, the original image memory 6 (= is provided with a filter coefficient storage section 6A and a coefficient data path line 114, and is read out by the control signal SIO from the control signal generation circuit 10 in the CPU 11; , 4 to the pass line selector 9 side.An example of the stored filter coefficient F is as shown in the following equation (5).

In other words, 6 stages (divided into two, the first stage is the first
Third coefficient Fil~F'13. @2nd row is 4th to 6th
The coefficients F21 to F23. The 6th row is the 7th to 9th coefficients F
31 to F33), the control signal SIO from the control signal generation circuit 1o generates a new value every time the filter is calculated by combining the two coefficients that match the @number or the coefficient with "0". It looks like it will be taken out and processed.

For example, in the first filter calculation, r, Fl, J, and "F12" are used, and in the second filter calculation, "F13" and "10" are used.
In the third time, the two coefficients are processed as "I21" (and "F22"...) and are based on the combination of the ninth coefficient "F33" and "0". When the calculation process is completed, the filter calculation is terminated.

FIG. 2 is a block diagram of one embodiment of the arithmetic circuit 5.

This circuit includes first and second original image data latches 5A, 5'B that latch original image data Gi, j input via data bus line '11, and data bus line 1□
The first and second fill coefficient data input through the first and second filters are latched through the first and second filters.゛Second coefficient data latch 5C
, 5D and the output of a processed image data latch latch 5C that latches processed image data that is also input via the data bus line 112.
F, a second multiplier 5G that multiplies the output of the second original gi+1 image data latch 5B and the output of the second coefficient data latch 5D, and the outputs of the first and second multipliers 5F and 5G. A first adder 5H that adds together, and a second adder 5■ that adds the output of the processed image data latch 5E in which the processed image data is latched and the output of the trace 1 adder 5H.
and an image take latch 5J that latches the addition result image take.

FIG. 6 is a circuit diagram showing an example configuration of the control signal generating circuit 10. In FIG. This circuit is connected to the control path line 118
A sequencer 10A that executes instructions input from the CPU by intervening with the CPU, and an address area IDB1. The first system having a sequence program area 10B2? M+ memory 10B, a first register 1[]C, a second control memory 10D storing control data for various circuits controlled by the output of this circuit for each area, and a second register. The sequence data is transmitted from the first register 10C to the pass line 1□
2 to the sequencer 10A, and the stored contents of the second control memo IJ10D are such that, for example, areas A, -A3 are fed back to the sequencer 10A through the first to sixth address generation circuits 2 to 6. Area A4 is control data for original image memory B, area A5 is control data for first working memory 7, area A6 is control data for second working memory 8, and area A7 is control data for arithmetic circuit 5. data, area A8 is the control data of the pass line selector, area A9 is the control area AIO of the external control part 1, which stores the coefficient data ('@6A's control data is stored), and the control signal is sent via the register 10E. 81 to S1o.

The operation of the device will be explained.

In the control signal generation circuit shown in FIG. 6, the sequencer 10A operates in accordance with the command C2 sent from the CPU 11 main body via the pass line 41B, and accesses the first control memory 10B via the pass line f19. The address data and sequence program of the second control memory are stored in the first control memory 10B, and the program and address signal required for filter calculation processing are selected based on the output from the sequencer. Pass line 120
is output to register 10C via. The sequence program area is fed back to the sequencer IOA and used as a timing take, and the address data is sent to the second control memory 10D via the register 10C. Such address data (therefore the second control memo'j
Control signals for the control system necessary for filter calculation processing stored in 10D are selected and output for each area.This control signal is supplied to each control system via register 1[]E. The circuit shown in Figure 1, which is controlled by the output of the control signal generating circuit 10, performs the following operations.

First, the pass line selector 9 is operated by the control signal S8, and the input data bus line 5 of the original image memory 6 and the input data bus line 5 of the arithmetic circuit 5 are selected. il, and also connects the coefficient data bus line\ and the input data bus line 112 of the arithmetic circuit 5, and further connects two consecutive data bus lines via the data bus line of the first working memory 7. The filter coefficients F1□F1□ are sequentially sent out and sequentially stored in the first working memory 7 (-) via j6 in the arithmetic circuit 5 as will be described in detail later. The input data bus lines 1 and 2 of the negative circuit 5 are connected to the data bus line f6 and the coefficient data bus line 1.4 which are connected to the working memory 7 of the parallel 1, and the deba data bus line '1 of the arithmetic circuit 5 is connected.
3 and the data bus line 17 connected to the second working memory 8 (second connection wire '1) are connected. In this state, the coefficient F12 and "DJ" are sequentially read out from the coefficient data storage section 6A, and the coefficient The data is sent out via the data bus line "14" and the input data bus line 112 of the performance circuit 5, and is subjected to a second filter operation process in the arithmetic circuit 5. The image data in the working memory Z is captured into the arithmetic circuit 5, and the captured image data and the filter arithmetic processing result are added and stored in the second working memory 8 via the data bus lines 113 and 17. Thereafter, by the operation of the pass line selector 9, the data bus line 17 connected to the second working memory 8 and the input catator bus line !1□ of the arithmetic circuit 5 are connected. .2 is also connected to the coefficient data bus line 114), and the output data bus line J13 of the arithmetic circuit 5 is connected to the data bus line f6 connected to the first working memory 7. In this state, filter coefficient F2
11 F22 i2 Performs predetermined filter calculation processing, and then "! Consequential theta and second working memory 8
The data read from and extracted from the data are added together and stored in the first working memory Z.

The following sequential filter coefficients F23. rOJ, F3□, F
3□.

F33. [[Each calculation process based on IJ+2 and the previously processed data are added each time, and the first... Second
Working memory (storing two).

Next, details of the operation of the arithmetic circuit 5 will be explained with reference to the block diagram of FIG. 2 and the time charts of FIGS. 4 to 9.

First, two filter coefficients F1□ and F1□ are sequentially latched in coefficient data latches 5C and 5D, and original image data Gi,
j is latched in the original image latches 5A and 5B in address order. -, multipliers 5F, 5G and adders 5H, 511
Therefore, the calculation shown in the following equation (6) is performed, and after being latched in the latch 5J, it is stored in the first working memory 7 as described above.

rli, j=F11·Gtj+F, -G1. j+1−・
-(6) This process is performed on all the original 11111 image data (Figure 4).

Next, the filter coefficient F130 is latched to the latches 5C and 5Dζ, and the original image data Gi and j are latched to the latches 5A and 5B in address order, and -ni+processing'fi+r
Data r1 of the first working memory 7 stored as
After latching i and J in the latch 5E and performing the calculation of the following equation (7), the result is latched in the latch 5J and stored in the second working memory 8.

r2i, j=F'13・Gi, j+2〇−Gi, j
+3+rlilj - (7) This process is performed on all the original image data (two pieces (FIG. 5)).

Next, filter coefficients F21jF'22 are latched 5C, 5
D with l1lt' primary latch-C (2. Latch the original image data G5j, latch the data r2i, J stored in the second working memory 8 with the latch 5E,
The following equation (8) is calculated, and the working memory 7 (2) of the deferred payment 1 latched in the latch 5J is stored.

r3i,j = F21 ・Gr + 1+J 10F2
2・IC+ +1+j + l +r21 +J...
・・・・・・(8) Perform this process for all original image data (Figure 6)
.

Next, filter coefficients 1i'23.0 are latched 5C and 5D.
and latches the original image data Gij.
5B, the first working memory 7 ('--stored data r3j, j is latched into the latch 5E,
The calculation of the following equation (9) is performed, and the result is stored in the working memory 8 of the deferred payment 2, which is latched in the latch 5J.

r4i, j-F23""'+j+200"Gj+Lj+
3+r3i,j - (9) This process is performed for all original image data (FIG. 7).

Latch the C-order filter coefficients F3□, F3□ 5C, 5D
When latched to Cf, original image data i, J latch 5
A.

5B, the data r41tJ stored in the second working memory 8 is latched in the latch 5E, the calculation of the following equation (10) is performed, and the result is latched in the latch 5J. 2. Store.

rs i+j = F31 ・Gt+z, j+F32
・C++z, j+1+r4 i, j ・−(
to) This process is performed on all the original image data C (FIG. 8).

Finally, the second filter coefficient F3310 is latched to the latches 5C and 5D, and the original image data Gj and J are latched to the latches 5A.
, 5B, the data rsLj stored in the first working memory 7 is latched to the latch 5E, the following formula α1) is calculated, and the result is latched to the latch 5J. Store in.

r6;, j =F3'3·Gi+2. j+2+()Gi
+2. j+3+r5i, j・・・・・・・・・・(n) This process is performed for all the original image data (double and one) (9th
figure).

As a result, the above equation (11) becomes the processed data Rt,j expressed by the following equation (12).

Ri * j= Fu・Gt, j 1 F1□・Gi, J+
10F13・Qi, j+20F'21-Gi+1.
j+F2z・Gi+1. j+10F23・Gi+11j
+2+F31・Gi+2, j+F3□・c++z
, j+1+F33・Gi+2. j+2
・・・・・・・・・(Iwa, that is,
This means that 3×6 filter calculation processing has been performed.

Although the above embodiment shows the case of a 3x6 filter operation, it goes without saying that filter operations such as 5X5, 7X7, etc. (2) can also be applied.In particular, when the number of multipliers is increased, If the number of latches is increased and parallel processing is performed on coefficients that match Ni1, the processing speed can be further improved.

〔Effect of the invention〕

According to the present invention as described in detail above, an arithmetic circuit is provided that uses a plurality of multipliers to perform processing for adjacent filter coefficients and addition processing for the results of the previous processing in parallel. It is possible to provide a filter arithmetic device with a simple configuration, easy address control, and improved processing speed. Also, the size of the spatial filter coefficient (or function) is 3x
3.5 x 5.7 x 7, etc.), it is possible to provide a device with excellent versatility.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention applied to a 6×6 filter arithmetic device, FIG. 2 is a block diagram showing an example of the configuration of an arithmetic circuit used therein, and FIG.
This figure is a block diagram showing an example of the control signal generation circuit in FIG. 1, and FIGS. 4 to 9 are time charts for explaining the operation of the apparatus of the present invention. 1...Filter arithmetic device, 1A...Arithmetic unit, 2
~4...Address generation circuit, 5...Arithmetic circuit,
6... Original image memory, 7.8... Working memory, 9... Pass line selector, 10... Control signal generation circuit, 11... Central processing control unit, 5A,
5B, 5C. 5D, 5E, 5J...Latch, 5F', 5G
...Multiplier ν, 5H, 5I...Adder, 10A・
...Sequencer, IDB...first control memory, '
1[]D...Second control memory, ioc, 1
0E...Register. Funeral 2 Figure Funeral 3 Figure S+ 52 Fable S White Kaa ------5OSn Figure 6

Claims (1)

[Claims] Ma) '%' to the spatial filter coefficients arranged in IJ box shape.
In a device that performs a predetermined spatial filter operation on original image data, a plurality of multiplications are performed in which a plurality of adjacent 1] matching filter coefficients and original image data are sequentially input and each is multiplied. A spatial filter arithmetic device characterized by providing an arithmetic circuit consisting of a second adder for each multiplier and a second adder for each multiplier.